JP2012103385A - Electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device equipped with a transistor and having a high definition pixel, and an electronic apparatus equipped with the electro-optic device.SOLUTION: The pixel P of an electro-optic device includes: a scan line 3a that extends in a first direction (X direction); a data line 6a extends in a second direction (Y direction) that crosses the scan line 3a; and a thin film transistor 30 that is electrically connected with the scan line 3a and data line 6a. The thin film transistor 30 is located so as to overlap the crossing of the scan line 3a and data line 6a in a planar fashion. The thin film transistor 30 includes: a semiconductor layer 30a having a drain region 30a5 that extends in the X direction, a source region 30a1 that extends in the Y direction, and a channel region 30a3 including a first extension part extending in the X direction and a second extension part extending in the Y direction; and a gate electrode part 30g opposing the channel region 30a3.

Description

  The present invention relates to an electro-optical device including a transistor as a switching element of a pixel, and an electronic apparatus including the same.

  As the electro-optical device, an electric device including a transistor having a semiconductor layer in which a source region and a channel region are arranged along a data line at an intersection of a data line and a scanning line and a drain region is bent along the scanning line. An optical device is known (Patent Document 1).

  According to the electro-optical device of Patent Document 1, since the semiconductor layer is bent halfway compared to the case where the semiconductor layer is linearly arranged along the data line or the scanning line, the data line or the scanning line is aligned. The size of the direction transistor can be reduced. Accordingly, an electro-optical device including a transistor can be realized even when the pixel arrangement pitch is small and high definition is achieved.

JP 2010-78840 A

  However, there is a demand for further increasing the number of pixels in the electro-optical device. Therefore, there is a problem in that it is desired to arrange a transistor having a predetermined characteristic for each pixel even when the pixel arrangement pitch is finer.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An electro-optical device according to this application example includes a scanning line extending in a first direction, a data line extending in a second direction intersecting the scanning line, the scanning line, and the data line. A transistor provided corresponding to the intersection and electrically connected to the scan line and the data line, the transistor including a first source / drain region extending in the first direction; Provided between the second source / drain region extending in the second direction and the first and second source / drain regions, so as to planarly overlap the intersection of the scanning line and the data line. A semiconductor layer provided and having a channel region including a first extension portion extending in the first direction and a second extension portion extending in the second direction; and a gate facing the channel region Having an electrode portion, and having And features.

  According to this configuration, the first direction (the extending direction of the scanning line) or the second direction (the extending direction of the data line) is compared with the case where the first or second source / drain region other than the channel region is bent. The dimension of the channel region can be substantially shortened, and the transistor can be arranged for each pixel even when the pixel arrangement pitch becomes finer than the conventional arrangement. That is, an electro-optical device having high-definition pixels that can be switched by a transistor can be provided. Further, conventionally, it has been natural to secure predetermined electrical characteristics by making the length of the channel region constant. In other words, there has been no idea of bending the channel region. However, as the pixel becomes higher in definition, the semiconductor layer needs to be downsized. If the pixel is downsized, variations in electrical characteristics due to bending of the channel region can be ignored. That is, a more preferable arrangement of the semiconductor layer in the high-definition pixel can be realized.

Application Example 2 In the electro-optical device according to the application example described above, a pixel electrode provided corresponding to the transistor is provided, and one of the first and second source / drain regions is electrically connected to the pixel electrode. And the other is electrically connected to the data line, is provided on both sides of the semiconductor layer in a plane along the one source / drain region, and electrically connects the scanning line and the gate electrode portion. A side wall portion having a light-shielding conductive film provided to extend from the gate electrode portion in the contact hole to be electrically connected, and the channel region has a length of the first extension portion in the first direction Of the lengths of the second extending portions in the second direction, the length on the one source / drain region side is preferably shorter than the length on the other source / drain region side.
According to this configuration, of the first and second source / drain regions connected to the channel region, one of the source / drain on the side electrically connected to the pixel electrode effective for preventing the occurrence of light leakage current The length on the region side is shorter than the other. Therefore, the length of the portion along the semiconductor layer of the light-shielding side wall provided on both sides of the semiconductor layer in a planar manner can be reduced. Therefore, it is possible to suppress an increase in the area of the light shielding region due to the provision of the side wall portion, and it is possible to suppress a decrease in the aperture ratio even if the side wall portion is provided in order to prevent the occurrence of light leakage current in the transistor.

Application Example 3 In the electro-optical device according to the application example described above, an LDD region is provided between the channel region and the first and second source / drain regions, and is provided on both sides of the semiconductor layer. It is preferable that at least one of the side wall portions is provided along the channel region and the LDD region.
According to this configuration, since the light is shielded by the side wall provided along the channel region and the LDD region, generation of light leakage current in the transistor can be further reduced.

Application Example 4 In the electro-optical device according to the application example described above, it is preferable that the light shielding region including the gate electrode portion is arranged symmetrically with respect to the scanning line and the data line.
According to this configuration, the shape of the opening portion of the adjacent pixel is symmetric with respect to the scanning line and the data line, so that a high-definition pixel that is not easily affected even if the visual characteristics in the optical design are biased. Can be provided.

Application Example 5 An electronic apparatus according to this application example includes the electro-optical device according to the application example described above.
According to this, even if it has a high-definition pixel, desired electro-optical characteristics can be obtained, and an electronic device capable of displaying with good appearance can be provided.

(A) is a schematic plan view which shows the structure of a liquid crystal device, (b) is a schematic sectional drawing cut | disconnected by the H-H 'line | wire of (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. (A) is a schematic plan view showing the configuration of the pixel of Example 1, (b) is a schematic plan view showing the configuration of the thin film transistor, and (c) is a schematic plan view showing the configuration of the storage capacitor. FIG. 3 is a schematic plan view illustrating the arrangement of pixels according to the first exemplary embodiment. FIG. 4 is a schematic cross-sectional view illustrating a structure of a pixel cut along a B-B ′ line in FIG. FIG. 4 is a schematic cross-sectional view showing the structure of a pixel taken along line C-C ′ in FIG. FIG. 6 is a schematic plan view illustrating a configuration of a pixel according to Embodiment 2. FIG. 6 is a schematic plan view illustrating the arrangement of pixels according to the second embodiment. (A) is a schematic plan view showing the configuration of the pixel of Example 3, (b) is a schematic plan view showing the configuration of the semiconductor layer of Example 3, and (c) is an arrangement of capacitor lines, relay electrodes, and capacitor electrodes. FIG. FIG. 10 is a schematic cross-sectional view illustrating a structure of a pixel cut along a line D-D ′ in FIG. 9. Schematic which shows the structure of the projection type display apparatus as an electronic device.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

(First embodiment)
In the present embodiment, an active matrix liquid crystal device as an electro-optical device including a thin film transistor (TFT) as a pixel switching element will be described as an example. This liquid crystal device can be suitably used as, for example, a light modulation element (liquid crystal light valve) of a projection type display device (liquid crystal projector) described later.

<Liquid crystal device>
First, a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to FIGS. 1 and 2. 1A is a schematic plan view showing the configuration of the liquid crystal device, FIG. 1B is a schematic cross-sectional view taken along line HH ′ of FIG. 1A, and FIG. 2 is an electrical configuration of the liquid crystal device. FIG.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are disposed to face each other, and a liquid crystal layer 50 that is sandwiched between the pair of substrates. . As the element substrate 10 and the counter substrate 20, a transparent glass substrate such as quartz is used.

  The element substrate 10 is slightly larger than the counter substrate 20, and both substrates are bonded via a seal material 40 arranged in a frame shape, and liquid crystal having positive or negative dielectric anisotropy is sealed in the gap. A liquid crystal layer 50 is formed. For the sealing material 40, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. A spacer (not shown) is mixed in the sealing material 40 to keep the distance between the pair of substrates constant.

  A light shielding film 21 is similarly provided in a frame shape inside the sealing material 40 arranged in a frame shape. The light shielding film 21 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding film 21 is a display region E having a plurality of pixels P. Although not shown in FIG. 1, the display area E is also provided with a light-shielding portion that divides a plurality of pixels P in a plane.

A data line driving circuit 101 is provided between the element substrate 10 and the sealing material 40 along one side. Further, an inspection circuit 103 is provided inside the sealing material 40 along the other one side facing the one side. Further, a scanning line driving circuit 102 is provided inside the sealing material 40 along the other two sides orthogonal to the one side and facing each other. A plurality of wirings 105 that connect the two scanning line driving circuits 102 are provided inside the sealing material 40 on the other side facing the one side. Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged along the one side.
Hereinafter, the direction along the one side will be referred to as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other will be described as the Y direction.
The arrangement of the inspection circuit 103 is not limited to this, and the inspection circuit 103 may be provided at a position along the inner side of the sealing material 40 between the data line driving circuit 101 and the display area E.

  As shown in FIG. 1B, on the surface of the element substrate 10 on the liquid crystal layer 50 side, a light-transmitting pixel electrode 15 provided for each pixel P and a thin film transistor (TFT; Thin Film) as a switching element. Transistor) 30, signal wiring, and an alignment film 18 covering these are formed.

  On the surface of the counter substrate 20 on the liquid crystal layer 50 side, a light shielding film 21, an interlayer film layer 22 formed so as to cover the light shielding film 21, and a common electrode 23 provided so as to cover the interlayer film layer 22 are shared. An alignment film 24 covering the electrode 23 is provided.

  As shown in FIG. 1A, the light shielding film 21 is provided in a frame shape at a position where the data line driving circuit 101, the scanning line driving circuit 102, and the inspection circuit 103 overlap in plan view. Thus, the light incident from the counter substrate 20 side is shielded, and the malfunction of the peripheral circuits including these drive circuits due to the light is prevented. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

  The interlayer film layer 22 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the light shielding film 21 with light transmittance. Examples of a method for forming such an interlayer film layer 22 include a method of forming a film using a plasma CVD method or the like.

  The common electrode 23 is made of, for example, a transparent conductive film such as ITO, and covers the interlayer film layer 22 and, as shown in FIG. 1A, the element substrate 10 side by the vertical conduction parts 106 provided at the four corners of the counter substrate 20. It is electrically connected to the wiring.

  The alignment film 18 covering the pixel electrode 15 and the alignment film 24 covering the common electrode 23 are selected based on the optical design of the liquid crystal device 100. For example, an organic material such as polyimide is formed, and the surface thereof is rubbed so that liquid crystal molecules are subjected to a substantially horizontal alignment treatment, or an inorganic material such as SiOx (silicon oxide) is vapor-phase grown. And a film formed by a method and aligned substantially perpendicularly to liquid crystal molecules.

As shown in FIG. 2, the liquid crystal device 100 is disposed so as to be parallel to the plurality of scanning lines 3 a and the plurality of data lines 6 a as signal lines that are insulated and orthogonal to each other at least in the display region E along the data lines 6 a. Capacitance line 3b.
The direction in which the scanning line 3a extends is the X direction (first direction), and the direction in which the data line 6a extends is the Y direction (second direction).

  A pixel electrode 15, a TFT 30, and a storage capacitor 16 are provided in a region divided by the scanning line 3a, the data line 6a, the capacitor line 3b, and these signal lines, and these constitute a pixel circuit of the pixel P. is doing.

The scanning line 3 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the source of the TFT 30. The pixel electrode 15 is electrically connected to the drain of the TFT 30.
The data line 6a is connected to the data line driving circuit 101 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 101 to the pixels P. The scanning line 3a is connected to a scanning line driving circuit 102 (see FIG. 1), and supplies scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 102 to each pixel P. The image signals D1 to Dn supplied from the data line driving circuit 101 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 102 supplies the scanning signals SC1 to SCm to the scanning line 3a in a pulse-sequential manner at a predetermined timing.

In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 15 at a predetermined timing. It is the structure written in. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 50 via the pixel electrode 15 is held for a certain period between the pixel electrode 15 and the common electrode 23 arranged to face each other via the liquid crystal layer 50. The
In order to prevent the held image signals D1 to Dn from leaking, the holding capacitor 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the common electrode 23. The storage capacitor 16 is provided between the drain of the TFT 30 and the capacitor line 3b. As will be described in detail later, the storage capacitor 16 has a dielectric layer between the light-shielding first electrode and the second electrode, and the second electrode constitutes the capacitor line 3b. . The capacitor line 3b is connected to a fixed potential. The fixed potential is, for example, a common potential (LCCOM) applied to GND or the common electrode 23.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG. The inspection circuit 103 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

  Such a liquid crystal device 100 is a transmission type, and adopts an optical design of a normally white mode in which the pixel P is brightly displayed when not driven and a normally black mode in which the pixel P is darkly displayed when not driven. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  The liquid crystal device 100 can display with high definition by increasing the number of pixels P. On the other hand, when the planar size (size) of the pixel P is reduced, the size and arrangement of the TFT 30 in the pixel circuit are reduced. Will also be limited. The inventors have developed a configuration of the TFT 30 that can obtain desired electrical characteristics such as switching characteristics even when the pixel P becomes high definition. Hereinafter, examples will be described.

Example 1
3A is a schematic plan view showing the configuration of the pixel of Example 1, FIG. 3B is a schematic plan view showing the configuration of the thin film transistor, and FIG. 3C is a schematic plan view showing the configuration of the storage capacitor. It is. 4 is a schematic plan view showing the arrangement of the pixels of Example 1, FIG. 5 is a schematic cross-sectional view showing the structure of the pixels cut along the line BB ′ in FIG. 3A, and FIG. 6 is FIG. It is a schematic sectional drawing which shows the structure of the pixel cut | disconnected by CC 'line.

  As shown in FIG. 3A, the pixel P of the first embodiment includes pixel electrodes 15 arranged in a matrix corresponding to the intersection of the scanning line 3a and the data line 6a, and the scanning line 3a and the data line 6a. And a TFT 30 having a semiconductor layer 30a bent in an L shape at the intersection.

  As shown in FIGS. 3A and 3B, the semiconductor layer 30a overlaps the scanning line 3a and overlaps the drain region 30a5 as the first source / drain region extending in the X direction and the data line 6a. A source region 30a1 as a second source / drain region extending in the Y direction, and a channel region 30a3 bent at the intersection and extending in the Y direction and the X direction are included. Further, an LDD (Lightly Doped Drain) region 30a2 is provided between the source region 30a1 and the channel region 30a3, and an LDD region 30a4 is provided between the drain region 30a5 and the channel region 30a3. The channel region 30a3 includes a first extension portion extending in the X direction and a second extension portion extending in the Y direction, and the length L1 of the first extension portion in the first direction extends in the Y direction. It is shorter than the length L2 of the existing second extending portion. Note that the first extension portion and the second extension portion have portions that overlap each other in a plane at the intersection of the scanning line 3a and the data line 6a.

The semiconductor layer 30a of the first embodiment is made of a polycrystalline silicon film having a width of about 0.3 μm, and the length of the channel region 30a3 in the Y direction, that is, the length L2 of the second extending portion is about 1. .05 μm, the length of the channel region 30a3 in the X direction, that is, the length L1 of the first extending portion is approximately 0.75 μm.
The lengths of the LDD regions 30a2 and 30a4 are approximately 0.5 μm to 1.0 μm, respectively.
When the semiconductor layer 30a is arranged linearly (when it is not bent), the length of the channel region 30a3 for securing predetermined electrical characteristics is about 1.5 μm by design, but the channel region 30a3 is bent. Thus, the length L2 of the channel region 30a3 in the Y direction can be shortened by 0.45 μm. In other words, the length of the center line of the bent channel region 30a3 is 1.5 μm in design.
The lengths of the source region 30a1 and the drain region 30a5 can be set as appropriate, and the length of the source region 30a1 is a relative positional relationship with the contact hole CNT1 for electrical connection with the data line 6a. It is decided by. Similarly, the length of the drain region 30a5 is determined by the relative positional relationship with the contact hole CNT2 for electrical connection with the pixel electrode 15 and a storage capacitor 16 described later.

The gate electrode portion 30g of the TFT 30 is provided so as to overlap the bent channel region 30a3, and has two extended portions extending in the X direction on both sides of the drain region 30a5 of the semiconductor layer 30a.
The scanning line 3a also has an extension portion so as to overlap the gate electrode portion 30g in the vicinity of the intersection with the data line 6a, and the electrical connection between the scanning line 3a and the gate electrode portion 30g in the mutual extension portion. Contact holes 33 and 34 are provided for easy connection. In the contact holes 33 and 34, a side wall portion having a light-shielding conductive film provided extending from the gate electrode portion 30g is provided. The configuration of the side wall will be described later.
As shown in FIG. 3C, the storage capacitor 16 of the pixel P is arranged to extend in the X direction from the main line portion extending in the Y direction and to overlap the extended portion of the scanning line 3a. One capacitive electrode 16a including the protruding portion, and the other capacitive electrode 16b provided in an island shape while overlapping the main line portion and the protruding portion of the one capacitive electrode 16a in a plan view.
The main line portion of one capacitor electrode 16a is arranged so as to straddle a plurality of pixels P in the Y direction, and functions as the capacitor line 3b.
The protruding portion of the other capacitor electrode 16b extends in the X direction so as to planarly include a contact hole CNT4 for electrical connection with the pixel electrode 15.

  As shown in FIG. 4, the plurality of pixels P arranged in a matrix form includes an opening area in which the pixels P are optically opened and a non-opening area (in a substantially lattice shape so as to surround the plurality of opening areas). Light shielding region).

  The non-opening region extending in the X direction includes at least the scanning line 3a. The scanning line 3a has conductivity and light shielding properties. For example, a single refractory metal such as Ti, Cr, W, Ta, Mo, Pd, an alloy selected from these refractory metals, metal silicide, Polysilicide or a laminate of these can be used.

  The non-opening region extending in the Y direction includes at least the data line 6a. The data line 6a is made of a material having conductivity and light-shielding property, for example, a low melting point metal such as Al, Ag, Au, or Cu, or a single high melting point metal such as Ti similar to the scanning line 3a. An alloy selected from the group consisting of metal silicide, polysilicide, and a laminate of these can be employed.

As described above, the scanning line 3a has the extended portion extended in the Y direction in the vicinity of the intersection with the data line 6a, and the opening area of the pixel P adjacent in the Y direction is in relation to the scanning line 3a. It is line symmetric. On the other hand, it is axisymmetric with respect to the data line 6a.
In the first embodiment, the non-opening region is expanded toward the opening region near the intersection, but the planar shape of the opening region is substantially square. That is, the width of the opening region in the X direction and the Y direction is substantially equal.

  With reference to FIG. 5 and FIG. 6, the structure of the pixel P of Example 1 will be described in detail. As shown in FIG. 5, the scanning line 3 a is first formed on the element substrate 10. Next, a first insulating film 11a made of, for example, silicon oxide is formed so as to cover the scanning line 3a, and a semiconductor layer 30a is formed in an island shape on the first insulating film 11a. As described above, the semiconductor layer 30a is made of a polycrystalline silicon film, and impurity ions are selectively implanted to have the LDD structure having the source region 30a1, the LDD region 30a2, the channel region 30a3, the LDD region 30a4, and the drain region 30a5. Is formed. Impurity ions are not implanted into the channel region 30a3.

  A second insulating film (gate insulating film) 11b is formed so as to cover the semiconductor layer 30a. Further, a gate electrode portion 30g is formed at a position corresponding to the channel region 30a3 with the second insulating film 11b interposed therebetween. As the material for forming the gate electrode portion 30g, the same material as that for the data line 6a described above can be used.

  A third insulating film 11c is formed so as to cover the gate electrode portion 30g and the second insulating film 11b, and the second insulating film 11b and the third insulating film 11c are disposed at positions overlapping with respective end portions of the semiconductor layer 30a. Two through holes are formed. Then, a conductive film (conductive film made of the material constituting the data line 6a described above) is formed so as to fill the two holes and cover the third insulating film 11c, and is patterned to connect to the source region 30a1. Contact hole CNT1, data line 6a, and source electrode 31 are formed. At the same time, the contact hole CNT2 and the drain electrode 32 are formed by patterning the relay electrode 6b in an island shape.

  The first interlayer insulating film 12 is formed so as to cover the data line 6a (source electrode 31), the drain electrode 32, and the third insulating film 11c. The first interlayer insulating film 12 is made of, for example, silicon oxide or nitride, and is subjected to a flattening process for flattening surface irregularities caused by covering the region where the TFT 30 is provided. Examples of the planarization method include surface polishing (CMP) and spin coating.

  On the first interlayer insulating film 12, a shield layer 35 patterned so as to overlap the scanning line 3a and the data line 6a in a plane is formed. The shield layer 35 is made of a low-resistance wiring material such as Al, for example, and has a light shielding property and shields the invading electromagnetic wave to protect the TFT 30. In the plan view of FIG. 3A, the shield layer 35 is not shown, but is formed in the non-opening region shown in FIG. 4 in plan view.

  A second interlayer insulating film 13 is formed so as to cover shield layer 35 and first interlayer insulating film 12. The second interlayer insulating film 13 is also made of, for example, silicon oxide or nitride, and may be subjected to a planarization process in the same manner as the first interlayer insulating film 12.

A hole penetrating the first interlayer insulating film 12 and the second interlayer insulating film 13 is formed at a position overlapping the drain electrode 32, and a light-shielding conductive film is formed so as to fill the hole. The conductive electrode is patterned to form the capacitor electrode 16b.
As the light-shielding conductive film, for example, a single layer film made of Al (aluminum), TiN (titanium nitride), or a multilayer film in which these layers are stacked can be used.

  Next, a protective film made of, for example, silicon oxide is formed so as to cover the capacitor electrode 16 b and the second interlayer insulating film 13. The protective film is patterned so as to exclude the region where the dielectric layer 16c is formed in the protective film. As a method for partially removing the protective film and patterning, for example, a method in which the formed protective film is partially dry-etched, or the surface of the capacitor electrode 16b to be removed in advance is masked with a resist or the like. There is a lift-off method in which the resist is removed after the film is formed. As a result, the protective layer 37 that covers the outer edge portion of the capacitor electrode 16b and covers the surface of the second interlayer insulating film 13 is formed.

Next, a translucent dielectric film is formed so as to cover the capacitor electrode 16b and the second interlayer insulating film 13, and patterning is performed so as to exclude a portion of the dielectric film that overlaps the contact hole CNT4 of the capacitor electrode 16b. Thus, the dielectric layer 16c is formed. As the light-transmitting dielectric film, a silicon nitride film, a single-layer film such as haunium oxide (HfO ₂ ), alumina (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), or a single-layer film thereof Of these, a multilayer film in which at least two kinds of single-layer films are stacked may be used. A dielectric layer 16c is formed by patterning so as to cover the capacitor electrode 16b and the protective layer 37.
Then, a conductive film is formed so as to cover the dielectric layer 16c, and is patterned so as to overlap the capacitor electrode 16b and to have the main line portion and the protruding portion described above, thereby forming the capacitor electrode 16a.
Even when the capacitive electrode 16a and the capacitive electrode 16b are both made of the same material, when the capacitive electrode 16a is patterned, the capacitive electrode 16b is completely covered by the protective layer 37 and the dielectric layer 16c. Therefore, problems such as etching of the capacitor electrode 16b are prevented.

  The storage capacitor 16 in the pixel P of Example 1 is configured by the capacitor electrode 16b, the dielectric layer 16c, and the capacitor electrode 16a formed as described above.

  Then, a third interlayer insulating film 14 made of, for example, silicon oxide or nitride is formed so as to cover the storage capacitor 16 and the protective layer 37. Of course, the third interlayer insulating film 14 may be planarized. A hole penetrating the third interlayer insulating film 14 and the protective layer 37 is provided at a position overlapping the capacitor electrode 16b, and a transparent conductive film is formed and patterned so as to fill the hole, thereby forming the pixel electrode 15 and the contact hole CNT4. And are formed.

  In the storage capacitor 16, the capacitor electrode 16b is electrically connected to the drain electrode 32 of the TFT 30 through the contact hole CNT3 and is electrically connected to the pixel electrode 15 through the contact hole CNT4. As described above, the main line portion of the capacitor electrode 16a is formed so as to extend over the plurality of pixels P in the extending direction (Y direction) of the data line 6a, and functions as the capacitor line 3b in the equivalent circuit (see FIG. 2). . A fixed potential is applied to the capacitor line 3b. The fixed potential is, for example, GND or a common potential (LCCOM) applied to the common electrode 23 of the counter substrate 20. Thereby, the potential applied to the pixel electrode 15 via the drain electrode 32 of the TFT 30 can be held between the capacitor electrode 16a and the capacitor electrode 16b.

  As shown in FIG. 6, contact holes 33 and 34 for providing electrical connection between the scanning line 3a and the gate electrode portion 30g are provided on both sides of the semiconductor layer 30a (LDD region 30a4) in the extended portion of the scanning line 3a. It has been. The contact holes 33 and 34 are simultaneously formed in the step of forming the gate electrode portion 30g, and side wall portions 33a and 34a formed by patterning a light-shielding conductive film are provided in the contact holes 33 and 34. .

A third insulating film 11c is formed so as to cover contact holes 33 and 34 and second insulating film 11b. Next, the data line 6a, the first interlayer insulating film 12, the shield layer 35, the second interlayer insulating film 13, the storage capacitor 16, and the third interlayer insulating film 14 are sequentially stacked on the third insulating film 11c.
A transparent conductive film is formed on the third interlayer insulating film 14, and the pixel electrode 15 is formed by patterning the transparent conductive film. Adjacent pixel electrodes 15 are patterned so that their outer edge portions overlap non-opening regions including the light-shielding scanning lines 3 a, the data lines 6 a, the shield layer 35, and the storage capacitor 16.

According to the configuration of the pixel P of the first embodiment, the following operations and effects are achieved.
(1) The channel region 30a3, which requires a predetermined length in terms of electrical characteristics, is bent at the intersection between the scanning line 3a and the data line 6a. Therefore, the substantial length in the Y direction in the arrangement of the semiconductor layer 30a can be shortened as compared with the case where the source / drain regions other than the channel region 30a3 are bent. In other words, even if the pixel P is arranged in a high-definition state, the TFT 30 having desired electrical characteristics can be provided for each pixel P.

  (2) Contact holes 33 and 34 having light-shielding side wall portions 33 a and 34 a are provided on both sides along the drain region 30 a 5 on the side connected to the pixel electrode 15. Therefore, light incident from the side surface of the drain region 30a5 can be blocked. That is, generation of light leakage current of the TFT 30 due to stray light strayed into the non-opening region can be effectively reduced.

  (3) The channel region 30a3 is bent so that the length L1 on the drain region 30a5 side is shorter than the length L2 on the source region 30a1 side. Therefore, compared with the case where the length L2 of the channel region 30a3 on the source region 30a1 side is shortened, the planar range in which the light-shielding contact holes 33 and 34 in consideration of the light leakage current due to stray light of the TFT 30 is reduced. Can do. In other words, the non-opening region can be reduced to secure a wider opening region.

(Example 2)
FIG. 7 is a schematic plan view illustrating the configuration of the pixel according to the second embodiment. FIG. 8 is a schematic plan view illustrating the arrangement of the pixel according to the second embodiment. The second embodiment is different from the first embodiment in the shape of the scanning line and the arrangement of contact holes for electrical connection between the scanning line and the gate electrode portion. In addition, the same code | symbol is attached | subjected to the same structure as Example 1, and detailed description is abbreviate | omitted.

  As shown in FIG. 7, the pixel PB of Example 2 includes a TFT 30B having a semiconductor layer 30a in which the channel region 30a3 is bent in an L shape at the intersection of the scanning line 3a and the data line 6a, as in Example 1. I have.

  The scanning line 3a has an extended portion extended so as to protrude from adjacent pixels PB in the X direction and the Y direction. The gate electrode portion 30gb is arranged so as to overlap the channel region 30a3 in plan view and the extension portion. Contact holes 33 and 34B for electrically connecting the scanning line 3a and the gate electrode portion 30gb are provided on both sides along the semiconductor layer 30a. In other words, one contact hole 34B extends along the channel region 30a3 bent from the LDD region 30a2 on the source region 30a1 side in the semiconductor layer 30a, and also on the side connected to the pixel electrode 15, the LDD region 30a4 and the drain region 30a5. Are arranged along.

  As shown in FIG. 8, the pixel PB of Example 2 has a configuration in which the opening regions of the pixels PB adjacent in the X direction and the Y direction are line symmetric with respect to the scanning line 3a and the data line 6a. In other words, the shape of the scanning line 3a and the gate electrode portion 30gb and the shape of the contact holes 33 and 34B are set so that the opening region of the adjacent pixel PB is line-symmetric with respect to the scanning line 3a and the data line 6a. Has been.

According to the configuration of the pixel PB of the second embodiment, in addition to the operations and effects (1) to (3) of the first embodiment, the following operations and effects are achieved.
(4) The contact hole 34B of the second embodiment shields the side surface of the semiconductor layer 30a over a wider range than the contact hole 34 of the first embodiment. Therefore, it has a higher light shielding property against stray light than that of the first embodiment, and the generation of light leakage current of the TFT 30B against stray light can be further reduced.

  (5) Since the opening area of the pixel PB in Example 2 is line symmetric in the X direction and the Y direction, it is assumed that the arrangement of the liquid crystal device 100 is changed when the viewing angle characteristics are biased in the liquid crystal device 100 However, the bias in the viewing angle characteristic is less likely to be emphasized than before the arrangement is changed. In particular, the projection display device described later is effective when a plurality of liquid crystal devices 100 are arranged for each color light as liquid crystal light valves.

(Example 3)
FIG. 9A is a schematic plan view showing the configuration of the pixel of Example 3, FIG. 9B is a schematic plan view showing the configuration of the semiconductor layer of Example 3, and FIG. 9C is the capacitance line and the relay electrode. It is a schematic plan view which shows arrangement | positioning of a capacitive electrode. FIG. 10 is a schematic cross-sectional view showing the structure of the pixel cut along the line DD ′ in FIG. In the third embodiment, a part of the semiconductor layer is made to function as a capacitor electrode of a storage capacitor, as compared with the first and second embodiments. That is, an example in which the pixel configuration is not limited to the first and second embodiments is shown. In addition, the same code | symbol is attached | subjected to the same structure as Example 1, and detailed description is abbreviate | omitted.

As shown in FIGS. 9A and 9B, in the pixel PC of the third embodiment, the channel region 30a3 is opposite to the first and second embodiments at the intersection of the scanning line 3a and the data line 6a. The TFT 30 </ b> C having the semiconductor layer 30 a that is bent is provided.
The scanning line 3a and the data line 6a are each provided with a constant width.
The TFT 30C has an L-shaped gate electrode portion 30gc that is bent at the intersection so as to overlap the bent channel region 30a3 and to overlap the scanning line 3a and the data line 6a in a plane. The gate electrode portion 30gc is electrically connected to the scanning line 3a through a contact hole CNT13 provided in a portion along the scanning line 3a.

  As shown in FIG. 9B, the semiconductor layer 30a includes a source region 30a1 and an LDD region 30a2 arranged along the data line 6a, a channel region 30a3 bent so that the source region 30a1 side becomes long, and scanning. It has an LDD region 30a4 and a drain region 30a5 arranged along the line 3a. Further, it has an extended portion 30a6 that is connected to the drain region 30a5 and is part of the source / drain region disposed along the data line 6a. The drain region 30a5 and its extension 30a6 function as one capacitor electrode 16d of the storage capacitor 16.

  A source electrode 31 (contact hole CNT11) is provided at the end of the source region 30a1. A drain electrode 32 (contact hole CNT12) is provided at the end of the drain region 30a5.

  As shown in FIG. 9C, the capacitor line 3b overlaps the data line 6a in plan and extends across a plurality of pixels PC in the Y direction. The capacitor line 3b has a protruding portion 3c protruding toward the scanning line 3a at the intersection of the scanning line 3a and the data line 6a. An island-shaped relay electrode 3d is provided at a position separated from the protrusion 3c in the X direction.

  The other capacitor electrode 16e of the storage capacitor 16 is provided across the protruding portion 3c of the capacitor line 3b and the relay electrode 3d, and is provided so as to overlap the one capacitor electrode 16d.

The protrusion 3c is provided with a contact hole CNT15 electrically connected to the capacitor line 3b.
The relay electrode 3d is provided with a contact hole CNT14 that is electrically connected to the capacitor electrode 16e. A contact hole CNT16 electrically connected to the drain region 30a5 and a contact hole CNT17 electrically connected to the pixel electrode 15 are provided.

  As shown in FIG. 9A, the island-shaped relay electrode 6b that overlaps the scanning line 3a, straddles the contact hole CNT14 and the contact hole CNT15, and the island-like straddle straddles the contact hole CNT12 and the contact hole CNT16. A relay electrode 6c is provided.

  The end portion of the other capacitor electrode 16e along the scanning line 3a is located between the contact hole CNT12 and the contact hole CNT16.

  Next, the structure of the pixel PC of Example 3 will be described with reference to FIG. As shown in FIG. 10, the scanning line 3a is first patterned on the element substrate 10, and the first insulating film 11a is formed so as to cover the scanning line 3a. Next, a semiconductor layer 30a made of a polycrystalline silicon film is patterned on the first insulating film 11a. Impurity ions are selectively implanted to form the source electrode 31, the source region 30a1, the LDD region 30a2, the channel region 30a3, the LDD region 30a4, and the drain region 30a5. At the same time, although not shown in FIG. 10, an extension 30a6 (see FIG. 9B) of the drain region 30a5 is formed. Then, a second insulating film (gate insulating film) 11b is formed so as to cover the semiconductor layer 30a.

  Next, the gate electrode portion 30gc and the other capacitor electrode 16e of the storage capacitor 16 are formed by patterning on the second insulating film 11b. Further, in the step of patterning and forming the gate electrode portion 30gc, a through-hole that penetrates through the first insulating film 11a and the second insulating film 11b that overlaps the gate electrode portion 30gc and reaches the scanning line 3a is provided, and the gate is filled so as to fill it. The contact hole CNT13 is formed by forming and patterning a material for forming the electrode portion 30gc.

  Next, the first interlayer insulating film 12 is formed so as to cover the gate electrode portion 30gc and the capacitor electrode 16e. The first interlayer insulating film 12 is formed with through holes that open to the source electrode 31, a part of the capacitor electrode 16e, and a part of the drain region 30a5. A material for forming the data line 6a is formed so as to fill these through holes and cover the surface of the first interlayer insulating film 12, and by patterning this, the data line 6a, the relay electrode 6b, the relay electrode 6c (drain) Electrode 32), contact hole CNT11, contact hole CNT12, and contact hole CNT14 are formed.

  Next, a second interlayer insulating film 13 is formed so as to cover the data line 6 a, the relay electrode 6 b, the relay electrode 6 c and the first interlayer insulating film 12. The second interlayer insulating film 13 is formed with through holes that open to the relay electrodes 6b and 6c. A material for forming the capacitor line 3b is formed so as to fill these through holes and cover the surface of the second interlayer insulating film 13, and by patterning this, the capacitor line 3b including the protruding portion 3c, the relay electrode 3d, Contact holes CNT15 and CNT16 are formed.

Next, a third interlayer insulating film 14 is formed so as to cover the capacitor line 3b, the relay electrode 3d, and the second interlayer insulating film 13. A through hole that opens to the relay electrode 6 c is formed in the third interlayer insulating film 14. A transparent conductive film such as ITO is formed so as to fill the through hole and cover the surface of the third interlayer insulating film 14, and the pixel electrode 15 and the contact hole CNT 17 are formed by patterning the transparent conductive film.
Note that the first interlayer insulating film 12, the second interlayer insulating film 13, and the third interlayer insulating film 14 are preferably subjected to a planarization process such as a CMP process so that the surfaces thereof are planarized.

  According to the configuration of the pixel PC of the third embodiment, in addition to the operation / effect (1) of the first embodiment, the following operations / effects are provided.

  (6) Since the drain region 30a5 and its extension 30a6 in the semiconductor layer 30a function as one capacitor electrode 16d of the storage capacitor 16, the layer structure is simplified compared to the first and second embodiments. A pixel PC can be realized.

  (7) What protrudes to the opening region side in the vicinity of the intersection of the scanning line 3a and the data line 6a is a portion where the portions extending in the X and Y directions of the capacitive electrodes 16d and 16e constituting the storage capacitor 16 are connected. Therefore, it is easy to enlarge the opening area as compared with the first and second embodiments. In other words, it is easy to achieve a high aperture ratio.

(Second Embodiment)
<Electronic equipment>
FIG. 11 is a schematic diagram illustrating a configuration of a projection display device as an electronic apparatus. As shown in FIG. 11, a projection display apparatus 1000 as an electronic apparatus according to the present embodiment includes a polarized illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. Three reflection mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a light combining element As a cross dichroic prism 1206 and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and the emission side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection type display device 1000, the liquid crystal device 100 that can obtain stable operation quality even if the pixels are high definition is provided, and high display quality is realized.

  Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) The method of bending the semiconductor layer 30a in Examples 1 to 3 of the first embodiment is not limited to this. For example, when the shape of the pixel P (or the pixel electrode 15) is not a substantially square with an aspect ratio of approximately 1: 1 but a rectangle, the channel region is bent at the intersection of the scanning line 3a and the data line 6a. 30a3 may be bent so that the side along the longitudinal direction of the pixel P becomes longer. According to this, even if the pixel P becomes high definition, the semiconductor layer 30a can be arranged efficiently.

  (Modification 2) The electronic apparatus to which the liquid crystal device 100 is applied is not limited to the projection display device 1000. For example, projection-type HUD (head-up display), direct-view type HMD (head-mounted display), electronic book, personal computer, digital still camera, LCD TV, viewfinder type or monitor direct-view type video recorder, car navigation system It can be suitably used as a display unit of an information terminal device such as an electronic notebook or POS.

  3a ... Scanning line, 6a ... Data line, 15 ... Pixel electrode, 30 ... Thin film transistor (TFT), 30a ... Semiconductor layer, 30a1 ... Source region as second source / drain region, 30a5 ... As first source / drain region Drain region, 30a3 ... channel region, 30a2, 30a4 ... LDD region, 30g ... gate electrode portion, 33, 34 ... contact hole between scanning line and gate electrode portion, 33a, 34a ... side wall portion, 100 ... electro-optical device Liquid crystal device, 1000... Projection type display device as an electronic device.

Claims (5)

A scan line extending in a first direction;
A data line extending in a second direction intersecting the scan line;
A transistor provided corresponding to the intersection of the scan line and the data line, and electrically connected to the scan line and the data line;
The transistor includes a first source / drain region extending in the first direction, a second source / drain region extending in the second direction, and the first and second source / drain regions. A first extension portion extending in the first direction and a second extension extending in the second direction, provided to overlap the intersection of the scanning line and the data line. A semiconductor region having a channel region including a portion;
A gate electrode portion facing the channel region;
An electro-optical device comprising: A pixel electrode provided corresponding to the transistor;
One of the first and second source / drain regions is electrically connected to the pixel electrode, and the other is electrically connected to the data line,
Planarly provided on both sides of the semiconductor layer along the one source / drain region, and extends from the gate electrode portion into a contact hole that electrically connects the scanning line and the gate electrode portion. A side wall portion having a light-shielding conductive film provided;
The channel region has a length on the one source / drain region side among the length of the first extension portion in the first direction and the length of the second extension portion in the second direction. The electro-optical device according to claim 1, wherein the electro-optical device is shorter than a length on the source / drain region side. LDD regions are respectively provided between the channel region and the first and second source / drain regions,
3. The electro-optical device according to claim 2, wherein at least one of the side wall portions provided on both sides of the semiconductor layer is provided along the channel region and the LDD region.   The electro-optical device according to claim 3, wherein the light shielding region including the gate electrode portion is arranged symmetrically with respect to the scanning line and the data line.   An electronic apparatus comprising the electro-optical device according to claim 1.

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