JP6079077B2 - Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus equipped with the electro-optical device.

  2. Description of the Related Art Conventionally, an active drive type liquid crystal display device which is an example of an electro-optical device has been widely used as a light modulation means (light valve) of a projection display device such as a projector. In the liquid crystal display device for use in the light valve, the pixel pitch is becoming finer as the aperture ratio of the pixel is increased. For example, in addition to the liquid crystal display device (1920 × 1080 pixels) compatible with full high-definition, more than four times that of full high-definition. High-definition liquid crystal display devices (4096 × 2160 pixels) having the number of pixels have been developed.

  The pixel size of the high-definition liquid crystal display device is very small, approximately 8 μm to 9 μm square. Each pixel has a pixel electrode, a thin film transistor (hereinafter abbreviated as TFT) that controls switching of the pixel electrode, and writing to the pixel electrode. A storage capacitor (capacitance element) for holding the image signal is arranged. In order to obtain a clearer display, it is necessary to increase the capacity of the capacitive element and suppress deterioration of the image signal written to the pixel electrode. Furthermore, since the capacitive element is a component that decreases the aperture ratio, it is desirable to increase the capacity of the capacitive element while suppressing an increase in the area occupied by the capacitive element in the pixel. For example, a plurality of capacitive elements are stacked. Therefore, it is necessary to increase the capacity of the capacitor element by connecting them in parallel without causing an increase in the area occupied by the capacitor element.

  On the other hand, a TFT, a capacitor element, or the like arranged in a pixel has a configuration in which electrodes arranged opposite to each other with an insulating layer interposed therebetween are electrically connected through a contact hole formed in the insulating layer. Since the contact hole is also a component that lowers the aperture ratio, it is desirable to reduce the area occupied by the contact hole in the pixel. For example, a method described in Patent Document 1 has been proposed as a method of connecting a plurality of electrodes with a contact hole having a smaller area.

JP 2009-37115 A

However, the method described in Patent Document 1 is a method in which conductive films sequentially stacked in three or more layers with an insulating layer interposed therebetween are connected to each other, and is used for connecting electrodes constituting a plurality of stacked capacitor elements. There was a problem that it was not applicable. Specifically, the capacitor element is composed of a pair of electrodes arranged to face each other with an insulating layer interposed therebetween. In the method described in Patent Document 1, the pair of electrodes arranged to face each other is electrically connected. There has been a problem that it cannot be applied to connection of electrodes constituting a plurality of capacitive elements.
A first capacitive element having a first electrode and a second electrode disposed opposite to each other with an insulating layer interposed therebetween, and a second capacitive element having a third electrode and a fourth electrode disposed opposite to each other with an insulating layer interposed therebetween In order to connect both the capacitive elements in parallel, for example, it is necessary to electrically connect the first electrode and the third electrode. In that case, a contact hole is formed in the insulating film stacked on the first electrode, another contact hole is formed in the insulating film stacked on the third electrode, and the first electrode and the other contact in the contact hole are formed. It was necessary to wire the third electrode in the hole with a conductive film. That is, at least two contact holes are required to electrically connect two kinds of electrodes arranged in different layers. In a high-definition liquid crystal display device with a small pixel size, there is a problem that when a new contact hole is formed in a pixel in order to connect stacked capacitive elements in parallel, the aperture ratio is greatly reduced.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 In the electro-optical device according to this application example, the first electrode, the first capacitor insulating layer, and the second electrode are stacked in the first direction, and the second electrode, the second capacitor insulating layer, and the third electrode are stacked. An electrode is laminated in the first direction, and includes an insulating layer that covers the third electrode, a contact hole that penetrates the insulating layer, and a conductive film that is disposed inside the contact hole, and intersects the first direction. The outer edge of the first electrode protrudes from the outer edge of the second electrode in the second direction, and the outer edge of the third electrode is disposed between the outer edge of the first electrode and the outer edge of the second electrode, and viewed from the first direction. In addition, at least a part of the outer edge of the third electrode is included in the region of the contact hole, and the first electrode and the third electrode are connected through a conductive film.

The outer edge of the second electrode, the outer edge of the third electrode, and the outer edge of the first electrode are arranged along the second direction, and the contact hole is the third electrode as viewed from the first direction intersecting the second direction. The outer edge is included. Further, in the contact hole, the third electrode is exposed in a region between the outer edge of the second electrode and the outer edge of the third electrode, and the first electrode is exposed in a region between the outer edge of the third electrode and the outer edge of the first electrode. The electrode is exposed. In other words, the contact hole has a region where the third electrode is exposed and a region where the first electrode is exposed, with the outer edge of the third electrode interposed therebetween. Further, by burying a conductive film in the contact hole, the first electrode and the third electrode can be electrically connected by the conductive film. That is, two electrodes (first electrode and third electrode) arranged in different layers can be electrically connected through a contact hole having a smaller area called one contact hole.
Furthermore, in the electro-optical device according to this application example, the first electrode, the first capacitor insulating layer, and the second electrode form a first capacitor element, and the second electrode, the second capacitor insulating layer, and the third electrode are formed. The second capacitor element is formed, and the first capacitor element and the second capacitor element are stacked. In the first capacitor element and the second capacitor element, the second electrode is one electrode, and the first electrode and the third electrode are the other electrode facing the one electrode. The first electrode and the third electrode, which are the other electrodes, are also electrically connected through the contact hole having a smaller area as described above. Therefore, the stacked first capacitor element and second capacitor element Are connected in parallel. That is, by forming a storage capacitor with two capacitor elements that are stacked and connected in parallel, the capacitance per unit area is increased, and the display performance of the electro-optical device can be improved.

  Application Example 2 In the electro-optical device according to the application example, the first interlayer insulating layer covering the outer edge of the first electrode between the first electrode and the first capacitor insulating layer, the second electrode, and the second capacitor. It is preferable that a second interlayer insulating layer covering the outer edge of the second electrode is provided between the insulating layer and the insulating layer.

  In the first capacitive element composed of the first electrode, the first capacitive insulating layer, and the second electrode, the outer edge (stepped portion) of the first electrode is covered with the first interlayer insulating layer, thereby making the step of the first electrode A short circuit between the first electrode and the second electrode in the portion can be suppressed. Similarly, in the second capacitor element constituted by the second electrode, the second capacitor insulating layer, and the third electrode, the outer edge (stepped portion) of the second electrode is covered with the second interlayer insulating layer, whereby the second capacitor element is formed. A short circuit between the second electrode and the third electrode in the step portion of the electrode can be suppressed.

  Application Example 3 In the electro-optical device according to the application example described above, the area of the first electrode exposed in the contact hole and the area of the third electrode exposed in the contact hole are substantially equal. Is preferred.

  The contact area between the first electrode and the conductive film in the contact hole (the exposed area of the first electrode), and the contact area between the third electrode and the conductive film in the contact hole (of the exposed third electrode) Since the contact area with the conductive film is small in either the first electrode or the third electrode, the problem that the contact resistance increases can be suppressed. Therefore, the first electrode and the third electrode can be stably electrically connected by the conductive film.

  Application Example 4 In the electro-optical device according to the application example described above, it is preferable that the insulating layer includes either silicon oxide, nitride, or oxynitride, and the third electrode is tungsten silicide.

  In this application example, it is necessary to form a contact hole that exposes the first electrode and the third electrode through the insulating layer containing either silicon oxide, nitride, or oxynitride (etching). . The third electrode is made of tungsten silicide and has excellent etching resistance when etching an insulating layer containing either silicon oxide, nitride, or oxynitride. The contact hole can be formed while suppressing etching damage.

  Application Example 5 The electro-optical device according to the application example includes a transistor and a second insulating layer sandwiched between the semiconductor layer of the transistor and the first electrode, and the second electrode has the second insulation. Preferably, the transistor is connected to the semiconductor layer of the transistor through a second contact hole that penetrates the layer and the first capacitor insulating layer.

  In the electro-optical device according to this application example, the first capacitor, the first capacitor insulating layer, and the second electrode form the first capacitor element, and the second electrode, the second capacitor insulating layer, and the third electrode form the first electrode. 2 capacitive elements are formed, and the first capacitive element and the second capacitive element are stacked and connected in parallel. The second electrode serves as one electrode constituting the first capacitor element and the second capacitor element. By connecting the second electrode to the semiconductor layer of the transistor, a predetermined signal is supplied to one electrode (second electrode) constituting the first capacitor element and the second capacitor element through the transistor. Can do.

  Application Example 6 An electronic apparatus according to this application example includes the electro-optical device described in the application example.

  Since the electronic device of this application example includes the electro-optical device whose display performance is improved by increasing the capacity of the capacitive element, for example, by using the electro-optical device as a light valve, the display device has excellent display performance. Projectors and projection televisions can be provided. Furthermore, it is possible to provide a small and lightweight electronic device such as an HMD (Head Mounted Display) or a digital camera using the electro-optical device as a monitor. Furthermore, the electro-optical device of the present invention can also be applied to display units of various electronic devices such as mobile computers, in-vehicle devices, audio devices, and information terminal devices.

  Application Example 7 In the electro-optical device manufacturing method according to this application example, the first electrode, the first capacitor insulating layer, the second electrode, the second capacitor insulating layer, the third electrode, and the insulating layer are the first. A method of manufacturing an electro-optical device in which a first electrode and a third electrode are electrically connected by a contact hole stacked in a direction and passing through an insulating layer and a conductive film disposed inside the contact hole. Forming a second electrode such that an outer edge of the first electrode protrudes from an outer edge of the second electrode in a second direction intersecting the first direction; and an outer edge of the first electrode and an outer edge of the second electrode; Forming the third electrode so that the outer edge of the third electrode is disposed between the first electrode and the third electrode, including at least part of the outer edge of the third electrode when viewed from the first direction. A step of forming a contact hole to be exposed; a first electrode exposed in the contact hole; Characterized in that it comprises a step of forming a conductive film covering the electrode, the.

In a configuration in which the first electrode, the first capacitor insulating layer, the second electrode, the second capacitor insulating layer, the third electrode, and the insulating layer are stacked in the first direction, the second direction intersecting the first direction In addition, each electrode is formed so that the outer edge of the second electrode, the outer edge of the third electrode, and the outer edge of the first electrode protrude in order. Using a resist for forming a contact hole including the outer edge of the third electrode as a mask, an insulating layer stacked on the third electrode, and a first capacitor insulating layer and a second capacitor stacked on the first electrode The insulating layer and the insulating layer are etched to form a contact hole that exposes the third electrode and the first electrode. By covering the first electrode and the third electrode exposed in the contact hole with a conductive film, the first electrode and the third electrode can be electrically connected. In other words, through this process, the first electrode and the third electrode can be electrically connected with a smaller area of one contact hole.
Further, the insulating layer stacked on the third electrode, and the first capacitor insulating layer, the second capacitor insulating layer, and the insulating layer stacked on the first electrode are continuously etched using, for example, the same resist as a mask. By doing so, a contact hole can be formed with a minimum number of photolithographic processes.

  Application Example 8 In the method of manufacturing the electro-optical device according to the application example, it is preferable that the insulating layer includes any one of silicon oxide, nitride, or oxynitride, and the third electrode is tungsten silicide. .

Since the third electrode is made of tungsten silicide and has excellent etching resistance when etching an insulating layer containing either silicon oxide, nitride, or oxynitride, etching to the third electrode is possible. The contact hole can be formed while suppressing damage.
For example, an insulating layer stacked on the third electrode, and a first capacitor insulating layer, a second capacitor insulating layer, and an insulating layer stacked on the first electrode may be formed of a film having the same etching performance (silicon oxide layer). An insulating layer including any one of an oxide, a nitride, and an oxynitride), an insulating layer stacked on the third electrode, a first capacitor insulating layer stacked on the first electrode, and a second Even if the capacitor insulating layer and the insulating layer are continuously etched to form a contact hole, etching damage to the third electrode can be suppressed.

1 is a schematic plan view illustrating a configuration of a liquid crystal display device according to an embodiment. FIG. 2 is a schematic cross-sectional view taken along line H-H ′ of the liquid crystal display device shown in FIG. 1. FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal display device according to the embodiment. FIG. 2 is a schematic plan view illustrating a configuration of a pixel in the liquid crystal display device according to the embodiment. FIG. 2 is a schematic plan view illustrating a configuration of a pixel in the liquid crystal display device according to the embodiment. FIG. 2 is a schematic plan view illustrating a configuration of a pixel in the liquid crystal display device according to the embodiment. FIG. 2 is a schematic plan view illustrating a configuration of a pixel in the liquid crystal display device according to the embodiment. FIG. 8 is a schematic cross-sectional view of a pixel along the line A-A ′ illustrated in FIGS. 4 to 7. A process flow for forming a contact region for connecting stacked capacitor elements in parallel. The schematic cross section of the contact area | region in the main processes. FIG. 2 is a plan view showing a configuration of a projector equipped with the liquid crystal display device according to the embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. Such embodiment shows one mode of the present invention, does not limit the present invention, and can be arbitrarily changed within the scope of the technical idea of the present invention. In each of the following drawings, the scale of each layer or each part is made different from the actual scale so that each layer or each part can be recognized on the drawing.

(Embodiment)
In the present embodiment, as an example of an electro-optical device, an active matrix liquid crystal display device including a thin film transistor (hereinafter referred to as TFT) as a pixel switching element will be described as an example. This liquid crystal display device can be suitably used, for example, as a light modulation element (light valve) of a projection type display device (liquid crystal projector) described later.

“Configuration of LCD”
FIG. 1 is a schematic plan view showing the configuration of the liquid crystal display device. 2 is a schematic cross-sectional view taken along the line HH ′ of the liquid crystal display device shown in FIG. FIG. 3 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal display device. Hereinafter, the configuration of the liquid crystal display device will be described with reference to FIGS.

  As shown in FIGS. 1 and 2, the liquid crystal display device 1 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are disposed to face each other, and a liquid crystal layer 15 that is sandwiched between the pair of substrates. For example, a glass substrate, a transparent substrate such as a quartz substrate, or a silicon substrate is used as the first substrate 11 constituting the element substrate 10 and the second substrate 12 constituting the counter substrate 20.

  The element substrate 10 is slightly larger than the counter substrate 20, and both substrates are bonded via a sealing material 14 arranged in a frame shape, and liquid crystal having positive or negative dielectric anisotropy is sealed in the gap. A liquid crystal layer 15 is formed. For example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed as the sealing material 14. A gap material (not shown) for keeping the distance between the pair of substrates constant is mixed in the seal material 14.

  A light shielding layer 18 is similarly provided in a frame shape inside the sealing material 14 arranged in a frame shape on the counter substrate 20 side. The light shielding layer 18 is made of, for example, a light shielding metal or metal oxide, and the inside of the light shielding layer 18 is a display region E having a plurality of pixels P. Although not shown in FIG. 1, the element substrate 10 is also provided with a light shielding portion that divides a plurality of pixels P in a plane. The display area E may include dummy pixels.

  A data line driving circuit 22 is provided between one side of the first substrate 11 and the sealing material 14 along the one side. Further, an inspection circuit 25 is provided inside the sealing material 14 along the other one side facing the one side. Further, a scanning line driving circuit 24 is provided inside the sealing material 14 along the other two sides orthogonal to the one side and facing each other. A plurality of wirings (not shown) that connect the two scanning line driving circuits 24 are provided inside the sealing material 14 on the other side facing the one side.

Wirings connected to the data line driving circuit 22 and the scanning line driving circuit 24 are connected to a plurality of external connection terminals 61 arranged along the one side. Thereafter, the direction along the one side is the X direction, the direction along the other two sides orthogonal to the one side and facing each other is the Y direction, the X direction and the Y direction are orthogonal to the element substrate. The direction from 10 to the counter substrate 20 will be described with the Z direction and the Z (+) direction upward.
The Z direction is an example of the “first direction” in the present invention.

  As shown in FIG. 2, on the surface of the first substrate 11 on the Z (+) direction side, a light-transmissive pixel electrode 27 provided for each pixel P, a TFT 30 as a switching element, a signal wiring, An alignment film 28 covering these is provided. In addition, a light shielding structure is employed that prevents light from entering the semiconductor layer in the TFT 30 to make the switching operation unstable.

  On the surface of the second substrate 12 on the Z (−) direction side, a light shielding layer 18, an interlayer insulating layer (not shown) formed so as to cover it, and a common provided so as to cover the interlayer insulating layer An electrode 31 and an alignment film 32 that covers the common electrode 31 are provided.

  As shown in FIG. 1, the light shielding layer 18 is provided in a frame shape at a position overlapping the scanning line driving circuit 24 and the inspection circuit 25 in plan view. Thus, the light incident from the counter substrate 20 side is shielded, and the malfunction of the peripheral circuits including these drive circuits due to the light is prevented. Further, unnecessary stray light is shielded from entering the display area E, and high contrast in the display of the display area E is ensured.

  The common electrode 31 is made of, for example, a transparent conductive film such as ITO (Indium Tin Oxide), covers the interlayer insulating layer, and includes the element substrate 10 by the vertical conduction portions 26 provided at the four corners of the counter substrate 20 as shown in FIG. It is electrically connected to the side wiring.

  The alignment film 28 covering the pixel electrode 27 and the alignment film 32 covering the common electrode 31 are selected based on the optical design of the liquid crystal display device 1. For example, a material in which an inorganic material such as SiOx (silicon oxide) is formed using a vapor phase growth method and aligned substantially perpendicularly to liquid crystal molecules can be used.

  As illustrated in FIG. 3, the liquid crystal display device 1 includes a plurality of scanning lines 3 a and a plurality of data lines 6 a that are insulated from each other and orthogonal to each other in at least the display region E, and a capacitor line 3 b. The direction in which the scanning line 3a extends is the X direction, and the direction in which the data line 6a extends is the Y direction.

  A pixel electrode 27, a TFT 30, and a capacitive element 16 are provided in a region divided by the scanning line 3a, the data line 6a, the capacitive line 3b, and these signal lines, and these constitute a pixel circuit of the pixel P. doing.

  The scanning line 3a is electrically connected to the gate of the TFT 30, and the data line 6a is electrically connected to the data line side source / drain region of the TFT 30. The pixel electrode 27 is electrically connected to the pixel electrode side source / drain region of the TFT 30.

  The data line 6a is connected to the data line driving circuit 22 (see FIG. 1), and is supplied with image signals D1, D2,..., Dn supplied from the data line driving circuit 22. The scanning line 3a is connected to the scanning line driving circuit 24 (see FIG. 1), and is supplied with scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 24.

  The image signals D1 to Dn supplied from the data line driving circuit 22 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 24 supplies the scanning signals SC1 to SCm to the scanning line 3a in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal display device 1, the TFT 30 as a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are pixel electrodes at a predetermined timing. 27 is written. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 15 through the pixel electrode 27 is held for a certain period between the pixel electrode 27 and the common electrode 31 disposed to face each other through the liquid crystal layer 15. The

  In order to prevent deterioration (leakage) of the held image signals D1 to Dn, the capacitive element 16 is connected in parallel with the liquid crystal capacitance formed between the pixel electrode 27 and the common electrode 31. The capacitive element 16 is provided between the pixel electrode side source / drain region of the TFT 30 and the capacitive line 3b.

  Such a liquid crystal display device 1 is, for example, a transmissive type, and adopts an optical design of a normally white mode in which a pixel P is brightly displayed when not driven and a normally black mode in which a dark display is displayed when not driven. . Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

`` Pixel configuration ''
4 to 7 are schematic plan views showing the configuration of the pixels in the liquid crystal display device. FIG. 8 is a schematic cross-sectional view of the pixel along the line AA ′ shown in FIGS. Hereinafter, the planar structure and cross-sectional structure of the pixel will be described with reference to FIGS.

  FIG. 4 is a schematic plan view showing layers from the light shielding film to the gate electrode in the pixel P. FIG. 5 is a schematic plan view showing layers from the first capacitance electrode to the second capacitance electrode. FIG. 6 is a schematic plan view showing layers from the third capacitor electrode to the data line. FIG. 7 is a schematic plan view showing layers from the capacitor line to the pixel electrode.

  First, as shown in FIG. 4, a scanning line 3 a which is an example of a light shielding film is provided in a non-opening region extending in the X direction. The scanning line 3a uses a light-shielding conductive member, and at least a part of the non-opening region is configured by the scanning line 3a. Examples of the light-shielding conductive material include W (tungsten), Ti (titanium), TiN (titanium nitride), and the like.

  The TFT 30 shown in FIG. 3 is provided in the non-opening region extending in the Y direction. By providing the TFT 30 in a non-opening region having a light shielding property, an optical malfunction of the TFT 30 is prevented and an aperture ratio in the opening region is secured.

  Specifically, as shown in FIG. 4, the TFT 30 includes a semiconductor layer 30a having a data line side source / drain region 30s, a pixel electrode side source / drain region 30d, and a channel region 30c. As described above, the semiconductor layer 30a is disposed in the non-opening region extending in the Y direction.

  Further, the TFT 30 is provided with a gate electrode 30g along the scanning line 3a in the non-opening region. In the gate electrode 30g, a portion extending in the X direction overlaps the channel region 30c in plan. The gate electrode 30g is electrically connected to the scanning line 3a through contact holes CNT51 and CNT52 provided between a portion extending in the X direction and the scanning line 3a. Note that the gate electrode 30g functions as a scanning line, similarly to the scanning line 3a that also serves as a light-shielding film provided below the TFT 30, and can be referred to as a second scanning line.

  Since the scanning line 3a is disposed on the lower layer side than the semiconductor layer 30a, the scanning line 3a is formed wider than the semiconductor layer 30a of the TFT 30, so that the channel region 30c of the TFT 30 with respect to light from a liquid crystal projector or the like. Can be shielded almost or completely. As a result, when the liquid crystal display device 1 is operated, the light leakage current in the TFT 30 is reduced, the contrast ratio can be improved, and high-quality image display is possible. Note that a substantially rectangular opening area surrounded by the non-opening area is a pixel P area.

  Next, as shown in FIG. 5, on the gate electrode 30g in the non-opening region, the island-shaped first capacitor electrode 16a, the first dielectric layer 16b (see FIG. 8), the second capacitor electrode 16c, Are sequentially stacked. The first capacitor electrode 16a is an example of the “first electrode” in the present invention, the second capacitor electrode 16c is an example of the “second electrode” in the present invention, and the first dielectric layer 16b is in the present invention. It is an example of a “first capacitor insulating layer”.

  The second capacitor electrode 16c is composed of two layers, and the first conductive layer 16c1 and the second conductive layer 16c2 are stacked from the first substrate 11 side. Of the second capacitor electrode 16c, the second conductive layer 16c2 is provided up to a region overlapping the pixel electrode side source / drain region 30d of the semiconductor layer 30a in a planar manner. In the region, the second conductive layer 16c2 is electrically connected to the pixel electrode side source / drain region 30d of the semiconductor layer 30a through the contact hole CNT53. The contact hole CNT53 is an example of the “second contact hole” in the present invention, and the pixel electrode side source / drain region 30d of the semiconductor layer 30a is an example of the “semiconductor layer of the transistor” in the present invention.

  A first insulating film CAPA41a used as an etching stopper when the second capacitor electrode 16c is formed is provided in a region overlapping the outer edge of the second capacitor electrode 16c in a plan view. In FIG. 5, the outer edge (outline) of the first insulating film CAPA41a is indicated by a broken line, and the area surrounded by the broken line is an opening area where the first insulating film CAPA41a is not formed. The first insulating film CAPA41a is formed so as to cover the outer edge of the island-shaped first capacitor electrode 16a. An opening region of the first insulating film CAPA41a surrounded by a square broken line is formed on the first capacitor electrode 16a protruding from the outer edge of the second capacitor electrode 16c, as indicated by an arrow with a symbol B. Yes. The opening region of the square first insulating film CAPA41a forms part of a contact hole CNT54 (see FIG. 6) described later.

  Next, as shown in FIG. 6, a second dielectric layer 16d (see FIG. 8) and a third capacitor electrode 16e are sequentially stacked on the second capacitor electrode 16c. The third capacitor electrode 16e is provided in an island shape so as to substantially overlap the first capacitor electrode 16a. The third capacitor electrode 16e is an example of the third electrode, and the second dielectric layer 16d is an example of the “second capacitor insulating layer” in the present invention.

  Moreover, the 1st relay electrode 42 and the 3rd relay electrode 43 are each provided in island shape along the X direction in a non-opening area | region. A contact hole CNT 56 is disposed so as to overlap the first relay electrode 42, and a contact hole CNT 54 is disposed so as to overlap the third relay electrode 43. The third relay electrode 43 is an example of the “conductive film” in the present invention, and the contact hole CNT 54 is an example of the “contact hole” in the present invention.

  A data line 6a is provided in a non-opening region extending in the Y direction. The data line 6a is electrically connected to the data line side source / drain region 30s via a contact hole CNT60 provided between a portion extending in the Y direction and the data line side source / drain region 30s. The data line 6a uses a light-shielding conductive member, and at least a part of the non-opening region is constituted by these.

  Next, as shown in FIG. 7, the capacitor line 3b, the second relay electrode 44, and the pixel electrode 27 are provided on the data line 6a. The second relay electrode 44 is electrically connected to the first relay electrode 42 via a contact hole CNT 57 provided between a portion extending in the X direction and the first relay electrode 42.

  The capacitor line 3b is provided along the data line 6a. Specifically, the capacitor line 3b is electrically connected to the third relay electrode 43 through a contact hole CNT58 provided between a portion extending in the X direction and the third relay electrode 43. .

  The pixel electrode 27 is formed in an island shape for each pixel P, and is provided so that the scanning line 3a or the data line 6a and the outer edge overlap in a planar manner. Each pixel P is divided into a matrix by the data lines 6a and the scanning lines 3a, and the end portions of the respective pixels P are formed so as to partially overlap the data lines 6a and the scanning lines 3a. The pixel electrode 27 is electrically connected to the second relay electrode 44 through the contact hole CNT59.

  Next, the structure of the pixel P will be described in more detail with reference to FIG. As shown in FIG. 8, the scanning line 3 a is provided on the first substrate 11. The scanning line 3a has a light shielding property, for example, at least one of metals such as Al (aluminum), Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). It is possible to use a single metal containing one metal, an alloy, a metal silicide, a polysilicide, a nitride, or a laminate of these.

  On the scanning line 3a, a base insulating layer 11a made of, for example, silicon oxide is provided so as to cover the first substrate 11 and the scanning line 3a. Further, an island-shaped semiconductor layer 30a is provided on the base insulating layer 11a.

  The semiconductor layer 30a is made of, for example, a polycrystalline silicon film, and impurity ions are implanted to form an LDD (Light doped Drain) structure. The data line side source / drain region 30s, the channel region 30c, and the pixel electrode side source / drain region 30d are formed. Have

  A first interlayer insulating layer (gate insulating layer) 11b is formed on the semiconductor layer 30a so as to cover the semiconductor layer 30a and the base insulating layer 11a. Further, a gate electrode 30g is provided at a position facing the channel region 30c with the first interlayer insulating layer 11b interposed therebetween.

  A second interlayer insulating layer 11c is provided on the gate electrode 30g so as to cover the gate electrode 30g and the first interlayer insulating layer 11b. On the second interlayer insulating layer 11c, the first capacitor electrode 16a, the first dielectric layer 16b, and the second capacitor electrode 16c are sequentially stacked to form the first capacitor element 116.

  The first interlayer insulating layer 11b and the second interlayer insulating layer 11c are examples of the “second insulating layer” in the present invention. The pixel electrode side source / drain region 30d of the semiconductor layer 30a, the first capacitor electrode 16a, It is arranged between. Further, a contact hole CNT53 (see FIG. 5) for connecting the pixel electrode side source / drain region 30d of the semiconductor layer 30a and the first capacitor electrode 16a is disposed.

  The first capacitor electrode 16a is, for example, a polysilicon film, and an opaque metal film containing a metal such as Al (aluminum) or Ag (silver) or an alloy can also be used. The first capacitor electrode 16a is connected to a constant potential, and also functions as a light shielding film that shields the TFT 30 from light.

The first dielectric layer 16b is composed of, for example, a single layer structure composed of a silicon oxide (SiO ₂ ) film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride (SiN) film. Alternatively, it has a multilayer structure. A second capacitor electrode 16c is provided by patterning on the first dielectric layer 16b.

  The second capacitor electrode 16 c is a pixel potential side capacitor electrode electrically connected to the pixel electrode side source / drain region 30 d (semiconductor layer 30 a) of the TFT 30 and the pixel electrode 27. The second capacitor electrode 16c is composed of a two-layer polysilicon film or a two-layer metal film, and is formed by patterning on the pixel electrode 27 side and the first conductive layer 16c1 formed by patterning on the TFT 30 side. Second conductive layer 16c2.

  A first insulating film CAPA41a is formed to cover the end (outer edge) of the first capacitor electrode 16a, and a second insulating film CAPA41b is formed to cover the outer edge of the second capacitor electrode 16c. That is, the first insulating film CAPA41a is formed so as to cover the outer edge of the first capacitor electrode 16a between the first capacitor electrode 16a and the first dielectric layer 16b. The second insulating film CAPA41b is formed between the second conductive layer 16c2 and the second dielectric layer 16d so as to cover the outer edge of the second conductive layer 16c2. The first insulating film CAPA41a is an example of a first interlayer insulating layer, and the second insulating film CAPA41b is an example of a “second interlayer insulating layer” in the present invention.

  The first insulating film CAPA41a prevents an electrical short circuit between the end face of the first capacitor electrode 16a and the end face of the second capacitor electrode 16c, and the second capacitor electrode 16c is etched by dry etching or the like. Used as an etching stopper when forming by processing. The second insulating film CAPA41b prevents an electrical short between the end face of the second capacitor electrode 16c and the end face of the third capacitor electrode 16e, and the third capacitor electrode 16e is formed by an etching process such as dry etching. It is used as an etching stopper when performing. The outer edge (contour) of the first insulating film CAPA41a and the outer edge (contour) of the second insulating film CAPA41b are formed at substantially the same position.

On the second capacitor electrode 16c, a second dielectric layer 16d and a third capacitor electrode 16e are sequentially stacked to form a second capacitor element 216. The third capacitor electrode 16e is an example of the “third electrode” in the present invention. The third capacitor electrode 16e is made of WSi (tungsten silicide).
The second dielectric layer 16d is configured in the same manner as the first dielectric layer 16b. For example, the second dielectric layer 16d is a silicon oxide (SiO ₂ ) film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or the like. It has a single layer structure or a multilayer structure composed of a silicon nitride (SiN) film or the like.

  A third interlayer insulating layer 11d, which is an example of the “insulating layer” in the present invention, is laminated on the third capacitor electrode 16e. The third interlayer insulating layer 11d is formed of a film containing either silicon oxide, silicon nitride, or silicon oxynitride.

  Further, the third relay electrode 43, the data line 6a, the first relay electrode 42 (see FIG. 2), and the like are provided on the third interlayer insulating layer 11d by patterning. The data line 6a is electrically connected to the data line side source / drain region 30s of the semiconductor layer 30a through a contact hole CNT60 penetrating the third interlayer insulating layer 11d to the first interlayer insulating layer 11b. The data line 6a, the first relay electrode 42, and the third relay electrode 43 are made of a conductive material such as a metal film, for example.

  On the third interlayer insulating layer 11d, a fourth interlayer insulating layer 11e and a capacitor line 3b are sequentially provided. The capacitor line 3b is configured to include a metal such as aluminum and is supplied with a constant potential (LCCOM). The capacitor line 3b is electrically connected to the third relay electrode 43 through a contact hole CNT58 that penetrates the fourth interlayer insulating layer 11e.

  A fifth interlayer insulating layer 11f is provided on the capacitor line 3b. A pixel electrode 27 made of an ITO film or the like is provided on the fifth interlayer insulating layer 11f by patterning. The pixel electrode 27 is connected to the second relay electrode 44 (see FIG. 7), the first relay electrode 42 (see FIG. 6), and the second capacitor electrode 16c.

  More specifically, the second conductive layer 16c2 is electrically connected to the first relay electrode 42 via the contact hole CNT56 (see FIG. 6). Further, the first relay electrode 42 is electrically connected to the second relay electrode 44 through a contact hole CNT57 (see FIG. 7). The second relay electrode 44 is electrically connected to the pixel electrode 27 through a contact hole CNT 59 (see FIG. 7). As described above, the second conductive layer 16c2 is electrically connected to the pixel electrode side source / drain region 30d of the semiconductor layer 30a through the contact hole CNT53 (see FIG. 5).

Thus, the second conductive layer 16c2 constituting the second capacitor electrode 16c, together with the first relay electrode 42 and the second relay electrode 44, electrically connects the pixel electrode side source / drain region 30d and the pixel electrode 27. Relay.
The capacitive element 16 includes a first capacitive element 116 and a second capacitive element 216 that are arranged (laminated) in the Z (+) direction and connected in parallel. Specifically, in the Z (+) direction, the first capacitor electrode 16a, the first dielectric layer 16b, the second capacitor electrode 16c, the second dielectric layer 16d, and the third capacitor electrode 16e are stacked, and the first capacitor The electrode 16a, the first dielectric layer 16b, and the second capacitor electrode 16c constitute a first capacitor element 116, and the second capacitor electrode 16c, the second dielectric layer 16d, and the third capacitor electrode 16e constitute a second capacitor element. 216 is configured. The second capacitive electrode 16c is one electrode constituting the first capacitive element 116 and the second capacitive element 216, and the first capacitive electrode 16a and the third capacitive electrode 16e are the first capacitive element 116 and the second capacitive element. It is the other electrode which comprises an element. By electrically connecting the first capacitor electrode 16a and the third capacitor electrode 16e within the contact hole CNT54, the first capacitor element 116 and the second capacitor element 216 are connected in parallel. The capacitive element 16 is configured by the first capacitive element 116 and the second capacitive element 216 thus connected in parallel.

"Contact Area Overview"
The greatest feature of the present invention is that the first capacitor electrode 16a and the third capacitor electrode 16e arranged in different layers are electrically connected by one contact hole (contact hole CNT54), that is, with a smaller contact area. There is in point. The outline of the contact region, which is the greatest feature of the present invention, will be described below.

A region F surrounded by a broken line in FIG. 8 is the contact region described above, and electrically connects the first capacitor electrode 16a and the third capacitor electrode 16e. In the region F, the second interlayer insulating layer 11c, the first capacitor electrode 16a, the first insulating film CAPA41a, the first dielectric layer 16b, the second capacitor electrode 16c, the second insulating film CAPA41b, and the second The dielectric layer 16d, the third capacitor electrode 16e, the third interlayer insulating layer 11d, and the third relay electrode 43 are sequentially stacked in the Z (+) direction.
As described above, the second interlayer insulating layer 11c is an example of the “second insulating layer”, the first capacitor electrode 16a is an example of the “first electrode”, and the first dielectric layer 16b is the “second capacitor”. The first insulating film CAPA41a is an example of the “first interlayer insulating layer”, the second capacitor electrode 16c is an example of the “second electrode”, and the second insulating film CAPA41b is the “first insulating film”. The second dielectric layer 16d is an example of a “second capacitor insulating layer”, the third capacitor electrode 16e is an example of a “third electrode”, and is a third interlayer insulating layer. 11d is an example of an “insulating layer”, and the third relay electrode 43 is an example of a “conductive film”.

In the region F, the outer edge of the first capacitor electrode 16a protrudes from the outer edge of the second capacitor electrode 16c in the X (−) direction intersecting (orthogonal) with the Z direction, and the outer edge of the first capacitor electrode 16a and the second capacitor electrode The outer edge of the third capacitor electrode 16e is disposed between the outer edge of 16c. Further, as viewed from the Z direction, a contact hole CNT54 including at least a part of the outer edge of the third capacitor electrode 16e is formed so as to penetrate the third interlayer insulating layer 11d.
The X (−) direction is an example of the “second direction” in the present invention.

  The contact hole CNT54 is formed to overlap the first capacitor electrode 16a and the third capacitor electrode 16e in a planar manner. Further, the contact hole CNT54 and the second capacitor electrode 16c do not overlap in plan view when viewed from the Z direction, and the first insulating film is formed between the outer edge of the contact hole CNT54 and the outer edge of the second capacitor electrode 16c. The CAPA 41a and the second insulating film CAPA 41b are arranged.

  In the region where the third capacitor electrode 16e extends in the contact hole CNT54, the third interlayer insulating layer 11d on the third capacitor electrode 16e is removed by etching. In the region between the outer edge of the third capacitor electrode 16e and the outer edge of the first capacitor electrode 16a in the contact hole CNT54, the first insulating film CAPA41a, the second insulating film CAPA41b, and the third layer stacked on the first capacitor electrode 16a. The interlayer insulating layer 11d is removed by etching.

  Further, the contact hole CNT 54 is covered with the third relay electrode 43. As a result, in the contact hole CNT54, the third capacitor electrode 16e contacts the third relay electrode 43 on the X (+) direction side with respect to the outer edge of the third capacitor electrode 16e, and the first capacitor on the X (−) direction side. The electrode 16 a is in contact with the third relay electrode 43. That is, the first capacitor electrode 16 a and the third capacitor electrode 16 e are electrically connected via the third relay electrode 43.

  As described above, the contact hole CNT54 and the second capacitor electrode 16c do not overlap in plan view when viewed from the Z direction, and the third interlayer insulating layer is interposed between the second capacitor electrode 16c and the third relay electrode 43. Since 11d exists, it is difficult for the second capacitor electrode 16c and the third relay electrode 43 to be short-circuited.

  The outer edge of the third capacitor electrode 16e is disposed at the center of the contact hole CNT54. Specifically, the distance between the outer edge of the third capacitor electrode 16e and the outer edge (wall surface) of the contact hole CNT54 on the X (−) direction side, and the contact hole on the outer edge of the third capacitor electrode 16e and the X (+) direction side. The distance from the outer edge (wall surface) of the CNT 54 is substantially the same. That is, in the contact hole CNT54, the area of the first capacitor electrode 16a that is in contact with the third relay electrode 43 (the exposed area of the first capacitor electrode 16a) and the third capacitor electrode 16e that is in contact with the third relay electrode 43 (third The exposed area of the capacitor electrode 16e is substantially the same. As a result, for example, the area in contact with the third relay electrode 43 in either the first capacitor electrode 16a or the third capacitor electrode 16e is reduced, and the problem that the contact resistance is increased can be suppressed. Therefore, the first capacitor electrode 16a and the third capacitor electrode 16e can be stably electrically connected.

  In the present embodiment, the first capacitor electrode 16a and the third capacitor electrode 16e arranged in different layers are electrically connected by one contact hole (contact hole CNT54). As a result, the first capacitor element 116 and the second capacitor element 216 are connected in parallel, and the capacitance value per unit area in the pixel P can be increased. Increasing the capacitance value of the capacitive element 16 improves the potential holding characteristics of the pixel electrode 27 and improves display performance such as improving contrast and reducing flicker.

  For example, when a known technique is used, an insulating layer (first insulating film CAPA41a, second insulating film CAPA41b, third interlayer insulating layer 11d) on the first capacitor electrode 16a and an insulating layer (third layer) on the third capacitor electrode 16e are used. Separate contact holes are formed in the interlayer insulating layer 11d), and each contact hole is covered with a conductive film (third relay electrode 43) to electrically connect the first capacitor electrode 16a and the third capacitor electrode 16e. Will be connected to. That is, in the known technique, two electrodes are electrically connected through two contact holes. As described above, in this embodiment, two electrodes arranged in different layers are electrically connected by one contact hole. That is, in this embodiment, one contact hole in the pixel P is reduced compared to the case where a known technique is used, and the aperture ratio of the pixel P can be improved.

"Method of manufacturing electro-optical device"
As described above, the greatest feature of the present invention is that the first capacitor electrode 16a and the third capacitor electrode 16e arranged in different layers are electrically connected through one contact hole (contact hole CNT54). There is in point. Hereinafter, a method for manufacturing an electro-optical device will be described with respect to a contact region (region F in FIG. 8) which is a point of the present invention. In addition, since the electro-optical device manufacturing method other than the contact region uses a known technique, the description thereof is omitted.
FIG. 9 is a process flow for forming a contact region in which stacked capacitor elements (first capacitor element and second capacitor element) are connected in parallel. FIG. 10 is a schematic cross-sectional view showing the state of the contact region in the main process.
Note that FIG. 10 corresponds to the region F in FIG. 8, and illustration of components arranged outside the region F is omitted.
Hereinafter, an outline of a method of manufacturing the electro-optical device in the contact region will be described with reference to FIGS. 9 and 10.

  In step S1 of FIG. 9, the first capacitor electrode 16a is formed on the second interlayer insulating layer 11c. The first capacitor electrode 16a is a polysilicon film deposited by a known technique such as a CVD method, and is patterned into a predetermined shape by the known technique.

  In step S2 of FIG. 9, a first insulating film CAPA41a is formed on the first capacitor electrode 16a. The first insulating film CAPA41a is composed of a film containing either silicon oxide, silicon nitride, or silicon oxynitride, and is deposited by a known technique such as a CVD method. The first insulating film CAPA41a is patterned into a predetermined shape by a known technique so as to cover the outer edge of the first capacitor electrode 16a.

In step S3 of FIG. 9, the first dielectric layer 16b is formed on the first capacitor electrode 16a and the first insulating film CAPA41a. The first dielectric layer 16b is composed of, for example, a single layer structure composed of a silicon oxide (SiO ₂ ) film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride (SiN) film. Or it has a multilayer structure.

  In step S4 of FIG. 9, the second capacitor electrode 16c is formed on the first dielectric layer 16b. The second capacitor electrode 16c is a two-layer polysilicon film, for example, and is deposited by a known technique such as a CVD method. The second capacitor electrode 16c may be composed of a two-layer metal film in addition to the two-layer polysilicon film. The first dielectric layer 16b and the second capacitor electrode 16c are patterned into a predetermined shape by a known technique using the first insulating film CAPA41a as an etching stopper.

  FIG. 10A shows a state immediately after step S4. As shown in the figure, in step S4, the second capacitor electrode 16c is formed so that the outer edge of the first capacitor electrode 16a protrudes from the second capacitor electrode 16c in the X (−) direction intersecting the Z direction. Yes. Further, the first capacitor electrode 16a protruding from the outer edge of the second capacitor electrode 16c is covered with the first insulating film CAPA41a.

  In step S5 of FIG. 9, a second insulating film CAPA41b is formed on the second capacitor electrode 16c. The second insulating film CAPA41b is composed of a film containing either silicon oxide, silicon nitride, or silicon oxynitride, and is deposited by a known technique such as a CVD method. The second insulating film CAPA41b is patterned into a predetermined shape by a known technique so as to cover the outer edge of the second capacitor electrode 16c.

In step S6 of FIG. 9, the second dielectric layer 16d is formed on the second capacitor electrode 16c and the second insulating film CAPA41b. The second dielectric layer 16d has a single layer structure composed of, for example, a silicon oxide (SiO ₂ ) film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride (SiN) film. Or it has a multilayer structure.

  In step S7 of FIG. 9, the third capacitor electrode 16e is formed on the second dielectric layer 16d. The third capacitor electrode 16e is made of WSi (tungsten silicide) and is deposited by a known technique such as sputtering. The third capacitor electrode 16e and the second dielectric layer 16d are patterned into a predetermined shape by a known technique using the second insulating film CAPA41b as an etching stopper.

  FIG. 10B shows a state immediately after step S7. As shown in the figure, in step S7, the third capacitor electrode 16e is arranged such that the outer edge of the third capacitor electrode 16e is disposed between the outer edge of the first capacitor electrode 16a and the outer edge of the second capacitor electrode 16c. Is formed. Further, the first insulating film CAPA41a protruding from the outer edge of the second capacitor electrode 16c is covered with the second insulating film CAPA41b.

In step S8 of FIG. 9, first, a third interlayer insulating layer 11d is formed. At this time, the third interlayer insulating layer 11d is stacked on the third capacitor electrode 16e on the third capacitor electrode 16e. A first insulating film CAPA41a, a second insulating film CAPA41b, and a third interlayer insulating layer 11d are stacked on the first capacitor electrode 16a.
Next, an etching process for forming the contact hole CNT54 is performed. This etching process includes a first etching process for etching the third interlayer insulating layer 11d and a second etching process for etching the second insulating film CAPA41b and the first insulating film CAPA41a. By the first etching process and the second etching process, a contact hole CNT54 that exposes the third capacitor electrode 16e and the first capacitor electrode 16a is formed.

  As described above, the third capacitor electrode 16e is made of tungsten silicide, and the first insulating film CAPA41a, the second insulating film CAPA41b, and the third interlayer insulating layer 11d are made of silicon oxide, silicon nitride, or silicon. It is composed of a film containing any of oxynitrides. The third capacitor electrode 16e in the contact hole CNT54 is exposed in the first etching process and exposed to the etching atmosphere in the second etching process. The tungsten silicide constituting the third capacitor electrode 16e is made of silicon oxide, silicon nitride, or silicon oxynitride constituting the first insulating film CAPA41a, the second insulating film CAPA41b, and the third interlayer insulating layer 11d. It has excellent etching resistance against an etching atmosphere in which a film containing any of them is etched. Accordingly, since the third capacitor electrode 16e is not etched in the first etching step and the second etching step, the etching damage to the third capacitor electrode 16e can be suppressed and the contact hole CNT54 can be formed.

  In addition, since the first insulating film CAPA41a, the second insulating film CAPA41b, and the third interlayer insulating layer 11d are the same type of film, the second etching process can be performed continuously to the first etching process. . In the present embodiment, the first insulating film CAPA 41a, the second insulating film CAPA 41b, and the third interlayer insulating layer 11d are continuously etched using the same resist as an etching mask. That is, the first etching process and the second etching process are continuously processed using the same resist as a mask.

  FIG. 10D shows a state immediately after step S8. As shown in the figure, in the contact hole CNT54, the third interlayer insulating layer 11d stacked on the third capacitor electrode 16e extending from the outer edge of the second capacitor electrode 16c and the first electrode protruding from the outer edge of the third capacitor electrode 16e. The first insulating film CAPA41a, the second insulating film CAPA41b, and the third interlayer insulating layer 11d stacked on the one capacitor electrode 16a are etched (removed). As a result, in the contact hole CNT54, the third capacitor electrode 16e in the region protruding from the outer edge (wall surface) of the contact hole CNT54 and the first capacitor electrode 16a in the region protruding from the outer edge of the third capacitor electrode 16e are exposed. Has been.

  That is, when viewed from the Z direction in which the first capacitor electrode 16a, the second capacitor electrode 16c, and the third capacitor electrode 16e are stacked, the outer edge of the third capacitor electrode 16e is included in the region of the contact hole CNT54. The first capacitor electrode 16a and the third capacitor electrode 16e are exposed across the outer edge of the third capacitor electrode 16e. As described above, the area of the first capacitor electrode 16a exposed in the contact hole CNT54 and the area of the exposed third capacitor electrode 16e exposed in the contact hole CNT54 are substantially the same.

  As described above, step S8 includes a step of forming the contact hole CNT54 that includes the outer edge of the third capacitor electrode 16e as viewed from the Z direction and exposes the first capacitor electrode 16a and the third capacitor electrode 16e.

  Since the third capacitor electrode 16e serves as an etching stopper in the second etching step, the second insulating film CAPA41b and the first insulating film CAPA41a disposed under the third capacitor electrode 16e in the contact hole CNT54 are not etched. .

  In the second etching step of etching the second insulating film CAPA41b and the first insulating film CAPA41a, for example, when etching such as wet etching or isotropic dry etching in which an etching gas is supplied without directivity is performed, the third capacitor electrode The second insulating film CAPA41b and the first insulating film CAPA41a are side-etched at the outer edge of 16e, and an overhang of the third capacitor electrode 16e occurs. If an overhang of the third capacitor electrode 16e occurs, the third relay electrode 43 formed in the next step (step S9) is cut off at the outer edge (step) of the third capacitor electrode 16e, and the third capacitor electrode 16e. And the first capacitor electrode 16a may not be electrically connected. In order to prevent such an overhang of the third capacitor electrode 16e (side etching of the second insulating film CAPA41b and the first insulating film CAPA41a) from occurring, the second etching step described above is performed by reactive ion etching or reactiveness. The treatment is preferably performed by anisotropic dry etching such as ion beam etching. In order to continuously process the first etching step and the second etching step, it is preferable that both the first etching step and the second etching step are performed by anisotropic dry etching.

  Further, the material constituting the third capacitor electrode 16e exhibits good etching selectivity (resistance) when etching a film containing either silicon oxide, silicon nitride, or silicon oxynitride. Tungsten silicide is preferred.

  In step S9 of FIG. 9, the third relay electrode 43 that covers the first capacitor electrode 16a and the third capacitor electrode 16e exposed in the contact hole CNT54 is formed. The third relay electrode 43 is a conductive material such as a metal film, and is formed by a known technique.

  FIG. 10C shows a state immediately after step S9. As shown in the figure, the first capacitor electrode 16a and the third capacitor electrode 16e exposed in the contact hole CNT54 are covered with the third relay electrode 43 and electrically connected by the third relay electrode 43. Yes.

  As described above, the third relay electrode 43 is connected to the capacitor line 3b through the contact hole CNT58. For this reason, the third relay electrode 43 is also formed on the third interlayer insulating layer 11d so as to cover the contact hole CNT54. For example, for the purpose of electrically connecting the first capacitor electrode 16a and the third capacitor electrode 16e, the third relay electrode 43 may be embedded in the contact hole CNT54.

As described above, according to the liquid crystal display device 1 according to the present embodiment, the following effects can be obtained.
The first capacitor electrode 16a and the third capacitor electrode 16e arranged in different layers are electrically connected by one contact hole (contact hole CNT54). As a result, the first capacitor element 116 and the second capacitor element 216 are connected in parallel, and the capacitance value per unit area in the pixel P can be increased. Increasing the capacitance value of the capacitive element 16 improves the potential holding characteristics of the pixel electrode 27 and improves display performance such as improving contrast and reducing flicker.

  For example, when a known technique is used, two electrodes arranged in different layers are electrically connected through contact holes formed in the respective electrodes, that is, through the two contact holes. In this embodiment, since two electrodes arranged in different layers are electrically connected by one contact hole, the number of contact holes in the pixel P is reduced compared to the case of using a known technique, and the pixel The aperture ratio of P can be improved.

  The third capacitor electrode 16e is made of tungsten silicide, and the third interlayer insulating layer 11d, the second insulating film CAPA41b, and the first insulating film CAPA41a are either silicon oxide, silicon nitride, or silicon oxynitride. It is comprised with the film | membrane containing this. Further, tungsten silicide is not easily etched when a film containing either silicon oxide, silicon nitride, or silicon oxynitride is etched, and has good etching resistance. Accordingly, the contact hole CNT54 that suppresses etching damage when continuously etching the third interlayer insulating layer 11d, the second insulating film CAPA41b, and the first insulating film CAPA41a and exposes the first capacitor electrode a and the third capacitor electrode 16e. Can be formed.

  The contact hole CNT54 and the second capacitor electrode 16c do not overlap in plan view when viewed from the Z direction, and the third interlayer insulating layer 11d exists between the second capacitor electrode 16c and the third relay electrode 43. In addition, the second capacitor electrode 16c and the third relay electrode 43 are less likely to be short-circuited.

  In the contact hole CNT54, the area of the first capacitor electrode 16a in contact with the third relay electrode 43 (exposed area of the first capacitor electrode 16a) and the third capacitor electrode 16e in contact with the third relay electrode 43 (third capacitor electrode) 16e (exposed area) is substantially the same. Therefore, for example, the first electrode and the third electrode can be suppressed by reducing the area in contact with the third relay electrode 43 by either the first capacitor electrode 16a or the third capacitor electrode 16e and increasing the contact resistance. Can be electrically connected stably.

  The first etching step for etching the third interlayer insulating layer 11d and the second etching step for etching the second insulating film CAPA41b and the first insulating film CAPA41a are continuously performed using the same resist as a mask. Therefore, the contact hole CNT54 can be formed with the minimum number of photomasks.

  In the present embodiment, in order to suppress a short circuit between the second capacitor electrode 16c and the third relay electrode 43, the second capacitor electrode 16c and the contact hole CNT54 do not overlap in plan view when viewed from the Z direction. did. In order to increase the capacity of the capacitive element 16, it is preferable to increase the formation area of the second capacitive electrode 16c as much as possible. For this reason, the second capacitor electrode 16c and the contact hole CNT54 may be configured to overlap in plan view when viewed from the Z direction.

  Further, in the present embodiment, the first insulating film CAPA41a is formed between the first capacitor electrode 16a and the first dielectric layer 16b, and a short circuit between the end surface of the first capacitor electrode 16a and the second capacitor electrode 16c. The second insulating film CAPA41b is formed between the second conductive layer 16c2 and the second dielectric layer 16d, and a short circuit between the second capacitor electrode 16c and the third capacitor electrode 16e is suppressed. In order to increase the capacitance of the capacitor 16, it is preferable not to provide the first insulating film CAPA41a and the second insulating film CAPA41b, and at least one of the first insulating film CAPA41a and the second insulating film CAPA41b is not provided. There may be.

  Further, the present invention is not limited to an active matrix type liquid crystal display device which is an example of an electro-optical device. For example, also in an active matrix organic electroluminescence display device which is an example of an electro-optical device, a capacitive element is formed in each pixel, and the present invention can be applied. Furthermore, the present invention can also be applied to other electro-optical devices including a capacitive element, and electronic devices such as a semiconductor device including a capacitive element.

(Electronics)
FIG. 11 is a plan view showing a configuration of a three-plate projector using the liquid crystal display device according to this embodiment as a light valve. An example of an electronic apparatus equipped with the display device according to the present embodiment will be described with reference to FIG.

  In the projector 2100, the light emitted from the light source 2102 composed of an ultra-high pressure mercury lamp is R (red), G (green), and B by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. The light is separated into the three primary colors (blue), led to the light valves 100R, 100G, and 100B corresponding to the respective colors, and enters the light valve. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent loss thereof, the B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

The configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal display device 1 in the above-described embodiment, and is image data corresponding to each color of R, G, and B supplied from an external host device (not shown). Driven.
The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. The light representing the color image synthesized by the dichroic prism 2112 is enlarged and projected by the lens unit 2114, and a full color image is displayed on the screen 2120.

  The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmitted images of the light valve 100G are projected as they are. The image formed by the light valve 100G is set so as to have a horizontally reversed relationship.

  In addition to the projector 2100 described with reference to FIG. 11, a projection television or the like can be provided as the electronic device. Furthermore, it is possible to provide a small and lightweight electronic device such as an HMD (Head Mounted Display) or a digital camera using the liquid crystal display device 1 as a monitor. Furthermore, the present invention can be applied to display units of various electronic devices such as mobile computers, in-vehicle devices, audio devices, and information terminal devices.

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display device, 3a ... Scanning line, 3b ... Capacitance line, 6a ... Data line, 10 ... Element board | substrate, 11 ... 1st board | substrate, 11a ... Base insulation layer, 11b ... 1st interlayer insulation layer, 11c ... 2nd Interlayer insulating layer, 11d ... third interlayer insulating layer, 11e ... fourth interlayer insulating layer, 11f ... fifth interlayer insulating layer, 12 ... second substrate, 14 ... sealing material, 15 ... liquid crystal layer, 16 ... capacitive element, 16a ... 1st capacitance electrode, 16b ... 1st dielectric layer, 16c ... 2nd capacitance electrode, 16d ... 2nd dielectric layer, 16e ... 3rd capacitance electrode, 18 ... Light shielding layer, 20 ... Opposite substrate, 22 ... Data line Drive circuit 24 ... Scanning line drive circuit 25 ... Inspection circuit 26 ... Vertical conduction part 27 ... Pixel electrode 28,32 ... Alignment film 30 ... TFT 30a ... Semiconductor layer 30c ... Channel region 30d ... Pixel Electrode side source / drain region, 30 g... Gate electrode, 3 s ... Data line side source / drain region, 31 ... Common electrode, 41a ... First insulating film CAPA, 41b ... Second insulating film CAPA, 42 ... First relay electrode, 43 ... Third relay electrode, 44 ... Second relay electrode 51, 52, 53, 54, 56, 57, 58, 59, 60 ... contact hole CNT, 61 ... external connection terminal, 100G, 100R, 100B ... light valve, 116 ... first capacitor element, 216 ... second capacitor Elements 2100 ... Projector 2102 ... Light source 2106 ... Mirror 2108 ... Dichroic mirror 2112 ... Dichroic prism 2114 ... Lens unit 2120 ... Screen 2121 ... Relay lens system 2122 ... Incident lens 2123 ... Relay lens 2124 ... outgoing lens.

Claims (5)

A first electrode, a second electrode, and a third electrode stacked in a first direction;
A first capacitive insulating layer disposed between the first electrode and the second electrode;
A second capacitive insulating layer disposed between the second electrode and the third electrode;
An insulating layer covering the third electrode;
A first interlayer insulating layer covering an outer edge of the first electrode from between the first electrode and the first capacitor insulating layer;
A second interlayer insulating layer covering an outer edge of the second electrode from between the second electrode and the second capacitor insulating layer;
A contact hole penetrating the insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer;
A conductive film disposed inside the contact hole;
Including
An outer edge of the first electrode projects from an outer edge of the second electrode in a second direction intersecting the first direction;
An outer edge of the third electrode is disposed between an outer edge of the first electrode and an outer edge of the second electrode;
When viewed from the first direction, at least a part of the outer edge of the third electrode is included in the region of the contact hole,
The electro-optical device, wherein the first electrode and the third electrode are connected via the conductive film.   The electro-optical device according to claim 1, wherein an area of the first electrode exposed in the contact hole and an area of the third electrode exposed in the contact hole are substantially equal. .   3. The electro-optical device according to claim 1, wherein the insulating layer includes one of silicon oxide, nitride, and oxynitride, and the third electrode is tungsten silicide. A transistor, and a second insulating layer sandwiched between the semiconductor layer of the transistor and the first electrode,
The second electrode is connected to a semiconductor layer of the transistor through a second contact hole penetrating the second insulating layer and the first capacitor insulating layer. The electro-optical device according to any one of the above.   An electronic apparatus comprising the electro-optical device according to claim 1.

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