JP2016080809A - Electro-optic device, method for manufacturing electro-optic device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device in which excellent display quality can be obtained by reducing roughness on a surface of a pixel electrode caused by a contact part, a method for manufacturing an electro-optic device, and electronic equipment.SOLUTION: An element substrate 10A of an electro-optic device includes: a pixel electrode 15A; a TFT (thin film transistor) 30 disposed corresponding to the pixel electrode 15A; a holding capacitor 16 comprising a dielectric layer 16c disposed between an upper electrode 16a and a lower electrode 16b; an interlayer insulation film 14 including a first interlayer insulation film 14a and a second interlayer insulation film 14b and disposed between the upper electrode 16b and the pixel electrode 15A; a conducting part 8 disposed on the upper electrode 16b and penetrating the first interlayer insulation film 14a; and a contact hole CNT4 disposed in a part of the second interlayer insulation film 14b overlapping the conducting part 8 in a plan view. The pixel electrode 15A is electrically connected to the upper electrode 16b via the contact hole CNT4 and the conducting part 8.SELECTED DRAWING: Figure 8

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus.

  As the electro-optical device, an active drive type liquid crystal device can be given. An active drive type liquid crystal device includes, for each of a plurality of pixels, a pixel electrode, a transistor as a switching element that controls switching of the pixel electrode, and a storage capacitor for holding a potential applied to the pixel electrode. . In the case where the active drive type liquid crystal device is a transmissive type, it is desired that a bright display is possible by making the aperture of the pixel as large as possible. However, if the size of the pixels is reduced to increase the number of pixels included in the display area in order to improve the display quality, the light-shielding area between the pixels other than the pixel openings is narrowed. When the storage capacitor is arranged in the light shielding region, the area of the capacitor electrode in the storage capacitor is reduced, and as a result, there is a problem that it is difficult to secure a desired electric capacity.

In order to improve such a problem, for example, in Patent Document 1, a transparent first electrode layer, which is provided between a pixel electrode and a substrate and overlaps a plurality of pixel electrodes in plan view, is provided on the pixel electrode. An electro-optical device having a storage capacitor in which a light-transmitting second electrode layer electrically connected and a light-transmitting dielectric layer interposed between the first electrode layer and the second electrode layer are stacked. It is disclosed.
According to the electro-optical device of Patent Document 1, since the storage capacitor has translucency, even if the storage capacitor is disposed in the opening of the pixel, the display light transmitted through the opening is not affected. Therefore, it is possible to provide an electro-optical device with excellent display quality by securing a desired electric capacity.

JP 2012-215744 A

  In the electro-optical device disclosed in Patent Document 1, a relay layer is formed between the transistor and the storage capacitor on the substrate, and the relay layer reaches the interlayer insulating film between the relay layer and the first electrode layer of the storage capacitor. A first contact hole is formed to electrically connect the first electrode layer and the transistor via the relay layer. Further, a second contact hole reaching the relay layer is formed in the interlayer insulating film between the relay layer and the pixel electrode, and the relay layer and the pixel electrode are electrically connected. Thereby, the pixel electrode is electrically connected to the first electrode layer of the storage capacitor and the transistor through the second contact hole and the relay layer.

On the other hand, since the relay layer is located below the first electrode layer of the storage capacitor on the substrate, the second contact hole is deeper than the first contact hole. Therefore, in order to achieve an electrically stable connection, it is desirable to make the planar size of the second contact hole larger than that of the first contact hole. That is, a second contact hole having an aspect ratio larger than that of the first contact hole is formed.
However, when the aspect ratio of the second contact hole connected to the pixel electrode is increased, the alignment state of the liquid crystal molecules in the concavo-convex portion caused by the second contact hole generated on the pixel electrode is different from that on the pixel electrode. There is a problem that it is difficult to achieve uniform display quality on the pixel electrode because it is more easily disturbed than the portion.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  [Application Example] An electro-optical device according to this application example includes a pixel electrode, a transistor provided corresponding to the pixel electrode, an upper electrode and a lower electrode, and between the upper electrode and the lower electrode. A dielectric capacitor provided on the upper electrode, an interlayer insulating film provided between the upper electrode and the pixel electrode, and an interlayer insulating film provided on the upper electrode. A conductive portion penetrating the film, and the pixel electrode is electrically connected to the upper electrode through the conductive portion.

  According to this application example, since the conductive portion that electrically connects the pixel electrode and the upper electrode is provided through the interlayer insulating film on the upper electrode, a contact hole is formed in the interlayer insulating film. Compared with the case where the pixel electrode and the upper electrode are connected, the unevenness of the surface of the pixel electrode caused by the conductive portion can be reduced. Accordingly, it is possible to provide an electro-optical device having excellent display quality, in which deterioration of display quality due to unevenness of the pixel electrode surface is suppressed.

In the electro-optical device according to the application example, each of the upper electrode and the lower electrode is made of a metal oxide, has translucency and conductivity, and the conductive portion is made of a metal or a metal compound. It is preferable to include at least one conductive layer.
According to this configuration, even if the translucent and conductive upper electrode and the lower electrode, that is, the storage capacitor are arranged in the opening region of the pixel having the pixel electrode, the desired electric capacitance can be reduced without affecting the display. It can be secured. On the other hand, by using a metal or a metal compound that has a lower resistance than the metal oxide as the conductive portion, electrical connection between the pixel electrode and the storage capacitor can be reliably performed. In addition, since different materials are used for the upper electrode and the conductive portion, it is possible to reduce the occurrence of problems such as etching of the upper electrode during patterning of the conductive portion, compared to the case where the same material is used.

In the electro-optical device according to the application example, the interlayer insulating film is provided between the first interlayer insulating film, the first interlayer insulating film, and the pixel electrode, and is made of a material different from the first interlayer insulating film. And the second interlayer insulating film having a thickness smaller than that of the first interlayer insulating film, wherein the conductive portion penetrates the first interlayer insulating film and overlaps the conductive portion in plan view. A contact hole may be provided in the insulating film portion.
According to this configuration, the upper electrode and the pixel electrode are connected via the conductive portion that penetrates the first interlayer insulating film and the contact hole provided in the second interlayer insulating film that is thinner than the first interlayer insulating film. Are electrically connected. Therefore, the unevenness of the surface of the pixel electrode caused by the contact hole can be reduced as compared with the case where the contact hole is provided in the interlayer insulating film including the first interlayer insulating film and the second interlayer insulating film. That is, it is possible to provide an electro-optical device having excellent display quality, in which deterioration of display quality due to unevenness on the pixel electrode surface is suppressed.

In the electro-optical device according to the application example described above, it is preferable that the first interlayer insulating film is an NSG (Non doped Silicate Glass) film and the second interlayer insulating film is a BSG (Boron doped Silicate Glass) film.
According to this configuration, since the BSG film is more hygroscopic than the NSG film, it is possible to suppress the display function from being deteriorated due to the lowering of the insulating function of the interlayer insulating film due to the ingress of moisture. That is, an electro-optical device having excellent display quality and reliability quality can be provided.

  Application Example A method of manufacturing an electro-optical device according to this application example includes a pixel electrode, a transistor provided corresponding to the pixel electrode, an upper electrode and a lower electrode, the upper electrode, and the lower electrode. And a storage capacitor configured to include a dielectric layer provided between the transistor and the pixel electrode on the substrate. , Forming a first conductive film and patterning to form the lower electrode, forming the dielectric layer covering the lower electrode, and second conductive covering the dielectric layer A step of forming a film, a step of forming and patterning a third conductive film that covers the second conductive film, and patterning the second conductive film. And forming the upper electrode Forming an interlayer insulating film covering the upper electrode and the conductive portion; removing a portion of the interlayer insulating film overlapping the conductive portion in a plane; and forming a fourth conductive film covering the interlayer insulating film. Forming the pixel electrode by patterning with a film.

  According to this application example, the conductive portion exposed through the interlayer insulating film is formed by removing the portion of the interlayer insulating film that overlaps the conductive portion in plan. Therefore, when the pixel electrode is formed by forming and patterning the fourth conductive film covering the interlayer insulating film, the conductive portion and the pixel electrode can be electrically connected. Therefore, the unevenness of the surface of the pixel electrode caused by the conductive portion can be reduced as compared with the case where the contact hole is formed in the interlayer insulating film to electrically connect the upper electrode and the pixel electrode. That is, it is possible to manufacture an electro-optical device having excellent display quality by suppressing a decrease in display quality due to unevenness on the surface of the pixel electrode.

In the method of manufacturing the electro-optical device according to the application example, the first conductive film and the second conductive film are formed using a metal oxide so that each of the first conductive film and the second conductive film has translucency and conductivity. The third conductive film is preferably formed using a metal or a metal compound so as to include at least one conductive layer.
According to this method, by using the metal oxide and forming the first conductive film and the second conductive film so as to have translucency and conductivity, a translucent storage capacitor can be formed. If the storage capacitor is translucent, the display is not affected even if the storage capacitor is arranged in the opening region of the pixel. In other words, the degree of freedom of arrangement of the storage capacitor in design is improved, and a desired electric capacity can be realized regardless of the size of the pixel. In addition, since the second conductive film and the third conductive film are formed of different materials, there is a problem that the second conductive film is etched when the conductive film is formed by patterning the third conductive film. Can be reduced. Therefore, by patterning the second conductive film after forming the conductive portion, the upper electrode can be formed with high positional accuracy with respect to the conductive portion.

In the method of manufacturing the electro-optical device according to the application example, the step of forming the interlayer insulating film includes the step of forming a first interlayer insulating film that covers the upper electrode and the conductive portion, and the conductive layer in a planar manner. Removing the portion of the first interlayer insulating film that overlaps with the first interlayer insulating film, and using a material different from that of the first interlayer insulating film, covering the first interlayer insulating film with a thickness smaller than that of the first interlayer insulating film Including a step of forming a two-layer insulating film, a step of forming a through-hole penetrating the portion of the second interlayer insulating film that overlaps the conductive portion in a plane, and the step of forming the pixel electrode includes the steps of: The fourth conductive film is formed so as to cover the through hole.
According to this method, the upper electrode and the pixel electrode are electrically connected via the conductive portion that penetrates the first interlayer insulating film and the contact hole formed in the second interlayer insulating film. The film thickness of the second interlayer insulating film is thinner than that of the first interlayer insulating film. Accordingly, the unevenness of the surface of the pixel electrode caused by the contact hole can be reduced as compared with the case where the contact hole is formed in the interlayer insulating film including the first interlayer insulating film and the second interlayer insulating film. That is, it is possible to manufacture an electro-optical device having excellent display quality by suppressing a decrease in display quality due to unevenness on the surface of the pixel electrode. Further, for example, an electro-optical device with improved reliability quality can be manufactured by forming the first interlayer insulating film and the second interlayer insulating film using different materials to form the interlayer insulating film.

In the method of manufacturing the electro-optical device according to the application example described above, the step of removing the portion of the interlayer insulating film or the portion of the first interlayer insulating film that overlaps the conductive portion in a planar manner includes the step of removing the surface of the interlayer insulating film. Alternatively, it is preferable that the surface of the first interlayer insulating film is flattened to expose the conductive portion.
According to this method, the surface of the interlayer insulating film or the surface of the first interlayer insulating film can be flattened, and display defects caused by the unevenness of the surface can be reduced.

  [Application Example] An electronic apparatus according to this application example includes the electro-optical device according to the application example described above.

[Application Example] An electronic apparatus according to this application example includes an electro-optical device manufactured by using the electro-optical device manufacturing method described in the application example.
According to these configurations, an electronic device having excellent display quality can be provided.

(A) is a schematic plan view which shows the structure of a liquid crystal device, (b) is a schematic sectional drawing in alignment with the H-H 'line | wire of the liquid crystal device shown to the same figure (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. The schematic plan view which shows arrangement | positioning of a pixel. FIG. 2 is a schematic plan view showing the arrangement of thin film transistors, electrodes related to the thin film transistors, and scanning lines in the pixel. FIG. 6 is a schematic plan view showing an arrangement of data lines, storage capacitors, etc. in a pixel of a conventional example. FIG. 6 is a schematic cross-sectional view showing the structure of a conventional element substrate taken along line B-B ′ of FIG. 5. The schematic plan view which shows arrangement | positioning of the storage capacity and the contact hole in an Example. FIG. 8 is a schematic cross-sectional view showing the structure of the element substrate of the example cut along line A-A ′ in FIG. 7. (A) is a schematic plan view which shows the contact part of the pixel electrode of an Example, (b) is a schematic plan view which shows the contact part of the pixel electrode of a prior art example. 6 is a flowchart showing a method for manufacturing a liquid crystal device. (A)-(e) is a schematic sectional drawing which shows the manufacturing method of a liquid crystal device. (F)-(j) is a schematic sectional drawing which shows the manufacturing method of a liquid crystal device. Schematic which shows the structure of the projection type display apparatus as an electronic device.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the present embodiment, an active drive type liquid crystal device including a thin film transistor (hereinafter referred to as TFT) for each pixel will be described as an example of an electro-optical device. This liquid crystal device can be suitably used, for example, as a light modulation element (liquid crystal light valve) of a projection display device (liquid crystal projector) described later.

(First embodiment)
<Electro-optical device>
First, the configuration of a liquid crystal device as an electro-optical device of the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1A is a schematic plan view showing the configuration of the liquid crystal device, and FIG. 1B is a schematic cross-sectional view along the line HH ′ of the liquid crystal device shown in FIG. FIG. 2 is an equivalent circuit diagram showing an electrical configuration of the liquid crystal device.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 according to the present embodiment includes an element substrate 10 and a counter substrate 20 that are arranged to face each other, and a liquid crystal layer 50 that is sandwiched between the pair of substrates. Have. As the base material 10s of the element substrate 10 and the base material 20s of the counter substrate 20, for example, a quartz substrate or a glass substrate having translucency is used. Note that translucency in this specification refers to a property of transmitting light having a wavelength in the visible light region by at least 85%.

  The element substrate 10 is slightly larger than the counter substrate 20. The element substrate 10 and the counter substrate 20 are bonded together via a sealing material 40 arranged in a frame shape along the outer edge portion of the counter substrate 20, and liquid crystal having positive or negative dielectric anisotropy is enclosed in the gap. Thus, the liquid crystal layer 50 is configured. As the sealing material 40, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. A spacer (not shown) is mixed in the sealing material 40 to keep the distance between the pair of substrates constant.

  Inside the sealing material 40, a display region E in which a plurality of pixels P are arranged in a matrix is provided. The counter substrate 20 is provided with a parting portion 21 that surrounds the display area E between the sealing material 40 and the display area E. The parting portion 21 is made of, for example, a light shielding metal or metal oxide. Note that the display area E may include dummy pixels arranged so as to surround the plurality of pixels P in addition to the plurality of pixels P contributing to display.

  The element substrate 10 is provided with a terminal portion in which a plurality of external connection terminals 104 are arranged. A data line driving circuit 101 is provided between the first side portion along the terminal portion of the element substrate 10 and the sealing material 40. In addition, an inspection circuit 103 is provided between the sealing material 40 and the display area E along the second side facing the first side. Further, a scanning line driving circuit 102 is provided between the seal material 40 and the display region E along the third side and the fourth side that are orthogonal to the first side and face each other. A plurality of wirings 105 that connect the two scanning line driving circuits 102 are provided between the sealing material 40 on the second side and the inspection circuit 103.

  Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged along the first side portion. Hereinafter, the direction along the first side is referred to as the X direction, and the direction along the third and fourth sides is referred to as the Y direction. Further, in this specification, viewing from the normal direction of the counter substrate 20 orthogonal to the X direction and the Y direction is referred to as “planar view” or “planar”.

  As shown in FIG. 1B, the element substrate 10 includes a base material 10s, a TFT 30 formed on the surface of the base material 10s on the liquid crystal layer 50 side, the pixel electrode 15, and an alignment film 18 that covers the pixel electrode 15 and the like. have. The TFT 30 and the pixel electrode 15 are components of the pixel P. Details of the pixel P will be described later.

  The counter substrate 20 includes a base material 20s, a parting portion 21, a planarization layer 22, a counter electrode 23, an alignment film 24, and the like, which are sequentially stacked on the surface of the base material 20s on the liquid crystal layer 50 side.

  The parting part 21 surrounds the display area E as shown in FIG. 1A, and is provided at a position overlapping the scanning line driving circuit 102 and the inspection circuit 103 in plan view. Thus, the light incident on the peripheral circuit including these drive circuits from the counter substrate 20 side is blocked, and the peripheral circuit has a role of preventing malfunction due to the light. Further, unnecessary stray light is shielded so as not to enter the display area E, and a high contrast in the display of the display area E is ensured.

  The planarization layer 22 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the parting portion 21 with translucency. Such a planarization layer 22 is a silicon oxide film formed by using, for example, a plasma CVD method, and has a thickness that can relax the surface unevenness of the counter electrode 23 formed on the planarization layer 22. Have.

  The counter electrode 23 is made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), for example, covers the planarization layer 22 and is formed at the four corners of the counter substrate 20 as shown in FIG. The vertical conduction portion 106 provided is electrically connected to the wiring on the element substrate 10 side.

  The alignment film 18 that covers the pixel electrode 15 and the alignment film 24 that covers the counter electrode 23 are set based on the optical design of the liquid crystal device 100, and an oblique deposition film (inorganic alignment film) of an inorganic material such as silicon oxide is used. It has been adopted. The alignment films 18 and 24 may employ an organic alignment film such as polyimide in addition to the inorganic alignment film.

  Such a liquid crystal device 100 is a transmission type, and adopts an optical design of a normally white mode in which the pixel P is brightly displayed when not driven and a normally black mode in which the pixel P is darkly displayed when not driven. Polarizing elements are arranged and used according to the optical design on the light incident side and the light exit side, respectively.

  Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIG. The liquid crystal device 100 includes a plurality of scanning lines 3 and a plurality of data lines 6 a as signal lines that are insulated and orthogonal to each other at least in the display region E, and a capacitor line 7. In FIG. 2, the capacitor line 7 is shown so as to be parallel to the data line 6a. However, in this embodiment, one capacitor electrode of a pair of capacitor electrodes of the storage capacitor 16 described later is the capacitor line 7. It is comprised so that the function of may be fulfilled.

  A pixel electrode 15, a TFT 30, and a storage capacitor 16 are provided in a region divided by the scanning line 3 and the data line 6a, and these constitute a pixel circuit of the pixel P.

  The scanning line 3 is electrically connected to the gate of the TFT 30, the data line 6 a is electrically connected to the first source / drain region of the TFT 30, and the pixel electrode 15 is electrically connected to the second source / drain region of the TFT 30. Has been.

  The data line 6a is connected to the data line driving circuit 101 (see FIG. 1). Image signals D1, D2,..., Dn are supplied from the data line driving circuit 101 to each pixel P via the data line 6a. The scanning line 3 is connected to the scanning line driving circuit 102 (see FIG. 1). The scanning signals SC1, SC2,..., SCm are supplied to each pixel P from the scanning line driving circuit 102 via the scanning line 3.

  The image signals D1 to Dn supplied from the data line driving circuit 101 may be supplied to the data lines 6a in the order of lines in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 102 supplies the scanning signals SC <b> 1 to SCm to the scanning line 3 in a pulse-sequential manner at a predetermined timing.

  In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 15 at a predetermined timing. It is the structure written in. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 50 via the pixel electrode 15 is held between the pixel electrode 15 and the counter electrode 23 for a certain period.

  In order to prevent the held image signals D1 to Dn from leaking, the holding capacitor 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the counter electrode 23. The storage capacitor 16 is provided between the second source / drain region of the TFT 30 and the capacitor line 7.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG.

  The inspection circuit 103 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

Next, the configuration of the pixel P in the liquid crystal device 100 will be described with reference to FIG. FIG. 3 is a schematic plan view showing the arrangement of pixels.
As shown in FIG. 3, the pixel P in the liquid crystal device 100 has, for example, a substantially square (substantially square) opening region in a plan view. The opening area is surrounded by a light-shielding non-opening area extending in the X direction and the Y direction and provided in a lattice shape.

  A scanning line 3 shown in FIG. 2 is provided in the non-opening region extending in the X direction. The scanning line 3 uses a light-shielding conductive member, and the scanning line 3 constitutes at least a part of the non-opening region.

  Similarly, a data line 6a shown in FIG. 2 is provided in the non-opening region extending in the Y direction. The data line 6a also uses a light-shielding conductive member, and at least a part of the non-opening region is constituted by these.

  The non-opening region is constituted not only by the signal lines provided on the element substrate 10 side, but also by a light shielding film provided in the same layer as the parting portion 21 and patterned in a lattice pattern on the counter substrate 20 side. Has been.

  The TFT 30 shown in FIG. 2 is provided near the intersection of the non-opening regions. By providing the TFT 30 in the vicinity of the intersection of the non-opening region having the light shielding property, the optical malfunction of the TFT 30 is prevented and the aperture ratio in the opening region is secured. Although the detailed structure of the pixel P will be described later, the width of the non-opening region in the vicinity of the intersecting portion is wider than that in other portions due to the provision of the TFT 30 near the intersecting portion.

  A pixel electrode 15 is provided for each pixel P. The pixel electrode 15 is substantially square in plan view, and is provided in the opening region so that the outer edge of the pixel electrode 15 overlaps the non-opening region. Although not shown in FIG. 3, a translucent storage capacitor 16 is disposed in the opening region. As shown in FIG. 2, the pixel electrode 15 is electrically connected to the second source / drain region of the TFT 30 and the storage capacitor 16. Hereinafter, an electrical connection structure between the pixel electrode 15 and the TFT 30 and the storage capacitor 16 will be described with reference to a conventional example and an example to which the present invention is applied.

<Conventional example>
First, an electrical connection structure between the pixel electrode 15 of the conventional example, the TFT 30, and the storage capacitor 16 will be described with reference to FIGS. 4 is a schematic plan view showing the arrangement of thin film transistors, electrodes and scanning lines related to the thin film transistors, and FIG. 5 is a schematic plan view showing the arrangement of data lines, storage capacitors, etc. in the conventional pixel. FIG. 6 is a schematic cross-sectional view showing the structure of a conventional element substrate taken along line BB ′ of FIG. 5.

  As shown in FIG. 4, the scanning line 3 is provided for each pixel P, extending in the X direction across the plurality of pixels P, and protrudes from the first part 3 a in the Y direction. It has the 2nd part 3b and the 3rd part 3c. Further, the scanning line 3 has a fourth portion 3d whose width is expanded in the X direction and the Y direction as compared with the first portion 3a and the second portion 3b (third portion 3c). The second portion 3b and the third portion 3c protruding in the Y direction are arranged so as to overlap with a data line 6a described later.

  On the scanning line 3, the semiconductor layer 30a of the TFT 30 is disposed in a region extending between the second portion 3b and the third portion 3c with the fourth portion 3d interposed therebetween. The semiconductor layer 30a is made of, for example, high-temperature polysilicon, and has a channel region 30c, a first source / drain region 30s, and a second source / drain region 30d. The first source / drain region 30s is disposed at a position overlapping the third portion 3c of the scanning line 3, and the second source / drain region 30d is disposed at a position overlapping the second portion 3b of the scanning line 3. Yes. A channel region 30c sandwiched between the first source / drain region 30s and the second source / drain region 30d is mainly disposed at a position overlapping the fourth portion 3d of the scanning line 3.

  At the end of the first source / drain region 30s, a contact hole 31 is provided for electrical connection with the data line 6a. At the end of the second source / drain region 30d, a contact hole 32 is provided for electrical connection with the storage capacitor 16 and the pixel electrode 15. That is, in this embodiment, the contact hole 31 functions as a source electrode of the TFT 30, and the contact hole 32 functions as a drain electrode of the TFT 30. Therefore, the contact hole 31 may be referred to as the source electrode 31 and the contact hole 32 may be referred to as the drain electrode 32.

  A gate electrode 30g is arranged at a position overlapping the channel region 30c of the semiconductor layer 30a. The gate electrode 30g has a portion that overlaps the channel region 30c at a position that overlaps the fourth portion 3d of the scanning line 3, and a portion that faces the channel region 30c in the X direction and extends in the Y direction. ing. In the portion extending in the Y direction, a contact hole 33 and a contact hole 34 reaching the lower scanning line 3 are provided. That is, the gate electrode 30g is electrically connected to the scanning line 3 via the two contact holes 33 and 34 provided with the channel region 30c interposed therebetween.

  The TFT 30 includes the semiconductor layer 30a and the gate electrode 30g described above. A first relay layer 4 for electrical connection between the drain electrode 32 of the TFT 30 and the storage capacitor 16 or the pixel electrode 15 is disposed at the intersection between the scanning line 3 where the TFT 30 is disposed and the data line 6a. ing. The first relay layer 4 includes a first portion 4a and a fourth portion 4c protruding from the intersecting portion in the X direction, and a second portion 4b and a third portion 4d protruding from the intersecting portion in the Y direction. have.

  The second portion 4b protruding in the Y direction of the first relay layer 4 is disposed and electrically connected so as to overlap the contact hole 32 functioning as a drain electrode. The other third portion 4d protruding in the Y direction of the first relay layer 4 is disposed so as not to overlap the contact hole 31 functioning as the source electrode.

  A contact hole CNT1 for electrical connection with a second relay layer 6b (see FIG. 5), which will be described later, is located near the end of the first portion 4a protruding in the X direction of the first relay layer 4. Is provided. In FIG. 4, the shape of the contact hole CNT1 is a square in plan view, but is not limited thereto, and may be a circle or an ellipse.

  Each of the scanning line 3 and the first relay layer 4 shown in FIG. 4 is one of the elements constituting the non-opening region shown in FIG.

  As shown in FIG. 5, the data line 6 a is provided so as to extend in the Y direction at a position overlapping the contact holes 31 and 32 of the TFT 30. An independent second relay layer 6b is provided for each pixel P between adjacent data lines 6a in the X direction. The second relay layer 6b is substantially rectangular in plan view, and a contact hole CNT1 is provided in the middle of the longitudinal direction extending in the X direction. As described above, the second relay layer 6b is electrically connected to the first relay layer 4 through the contact hole CNT1.

  As will be described in detail later, the data line 6a and the second relay layer 6b are provided in the same wiring layer on the base material 10s. On the base material 10 s, the lower electrode 16 a of the pair of capacitor electrodes of the storage capacitor 16 extends over the plurality of pixels P on the upper layer of the wiring layer provided with the data line 6 a and the second relay layer 6 b. Is provided. The lower electrode 16a functions as the capacitor line 7 common to the plurality of pixels P. The upper electrode 16b of the pair of capacitor electrodes of the storage capacitor 16 is provided independently for each pixel P between the adjacent data lines 6a. The upper electrode 16b is substantially square in plan view, and the outer edges of the two sides facing each other in the X direction overlap the data line 6a in plan view. In addition, one of the two sides facing the Y direction of the upper electrode 16b overlaps the second relay layer 6b in plan view. The lower electrode 16a and the upper electrode 16b are formed using a transparent conductive film such as ITO or IZO, for example.

  In the second relay layer 6b, contact holes CNT2 and CNT3 are arranged on both sides in the X direction with the contact hole CNT1 interposed therebetween. The contact hole CNT2 and the contact hole CNT3 are provided through the lower electrode 16a so as not to contact the lower electrode 16a. The contact hole CNT2 is provided at a position where the second relay layer 6b and the upper electrode 16b overlap in a plan view, and electrically connects the second relay layer 6b and the upper electrode 16b. The upper electrode 16b is cut away so as not to contact the contact hole CNT3. The contact hole CNT3 is provided for electrical connection between the second relay layer 6b and the pixel electrode 15 (see FIG. 6). The shape of the contact holes CNT2 and CNT3 in plan view is a substantially rectangular shape whose longitudinal direction is along the X direction. The term “substantially rectangular” includes those whose corners are arcuate.

  Each of the data line 6a and the second relay layer 6b shown in FIG. 5 is one of the elements constituting the non-opening region shown in FIG.

  Next, a cross-sectional structure in the electrical connection between the pixel electrode 15 and the TFT 30 of the conventional example will be described with reference to FIG. In order to distinguish between the conventional example and an example described later, in FIG. 6 showing the conventional example, the reference numeral of the pixel electrode is 15B, and the reference numeral of the element substrate having the pixel electrode 15B of the conventional example is 10B.

  As shown in FIG. 6, on the base material 10s of the element substrate 10B of the conventional example, the first layer including the scanning line 3, the second layer including the TFT 30, and the third layer including the first relay layer 4 are sequentially arranged. The fourth layer including the data line 6a, the fifth layer including the storage capacitor 16 and the sixth layer (uppermost layer) including the pixel electrode 15B are formed. A base insulating film 11a is formed between the first layer and the second layer, and an interlayer insulating film 11c is formed between the second layer and the third layer. An interlayer insulating film 12 is formed between the third layer and the fourth layer, an interlayer insulating film 13 is formed between the fourth layer and the fifth layer, and between the fifth layer and the sixth layer. An interlayer insulating film 14 is formed. This prevents a short circuit between the aforementioned elements. In addition, in the base insulating film 11a and the interlayer insulating film 11c to the interlayer insulating film 14, contact holes and the like for making electrical connection between the above-described elements are formed. Hereinafter, each of these elements will be described in order. FIG. 4 shows a planar arrangement of each element from the first layer to the third layer, and FIG. 5 shows a planar arrangement of each element from the fourth layer to the fifth layer.

  First, in the first layer, for example, a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of these containing at least one of refractory metals such as Ti, Cr, Mo, Ta, W, etc. Alternatively, the scanning line 3 made of conductive polysilicon or the like is formed. In particular, the scanning line 3 is preferably formed using metal silicide from the viewpoint of shielding the return light incident from the base material 10s side and not reflecting the incident light incident from the counter substrate 20 side. In the embodiment, the scanning line 3 is formed using WSi (tungsten silicide). The film thickness of the scanning line 3 is about 200 nm, for example.

Next, a base insulating film 11a that covers the scanning lines 3 is formed. The base insulating film 11a is formed using, for example, silicon oxide. The film thickness of the base insulating film 11a is about 450 nm, for example.
Subsequently, a semiconductor layer 30a is formed on the base insulating film 11a in the second layer. The semiconductor layer 30a is made of, for example, polysilicon, and impurity ions are selectively implanted, and the LDD including the first source / drain region 30s, the junction region 30e, the channel region 30c, the junction region 30f, and the second source / drain region 30d. (Lightly Doped Drain) structure is built. The film thickness of the semiconductor layer 30a is approximately 40 nm, for example.

  Next, a gate insulating film 11b covering the semiconductor layer 30a is formed. The gate insulating film 11b is formed using, for example, silicon oxide. The thickness of the gate insulating film 11b is about 55 nm, for example.

  Next, groove-shaped through holes are formed in the base insulating film 11a and the gate insulating film 11b. A gate electrode 30g and a pair of contact holes 33 and 34 are formed by forming and patterning a conductive film so as to fill the through hole. In FIG. 6, the contact hole 34 of the pair of contact holes 33 and 34 is illustrated, and the contact hole 33 is not illustrated. Thereby, a part of the semiconductor layer 30a of the TFT 30 is covered with the contact holes 33 and 34 from the side in a plan view as shown in FIG. 4, and at least from the pair of contact holes 33 and 34 side. Incident light is blocked. The contact holes 33 and 34 are formed so that the lower ends thereof are in contact with the scanning lines 3. Accordingly, the gate electrode 30g and the scanning line 3 existing in a certain row (X direction) are always at the same potential as long as the row is focused.

An example of the conductive film used for the gate electrode 30g is a conductive polysilicon film. The film thickness of the gate electrode 30g is about 100 nm, for example.
Then, an interlayer insulating film 11c covering the gate electrode 30g and the gate insulating film 11b is formed. The interlayer insulating film 11c is formed using, for example, silicon oxide and has a film thickness of, for example, about 300 nm.

  A through hole is formed in the gate insulating film 11b and the interlayer insulating film 11c at a position overlapping with the second source / drain region 30d of the semiconductor layer 30a, and on the interlayer insulating film 11c so as to cover the inside of the through hole. The first relay layer 4 and the contact hole 32 are formed by forming and patterning a conductive film. The first relay layer 4 that is the third layer is formed so as to overlap the gate electrode 30g in plan view (see FIG. 4). Examples of the conductive film used for the first relay layer 4 (third layer) include low resistance wiring materials such as metals such as Al (aluminum) and Ti (titanium) and metal compounds thereof. In addition, the 1st relay layer 4 is not limited to being a single material layer, The multilayer structure which consists of a different material layer may be sufficient.

  Next, an interlayer insulating film 12 that covers the first relay layer 4 is formed. The interlayer insulating film 12 is formed using, for example, silicon oxide and has a film thickness of, for example, about 400 nm. A through-hole penetrating the gate insulating film 11b, the interlayer insulating film 11c, and the interlayer insulating film 12 is formed at a position of the interlayer insulating film 12 overlapping the first source / drain region 30s in the semiconductor layer 30a. In addition, a through hole penetrating the interlayer insulating film 12 is formed at a position overlapping the first portion 4 a in the first relay layer 4 of the interlayer insulating film 12. By forming and patterning a conductive film on the interlayer insulating film 12 so as to cover the inside of these through holes, the data lines 6a and the second relay layer 6b as the fourth layer, the contact holes 31 and A contact hole CNT1 is formed. As the conductive film used for the fourth layer, the same metal or metal compound as that for the third layer can be used.

  Next, an interlayer insulating film 13 is formed to cover the data line 6a and the second relay layer 6b, which are the fourth layer. The interlayer insulating film 13 is formed using, for example, silicon oxide. The film thickness of the interlayer insulating film 13 is approximately 400 nm, for example. Since the surface of the interlayer insulating film 13 is uneven due to the underlying wiring structure, a planarization process such as a CMP (Chemical Mechanical Polishing) process is performed.

  Next, the storage capacitor 16 as the fifth layer is formed on the interlayer insulating film 13 that has been subjected to the planarization process. Specifically, first, the lower electrode 16a of the storage capacitor 16 is formed by forming a transparent conductive film such as ITO or IZO on the interlayer insulating film 13 and patterning it. The film thickness of the lower electrode 16a is about 140 nm, for example. As shown in FIG. 5, the lower electrode 16 a is formed over at least the display region E as a common capacitance line 7 in the plurality of pixels P. In addition, the lower electrode 16a is used to connect a contact hole CNT2 for electrical connection between the upper electrode 16b of the storage capacitor 16 and the second relay layer 6b, and an electrical connection between the pixel electrode 15B and the second relay layer 6b. The contact hole CNT3 is patterned so as to have an opening so as not to contact the contact hole CNT3.

Next, a dielectric layer 16c that covers the lower electrode 16a is formed. The dielectric layer 16c is composed of a plurality of layers formed using dielectric materials having different dielectric constants. The film thickness of the dielectric layer 16c is, for example, about 30 nm to 60 nm. Examples of the dielectric material include hafnium oxide, aluminum oxide, a silicon oxide film, a silicon nitride film, and tantalum oxide (Ta ₂ O ₅ ). By combining these layers having different dielectric constants, a larger electric capacity can be realized while ensuring translucency.

  Next, a through-hole penetrating the interlayer insulating film 13 and the dielectric layer 16c is formed at a position overlapping the second relay layer 6b in plan view. The upper electrode 16b of the storage capacitor 16 and the contact hole CNT2 are formed by patterning a transparent conductive film such as ITO or IZO that covers the dielectric layer 16c so as to cover the inside of the through hole. It is formed. The film thickness of the upper electrode 16b is approximately 140 nm, for example.

  Next, an interlayer insulating film 14 that covers the upper electrode 16b and the contact hole CNT2 is formed. This interlayer insulating film 14 corresponds to the interlayer insulating film in the present invention. The interlayer insulating film 14 includes a first interlayer insulating film 14a and a second interlayer insulating film 14b stacked on the first interlayer insulating film 14a. More specifically, first, an NSG (Non doped Silicate Glass) film covering the upper electrode 16b and the contact hole CNT2 is formed by, for example, a plasma CVD method. Then, for the purpose of alleviating the unevenness of the surface of the NSG film generated by covering the contact holes CNT2 and the like, a planarization process such as a CMP process is performed. The film thickness of the NSG film, that is, the first interlayer insulating film 14a on the upper electrode 16b after the planarization process is about 100 nm, for example. Then, a second interlayer insulating film 14b covering the first interlayer insulating film 14a is formed. The second interlayer insulating film 14b is formed using a material different from that of the first interlayer insulating film 14a so as to be thinner than the first interlayer insulating film 14a. The second interlayer insulating film 14b is, for example, a BSG (Boron doped Silicate) film, and is formed by using, for example, a plasma CVD method. The film thickness of the second interlayer insulating film 14b is about 75 nm, for example. The total film thickness obtained by adding the film thickness of the dielectric layer 16c to the film thickness of the interlayer insulating film 14 where the contact hole CNT3 will be formed later is approximately 475 nm.

  Next, a through-hole penetrating the interlayer insulating film 13, the dielectric layer 16 c and the interlayer insulating film 14 is formed at a position overlapping the second relay layer 6 b in plan view. A pixel electrode 15B and a contact hole CNT3 are formed by forming and patterning a transparent conductive film such as ITO covering the interlayer insulating film 14 so as to cover the inside of the through hole. As illustrated in FIG. 3, the pixel electrode 15 </ b> B is formed so as to overlap with the storage capacitor 16 in the opening region of the pixel P and to overlap the outer edge portion of the pixel electrode 15 </ b> B with the non-opening region. In the present embodiment, light incident from the counter substrate 20 side is transmitted through the counter substrate 20 and the liquid crystal layer 50, and is transmitted through the pixel electrode 15 </ b> B and the storage capacitor 16 disposed in the opening region of the pixel P. It is injected from the side. In the conventional example, the film thickness of the pixel electrode 15B made of a transparent conductive film is about 140 nm. Thereby, it is suppressed that incident light is optically attenuated by passing through the pixel electrode 15 </ b> B and the storage capacitor 16. Further, by setting the film thickness of the pixel electrode 15B to about 140 nm, the coverage of the contact hole CNT3 deeper than the contact hole CNT2 is improved, and the electrical connection between the pixel electrode 15B and the second relay layer 6b is stabilized. It has become. In the conventional example, as shown in FIG. 5, the planar sizes of the contact hole CNT2 and the contact hole CNT3 are substantially the same. On the other hand, as shown in FIG. 6, the depth of the contact hole CNT3 (approximately 875 nm) is deeper than the depth of the contact hole CNT2 (approximately 400 nm). That is, the aspect ratio of the contact hole CNT3 is larger than that of the contact hole CNT2.

<Example>
Next, an electrical connection structure between the pixel electrode and the TFT 30 of the embodiment will be described with reference to FIGS. FIG. 7 is a schematic plan view showing the arrangement of the storage capacitors and contact holes in the example, and FIG. 8 is a schematic cross-sectional view showing the structure of the element substrate of the example taken along the line AA ′ of FIG. In order to distinguish the above-described conventional example from the example, in FIG. 8 showing the example, the reference numeral of the pixel electrode is 15A, and the reference numeral of the element substrate having the pixel electrode 15A of the example is 10A. In addition, arrangement | positioning of TFT30 in the Example, the scanning line 3, and the 1st relay layer 4 is the same as a prior art example. Therefore, hereinafter, the structure after the fourth layer in the element substrate 10A of the embodiment will be described.

  As shown in FIG. 7, the data line 6 a in the embodiment is provided so as to extend in the Y direction at a position overlapping the contact holes 31 and 32 of the TFT 30. An independent second relay layer 6b is provided for each pixel P between adjacent data lines 6a in the X direction. The second relay layer 6b is substantially rectangular in plan view, and a contact hole CNT1 is provided in the middle of the longitudinal direction extending in the X direction. As described above, the second relay layer 6b is electrically connected to the first relay layer 4 through the contact hole CNT1.

  The data line 6a and the second relay layer 6b are provided in the same wiring layer on the base material 10s. On the substrate 10s, the lower electrode 16a of the storage capacitor 16 is provided on the upper layer of the wiring layer provided with the data line 6a and the second relay layer 6b so as to straddle the plurality of pixels P. The lower electrode 16a functioning as the capacitor line 7 is disposed across a plurality of pixels P. The upper electrode 16b of the storage capacitor 16 is provided independently for each pixel P between the adjacent data lines 6a. The upper electrode 16b is substantially square in plan view, and the outer edges of the two sides facing each other in the X direction overlap the data line 6a in plan view. In addition, one of the two sides facing the Y direction of the upper electrode 16b overlaps the second relay layer 6b in plan view.

  In the second relay layer 6b, a contact hole CNT2 is disposed on one side in the X direction (right side in the drawing) across the contact hole CNT1. The contact hole CNT2 is provided through the lower electrode 16a so as not to contact the lower electrode 16a. The contact hole CNT2 is provided at a position where the second relay layer 6b and the upper electrode 16b overlap in a plan view, and electrically connects the second relay layer 6b and the upper electrode 16b. A contact hole CNT4 for electrical connection with the pixel electrode 15A (see FIG. 8) is provided at the lower left corner of the upper electrode 16b. The contact hole CNT4 does not overlap the second relay layer 6b in plan view. The shape of the contact hole CNT2 in plan view is a substantially rectangular shape whose longitudinal direction is along the X direction, and the shape of the contact hole CNT4 in plan view is circular.

  As shown in FIG. 8, the lower electrode 16a of the storage capacitor 16 is formed on the interlayer insulating film 13 covering the data line 6a and the second relay layer 6b which are the fourth layers. The lower electrode 16a is patterned so as to have an opening in a portion overlapping the contact hole CNT2. A dielectric layer 16c is formed to cover the lower electrode 16a. A through hole penetrating the dielectric layer 16c and the interlayer insulating film 13 is formed at a position overlapping the second relay layer 6b, and a transparent conductive film is formed and patterned so as to cover the inside of the through hole. Thus, the upper electrode 16b and the contact hole CNT2 are formed.

  On the upper electrode 16b, the conductive portion 8 penetrating the first interlayer insulating film 14a is formed. A second interlayer insulating film 14b is formed covering the conductive portion 8 and the first interlayer insulating film 14a. A through hole is formed in a portion of the second interlayer insulating film 14b that overlaps the conductive portion 8 in a plane, and a transparent conductive film such as ITO or IZO is formed and patterned so as to cover the inside of the through hole. The pixel electrode 15A and the contact hole CNT4 are formed. The film thickness of the pixel electrode 15A is, for example, approximately 10 nm to 50 nm. The pixel electrode 15A is electrically connected to the upper electrode 16b of the storage capacitor 16 through the contact hole CNT4 and the conductive portion 8. That is, the pixel electrode 15A is electrically connected to the drain electrode 32 of the TFT 30 via the contact hole CNT4, the conductive portion 8, the contact hole CNT2, the second relay layer 6b, and the first relay layer 4. A detailed method for forming the conductive portion 8 will be described later.

  Next, referring to FIG. 9, the contact portion of the pixel electrode 15 will be described more specifically by comparing the conventional example and the example. FIG. 9A is a schematic plan view showing the contact portion of the pixel electrode of the embodiment, and FIG. 9B is a schematic plan view showing the contact portion of the pixel electrode of the conventional example.

As shown in FIG. 9B, the contact portion of the pixel electrode 15B shown in the conventional example is the interlayer insulating film 13 between the fourth layer and the fifth layer and between the fifth layer and the sixth layer. This is due to the contact hole CNT3 having a depth of about 875 nm provided through the interlayer insulating film 14. In consideration of electrical connection, the planar shape of the contact hole CNT3 is, for example, a substantially rectangular shape having a length L1 in the X direction of about 1.3 μm and a length L2 in the Y direction of about 0.5 μm. Therefore, the aspect ratio of the contact hole CNT3 of the conventional example (contact hole depth / maximum diameter of the contact hole; in the case of the contact hole CNT3, the flat area is replaced with the area of the circle, and the circle diameter is calculated to be 0.91 μm. ) Is 875 nm / 910 nm≈0.96.
On the other hand, the contact portion of the pixel electrode 15A of the embodiment is due to a contact hole CNT4 provided on the conductive portion 8, as shown in FIG. The planar shape of the contact hole CNT4 is circular, and its size is, for example, φ0.35 μm. As described above, the contact hole CNT4 is formed by etching the second interlayer insulating film 14b having a film thickness of approximately 75 nm, and the depth after the etching is approximately 100 nm. That is, the aspect ratio of the contact hole CNT4 in the example is 100 nm / 350 nm≈0.29. Therefore, the unevenness on the surface of the pixel electrode in the conventional example due to the contact portion covers a depth of less than 875 nm and 0.65 μm ² , whereas the unevenness on the surface of the pixel electrode in the embodiment has a depth of less than 100 nm. Over a range of 0.1 μm ² . That is, the unevenness on the surface of the pixel electrode is considerably smaller in the example than in the conventional example.

<Method of manufacturing electro-optical device>
Next, a method for manufacturing the liquid crystal device 100 as a method for manufacturing the electro-optical device according to the present embodiment will be described with reference to FIGS. FIG. 10 is a flowchart illustrating a method for manufacturing a liquid crystal device, and FIGS. 11A to 11E and 12F to 12J are schematic cross-sectional views illustrating a method for manufacturing a liquid crystal device. In addition, the manufacturing method of the liquid crystal device 100 in the present embodiment is a manufacturing method of the element substrate 10A constituting the liquid crystal device 100, and the scanning line 3 (first layer) and the TFT 30 (second layer) are formed on the base material 10s. As the method for forming the first relay layer 4 (third layer), the data line 6a, the second relay layer 6b (fourth layer), etc., a known manufacturing method as described above can be used. Hereinafter, a method for manufacturing the storage capacitor 16 and the pixel electrode 15A in the fifth and subsequent layers, which is a feature of the present invention, will be described.

  As shown in FIG. 10, the manufacturing method of the liquid crystal device 100 of this embodiment (the manufacturing method of the element substrate 10A) includes the lower electrode forming step (step S1), the dielectric layer forming step (step S2), and the first A contact hole forming process (step S3), a second conductive film forming process (step S4), a third conductive film forming process (step S5), and a third conductive film patterning process (step S6) are provided. In addition, the second conductive film patterning step (step S7), the first interlayer insulating film forming step (step S8), the planarization processing step (step S9), the second interlayer insulating film forming step (step S10), the second contact A hole forming step (step S11) and a pixel electrode forming step (step S12) are provided.

  In the lower electrode forming step (step S1) in FIG. 10, first, as shown in FIG. 11A, a first conductive film 16ab covering the interlayer insulating film 13 is formed. The first conductive film 16ab is a metal oxide film such as ITO or IZO, and is formed to have translucency and conductivity by a vacuum deposition method, a sputtering method, or the like. The film thickness of the first conductive film 16ab is approximately 140 nm, for example. Then, the lower electrode 16a is formed by patterning so that the portion of the first conductive film 16ab overlapping with the contact hole CNT2 is removed by etching. Then, the process proceeds to step S2.

  In the dielectric layer forming step (step S2) of FIG. 10, as shown in FIG. 11B, a dielectric layer 16c that covers the lower electrode 16a is formed. The dielectric layer 16c is composed of a plurality of layers having different dielectric constants as described above, and the film thickness is formed in the range of 30 nm to 60 nm so as to have translucency. Then, the process proceeds to step S3.

  In the first contact hole forming step (step S3) in FIG. 10, as shown in FIG. 11C, the interlayer insulating film 13 is formed on the portion overlapping the second relay layer 6b and from which the lower electrode 16a has been removed. A through hole 13a penetrating to the second relay layer 6b is formed. Examples of the method for forming the through hole 13a include dry etching using a fluorine-based processing gas. Then, the process proceeds to step S4 and step S5.

  In the second conductive film forming step (step S4) and the third conductive film forming step (step S5) in FIG. 10, as shown in FIG. 11 (d), first, the inside of the through hole 13a is covered, and the dielectric A second conductive film 16bb is formed to cover the layer 16c. The second conductive film 16bb is a metal oxide film such as ITO or IZO, like the first conductive film 16ab, and is formed to have translucency and conductivity by a vacuum evaporation method, a sputtering method, or the like. . The film thickness of the second conductive film 16bb is about 140 nm, for example. Subsequently, a third conductive film 8b that is a precursor of the conductive portion 8 is formed so as to cover the second conductive film 16bb. The third conductive film 8b is formed using a metal or a metal compound by a vacuum deposition method, a sputtering method, or the like. Examples of the metal include Al (aluminum), Ti (titanium), Cr (chromium), Ni (nickel), Cu (copper), Mo (molybdenum), Ta (tantalum), and W (tungsten). Examples of the metal compound include nitrides and silicides of these metals. The third conductive film 8b may include at least one conductive layer using a material selected from these metals or metal compounds. In the present embodiment, the third conductive film 8b is formed using TiN (titanium nitride). The film thickness of the third conductive film 8b is approximately 400 nm, which is equivalent to the first interlayer insulating film 14a to be formed later. Then, the process proceeds to step S6.

  In the third conductive film patterning step (step S6) in FIG. 10, as shown in FIG. 11E, the third conductive film 8b is patterned by photolithography to form the conductive portion 8. As a method of etching the third conductive film 8b, dry etching or wet etching can be used. In particular, since the third conductive film 8b is formed on the second conductive film 16bb made of ITO, IZO, or the like, which is a metal oxide film, the second conductive film 16bb can function as an etching stop film. . As shown in FIG. 9A, the planar shape of the conductive portion 8 is, for example, a substantially square having a side of about 650 nm (0.65 μm). The planar shape of the conductive portion 8 is not limited to a substantially square shape. Then, the process proceeds to step S7 and step S8.

  In the second conductive film patterning step (step S7) and the first interlayer insulating film forming step (step S8) in FIG. 10, as shown in FIG. 12 (f), first, the second conductive film 16bb is patterned by photolithography. Thus, the upper electrode 16b is formed. As an etching method of the second conductive film 16bb, wet etching can be used. At this time, since the conductive portion 8 made of a different material is formed on the second conductive film 16bb, the position of the upper electrode 16b can be accurately patterned with respect to the conductive portion 8. Subsequently, an NSG film 14ab serving as a first interlayer insulating film covering the conductive portion 8 and the upper electrode 16b is formed. As a method for forming the NSG film 14ab, for example, a plasma CVD method can be given. The film thickness of the NSG film 14ab is approximately 600 nm. On the surface of the NSG film 14ab, irregularities due to the conductive portion 8 and the contact hole CNT2 occur. Then, the process proceeds to step S9.

  In the planarization process step (step S9) in FIG. 10, the surface of the NSG film 14ab having the unevenness is subjected to a planarization process, specifically, a CMP process. The CMP process is performed until the conductive portion 8 is exposed on the surface of the NSG film 14ab. As a result, as shown in FIG. 12G, the first interlayer insulating film 14a having the planarized surface while the conductive portion 8 penetrates is formed. The thickness of the first interlayer insulating film 14a on the upper electrode 16b after planarization is, for example, about 100 nm. Then, the process proceeds to step S10.

  In the second interlayer insulating film forming step (step S10) in FIG. 10, as shown in FIG. 12H, a second interlayer insulating film 14b covering the conductive portion 8 and the first interlayer insulating film 14a is formed. The second interlayer insulating film 14b is a BSG film and is formed using, for example, a plasma CVD method. The film thickness of the second interlayer insulating film 14b is thinner than the film thickness of the first interlayer insulating film 14a, for example, approximately 75 nm. Thereby, the interlayer insulating film 14 including the first interlayer insulating film 14a and the second interlayer insulating film 14b is completed. Then, the process proceeds to step S11.

  In the second contact hole forming step (step S11) in FIG. 10, as shown in FIG. 12 (i), the portion of the second interlayer insulating film 14b that planarly overlaps the conductive portion 8 is etched by photolithography. Then, a through hole 14c that penetrates through the second interlayer insulating film 14b and reaches the conductive portion 8 is formed. The size of the through hole 14c is about φ0.35 μm as described above. The substantial depth of the through hole 14c is about 100 nm. Then, the process proceeds to step S12.

  In the pixel electrode formation step (step S12) of FIG. 10, a metal oxide film (fourth conductive film) such as ITO or IZO is formed so as to cover the inside of the through hole 14c and the second interlayer insulating film 14b. Then, the pixel electrode 15A and the contact hole CNT4 are formed by patterning by photolithography. The film thickness of the pixel electrode 15A is approximately 10 nm to 50 nm. As a result, the pixel electrode 15A electrically connected to the upper electrode 16b through the conductive portion 8 and the contact hole CNT4 is completed. The surface unevenness due to the contact hole CNT4 in the pixel electrode 15A falls within a range determined by the depth (100 nm) and size (φ0.35 μm) of the contact hole CNT4. Accordingly, the pixel electrode 15A having a considerably small unevenness on the surface of the pixel electrode as compared with the pixel electrode 15B of the conventional example described above is formed.

According to the first embodiment, the following effects can be obtained.
(1) The pixel electrode 15A in the pixel P of the liquid crystal device 100 is formed on the upper electrode 16b of the storage capacitor 16, and the conductive portion 8 penetrating the first interlayer insulating film 14a and the contact formed on the conductive portion 8. It is electrically connected to the upper electrode 16b through the hole CNT4. The contact hole CNT4 is formed so as to penetrate the second interlayer insulating film 14b, which is thinner than the first interlayer insulating film 14a. Therefore, as compared with the pixel electrode 15B electrically connected to the upper electrode 16b by the contact hole CNT3 penetrating the interlayer insulating film 13 and the interlayer insulating film 14 as in the conventional example, the surface of the pixel electrode caused by the contact portion The unevenness is considerably small. Therefore, the disorder of the alignment of the liquid crystal molecules due to the unevenness of the pixel electrode surface is unlikely to cause display unevenness. That is, it is possible to provide or manufacture the liquid crystal device 100 in which the display state in the pixel P is uniform and has excellent display quality.
Further, disposing the conductive portion 8 made of a different material between the upper electrode 16b made of the same metal oxide and the pixel electrode 15A means that the pixel electrode 15A is patterned by patterning the transparent conductive film (fourth conductive film). When forming the upper electrode 16b, the upper electrode 16b can be prevented from being etched.
(2) The second conductive film 16bb is formed using a metal oxide such as ITO or IZO, and the third conductive film 8b formed on the second conductive film 16bb is formed using a metal or a metal compound. When the conductive portion 8 is formed by patterning the third conductive film 8b, the second conductive film 16bb functions as an etching stop film. Therefore, the conductive portion 8 can be formed with high accuracy. In addition, since the second conductive film 16bb and the third conductive film 8b are formed using different materials, the second conductive film 16bb is formed after the third conductive film 8b is patterned to form the conductive portion 8. By patterning to form the upper electrode 16b, the upper electrode 16b can be accurately formed with respect to the conductive portion 8.
(3) The first interlayer insulating film 14a is made of an NSG film, and the second interlayer insulating film 14b is made of a BSG film. Since the BSG film has a moisture absorption performance superior to that of the NSG film, the insulation between the wiring layers of the element substrate 10A is unlikely to deteriorate even when moisture enters. That is, the liquid crystal device 100 having high reliability quality can be manufactured or provided.
(4) Since the method of removing the portion of the NSG film 14ab that overlaps the conductive portion 8 in plan is a CMP process for polishing the NSG film 14ab, the pixel electrode 15A having a flatter surface is realized. Can do.
(5) The contact hole CNT4 provided in the second interlayer insulating film 14b for electrical connection between the pixel electrode 15A and the upper electrode 16b has a smaller aspect ratio than the contact hole CNT3 of the conventional example. Therefore, electrical connection can be ensured even if the pixel electrode 15A of the embodiment (10 nm to 50 nm) is made thinner than the pixel electrode 15B of the conventional example (140 nm). That is, the pixel electrode 15A can be formed with less material than the conventional example, and a brighter transmissive liquid crystal device 100 can be realized.

(Second Embodiment)
<Electronic equipment>
Next, a projection display device as an electronic apparatus to which the liquid crystal device 100 as an electro-optical device according to this embodiment is applied will be described with reference to FIG. FIG. 13 is a schematic diagram showing the configuration of the projection display device.

  As shown in FIG. 13, a projection display apparatus 1000 as an electronic apparatus according to the present embodiment includes a polarization illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. And. In addition, three reflection mirrors 1106, 1107, 1108 and five relay lenses 1201, 1202, 1203, 1204, 1205 are provided. Further, it includes transmissive liquid crystal light valves 1210, 1220, and 1230 as three light modulation means, a cross dichroic prism 1206 as a light combining element, and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected onto the screen 1300 by the projection lens 1207, which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 (see FIG. 1) of the first embodiment is applied. A pair of polarizing elements arranged in crossed Nicols are arranged with a gap between the colored light incident side and the emitting side of the liquid crystal device 100. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection display apparatus 1000, since the liquid crystal device 100 of the first embodiment is used as the liquid crystal light valves 1210, 1220, and 1230, the unevenness of the surface of the pixel electrode caused by the contact portion is considerable. It is getting smaller. Therefore, the disorder of the alignment of the liquid crystal molecules caused by the unevenness on the surface of the pixel electrode is unlikely to cause display unevenness. That is, it is possible to provide the projection display apparatus 1000 having a uniform display state in the pixels P and excellent display quality.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. The manufacturing method of the electro-optical device and the electronic apparatus to which the electro-optical device is applied are also included in the technical scope of the present invention. Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) The method of exposing the conductive portion 8 on the surface of the first interlayer insulating film 14a is to perform a planarization process on the NSG film 14ab covering the conductive portion 8 and expose the conductive portion 8 on the surface of the NSG film 14ab. The method is not limited. For example, the conductive portion 8 may be formed by forming a through hole in the first interlayer insulating film 14a and filling the through hole with a metal or a metal compound. Since the NSG film 14ab is planarized for the purpose of further flattening the surface of the pixel electrode 15, the manufacturing method of the first embodiment includes an extra step such as forming the through hole. This is preferable in that

  (Modification 2) The interlayer insulating film 14 between the upper electrode 16b and the pixel electrode 15 is not limited to the configuration including the first interlayer insulating film 14a and the second interlayer insulating film 14b. In other words, the interlayer insulating film 14 may have a single layer structure made of an NSG film.

  (Modification 3) The structure in which the pixel electrode 15 and the storage capacitor 16 of the present invention are electrically connected is not limited to being applied to the transmissive liquid crystal device 100. The pixel electrode 15 can also be applied to a reflective liquid crystal device in which a metal film such as Al (aluminum) having light reflectivity or a structure in which a metal film and a transparent conductive film are stacked is employed. Thereby, the unevenness of the surface of the pixel electrode caused by the contact portion is reduced, and a reflective liquid crystal device having excellent display quality can be provided or manufactured.

  (Modification 4) The liquid crystal device 100 of the first embodiment may be configured to include a color filter corresponding to each of the plurality of pixels P in either the element substrate 10 or the counter substrate 20.

  (Modification 5) The electronic apparatus to which the liquid crystal device 100 of the first embodiment is applied is not limited to the projection display device 1000 of the second embodiment. For example, the counter substrate 20 of the liquid crystal device 100 may include color filters corresponding to at least red (R), green (G), and blue (B), and the projection display device may have a single plate configuration. Also, for example, a projection type HUD (head-up display), HMD (head-mounted display), electronic book, personal computer, digital still camera, liquid crystal television, viewfinder type or monitor direct view type video recorder, car navigation system, The liquid crystal device 100 can be suitably used as a display unit of an information terminal device such as an electronic notebook or POS.

  DESCRIPTION OF SYMBOLS 8 ... Conductive part, 8b ... 3rd conductive film, 10 ... Element board | substrate, 10s ... Base material as a board | substrate, 14 ... Interlayer insulation film, 14a ... 1st interlayer insulation film, 14b ... 2nd interlayer insulation film, 14c ... Through Hole 15, pixel electrode 16, storage capacitor, 16 a, lower electrode, 16 ab, first conductive film, 16 b, upper electrode, 16 bb, second conductive film, 16 c, dielectric layer, 30, TFT (thin film transistor) , 100... Liquid crystal device as an electro-optical device, 1000...

Claims (10)

A pixel electrode;
A transistor provided corresponding to the pixel electrode;
A storage capacitor configured to include an upper electrode and a lower electrode, and a dielectric layer provided between the upper electrode and the lower electrode;
An interlayer insulating film provided between the upper electrode and the pixel electrode;
A conductive portion provided on the upper electrode and penetrating the interlayer insulating film,
The electro-optical device, wherein the pixel electrode is electrically connected to the upper electrode through the conductive portion. Each of the upper electrode and the lower electrode is made of a metal oxide, has translucency and conductivity,
The electro-optical device according to claim 1, wherein the conductive portion includes at least one conductive layer made of a metal or a metal compound. The interlayer insulating film is provided between the first interlayer insulating film, and between the first interlayer insulating film and the pixel electrode, and is made of a material different from that of the first interlayer insulating film and having a thickness greater than that of the first interlayer insulating film. And a thin second interlayer insulating film,
The conductive portion penetrates the first interlayer insulating film,
The electro-optical device according to claim 1, wherein a contact hole is provided in a portion of the second interlayer insulating film that overlaps the conductive portion in a plan view.   4. The electro-optical device according to claim 3, wherein the first interlayer insulating film is made of an NSG (Non doped Silicate Glass) film, and the second interlayer insulating film is made of a BSG (Boron doped Silicate Glass) film. A pixel electrode; a transistor provided corresponding to the pixel electrode; an upper electrode and a lower electrode; and a dielectric layer provided between the upper electrode and the lower electrode. A storage capacitor, and a manufacturing method of an electro-optical device comprising:
Forming the lower electrode by forming and patterning a first conductive film on the substrate between the transistor and the pixel electrode; and
Forming the dielectric layer covering the lower electrode;
Forming a second conductive film covering the dielectric layer;
Forming a conductive film on the second conductive film by forming and patterning a third conductive film covering the second conductive film; and
Patterning the second conductive film to form the upper electrode;
Forming an interlayer insulating film covering the upper electrode and the conductive portion;
Removing the portion of the interlayer insulating film that overlaps the conductive portion in a plane;
Forming a pixel electrode by forming and patterning a fourth conductive film covering the interlayer insulating film, and a method for manufacturing the electro-optical device. The first conductive film and the second conductive film are formed using a metal oxide so that each of them has translucency and conductivity.
6. The method of manufacturing an electro-optical device according to claim 5, wherein the third conductive film is formed using a metal or a metal compound so as to include at least one conductive layer. The step of forming the interlayer insulating film includes:
Forming a first interlayer insulating film covering the upper electrode and the conductive portion;
Removing the portion of the first interlayer insulating film that overlaps the conductive portion in a plane;
Using a material different from that of the first interlayer insulating film, and forming a second interlayer insulating film covering the first interlayer insulating film with a film thickness thinner than the first interlayer insulating film;
Forming a through hole penetrating through the portion of the second interlayer insulating film that overlaps the conductive portion in plan view,
7. The method of manufacturing an electro-optical device according to claim 5, wherein the step of forming the pixel electrode forms the fourth conductive film so as to cover the through hole.   The step of removing the portion of the interlayer insulating film or the portion of the first interlayer insulating film that overlaps the conductive portion in a planar manner is performed by planarizing the surface of the interlayer insulating film or the surface of the first interlayer insulating film. The method of manufacturing an electro-optical device according to claim 5, wherein the method is a step of exposing the conductive portion.   An electronic apparatus comprising the electro-optical device according to claim 1.   An electronic apparatus comprising the electro-optical device manufactured using the method for manufacturing an electro-optical device according to claim 5.

Images