JP2012044134A - Method of manufacturing built-in circuit board - Google Patents

Method of manufacturing built-in circuit board Download PDF

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JP2012044134A
JP2012044134A JP2010274451A JP2010274451A JP2012044134A JP 2012044134 A JP2012044134 A JP 2012044134A JP 2010274451 A JP2010274451 A JP 2010274451A JP 2010274451 A JP2010274451 A JP 2010274451A JP 2012044134 A JP2012044134 A JP 2012044134A
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circuit board
external electrode
electrode terminal
forming
film
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JP5265650B2 (en
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Sun-Un Yi
イ・スン・ウン
I Na Sin
シン・イー・ナ
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a built-in circuit board.SOLUTION: A method of manufacturing a built-in circuit board includes steps of: preparing an electric element having an external electrode terminal; forming a protective film to cover the external electrode terminal so as not to expose the external electrode terminal; preparing a circuit board having an upper face and a lower face and a chip mounting cavity whose upper and lower parts are opened; adhering a mold release film to the upper face of the circuit board so that the opened upper face of the chip mounting cavity can be closed; positioning the electric element in the chip mounting cavity so that the protection film can be adhered to the mold release film; filling a remaining space of the chip mounting cavity through the opened lower part of the chip mounting cavity and forming an insulating film which covers the lower face of the circuit board; separating the mold release film from the circuit board; removing the protection film so that the external electrode terminal can be exposed; and forming a metal circuit structure which is electrically connected to the external electrode terminal on the circuit board.

Description

本発明は、埋め込み回路基板の製造方法に関するもので、より詳しくは、基板の製造過程で電気素子と回路パターンとの電気的な接続不良を防止できる埋め込み回路基板の製造方法に関するものである。   The present invention relates to a method for manufacturing an embedded circuit board, and more particularly to a method for manufacturing an embedded circuit board that can prevent electrical connection failure between an electric element and a circuit pattern in the process of manufacturing the board.

半導体パッケージ技術は、製造された半導体集積回路チップ（ＩＣ）を外部環境から保護して、該半導体集積回路チップを外部電子装置に装着させるために提供される。通常、半導体パッケージは少なくとも１つの回路基板及び該回路基板に備わる集積回路チップを含むことができる。このような回路基板のうち埋め込み印刷回路基板（Ｅｍｂｅｄｄｅｄ Ｐｒｉｎｔｅｄ Ｃｉｒｃｕｉｔ Ｂｏａｒｄ：Ｅｍｂｅｄｄｅｄ ＰＣＢ）は半導体パッケージの集積度を上げるために、回路基板内に電気素子を組み込んだ構造を有する。   Semiconductor package technology is provided for protecting a manufactured semiconductor integrated circuit chip (IC) from the external environment and mounting the semiconductor integrated circuit chip on an external electronic device. In general, a semiconductor package can include at least one circuit board and an integrated circuit chip provided on the circuit board. Among such circuit boards, an embedded printed circuit board (Embedded PCB) has a structure in which electric elements are incorporated in the circuit board in order to increase the degree of integration of the semiconductor package.

前述のような埋め込み回路基板は、能動素子及び受動素子のような電気素子を準備して該回路基板のキャビティ内に配設し、所定の絶縁材で該キャビティの余り空きを満たした後、該電気素子の電極端子と該回路基板の回路パターンとを電気的に接続する工程を行って製造されている。しかし、絶縁材で該キャビティの空きを満たす過程において、該絶縁材のうちの一部が電気素子の電極端子を覆うという現象が生じる。この場合、該電気素子の外部電極端子と該回路基板の回路パターンとを電気的に接続させる後続工程で、該電極端子を覆う絶縁材料によって該電気素子と該回路パターンとの間の電気的接続に不良が発生するという不都合がある。   The embedded circuit board as described above is prepared by arranging an electric element such as an active element and a passive element in a cavity of the circuit board, filling a remaining space of the cavity with a predetermined insulating material, It is manufactured by performing a step of electrically connecting the electrode terminals of the electric element and the circuit pattern of the circuit board. However, in the process of filling the cavity with the insulating material, a phenomenon occurs in which a part of the insulating material covers the electrode terminal of the electric element. In this case, in the subsequent step of electrically connecting the external electrode terminal of the electrical element and the circuit pattern of the circuit board, electrical connection between the electrical element and the circuit pattern by an insulating material covering the electrode terminal There is an inconvenience that a defect occurs.

本発明は上記の問題点に鑑みて成されたものであって、製造工程効率を向上させた埋め込み回路基板の製造方法を提供することに、その目的がある。   The present invention has been made in view of the above problems, and has an object to provide a method of manufacturing an embedded circuit board with improved manufacturing process efficiency.

また、製造過程において電気素子と回路パターンとの電気的な接続信頼性が低下するのを防止する埋め込み回路基板の製造方法を提供することに、その目的がある。 It is another object of the present invention to provide a method for manufacturing an embedded circuit board that prevents a decrease in electrical connection reliability between an electrical element and a circuit pattern during the manufacturing process.

韓国特許第１０−０７８２９３５号公報Korean Patent No. 10-0782935 韓国特許第１０−０８３６６５１号公報Korean Patent No. 10-083651

〔課題を解決するための手段〕
上記目的を解決するために、本発明の好適な実施の形態による埋め込み回路基板の製造方法は、外部電極端子を有する電気素子を準備するステップと、前記外部電極端子が露出されないように、前記外部電極端子を覆う保護膜を形成するステップと、上面及び下面を有し、上下部が開けられたチップ実装キャビティを有する回路基板を準備するステップと、前記チップ実装キャビティの開けられた上部が閉じられるように、前記回路基板の前記上面に離型フィルムを付着するステップと、前記保護膜が前記離型フィルムに密着されるように、前記電気素子を前記チップ実装キャビティ内に位置させるステップと、前記チップ実装キャビティの開けられた下部を通じて、前記チップ実装キャビティの余り空きを満たすと共に前記回路基板の前記下面を覆う絶縁膜を形成するステップと、前記回路基板から前記離型フィルムを分離するステップと、前記外部電極端子が露出するように前記保護膜を除去するステップと、前記回路基板に前記外部電極端子と電気的に接続する金属回路構造物を形成するステップとを含むことができる。 [Means for solving the problems]
In order to solve the above-described object, a method of manufacturing an embedded circuit board according to a preferred embodiment of the present invention includes a step of preparing an electric element having an external electrode terminal, and the external electrode terminal is not exposed. A step of forming a protective film covering the electrode terminals; a step of preparing a circuit board having a chip mounting cavity having an upper surface and a lower surface and having upper and lower portions opened; and an upper portion where the chip mounting cavity is opened Attaching a release film to the upper surface of the circuit board; positioning the electrical element in the chip mounting cavity so that the protective film is in close contact with the release film; Through the opened bottom of the chip mounting cavity, the remainder of the chip mounting cavity is filled and the circuit board Forming an insulating film covering a surface; separating the release film from the circuit board; removing the protective film so that the external electrode terminals are exposed; and the external electrode on the circuit board. Forming a metal circuit structure that is electrically connected to the terminal.

本発明の実施形態によれば、前記保護膜を形成するステップは、前記外部電極端子に絶縁テープを付着するステップを含むことができる。   According to the embodiment of the present invention, forming the protective film may include attaching an insulating tape to the external electrode terminal.

本発明の実施形態によれば、前記保護膜を形成するステップは、前記外部電極端子に絶縁膜を塗布するステップを含むことができる。   According to the embodiment of the present invention, forming the protective film may include applying an insulating film to the external electrode terminal.

本発明の実施形態によれば、前記保護膜を除去するステップは、前記回路基板から前記離型フィルムを分離するステップで行なわれることができる。   According to the embodiment of the present invention, the step of removing the protective film may be performed by separating the release film from the circuit board.

本発明の実施形態によれば、前記保護膜と前記離型フィルムとの間の接着力は、前記外部電極端子と前記保護膜との間の接着力に比べて大きくなることができる。   According to the embodiment of the present invention, the adhesive force between the protective film and the release film can be larger than the adhesive force between the external electrode terminal and the protective film.

本発明の実施形態によれば、前記金属回路構造物を形成するステップは、前記回路基板を貫通する導電性ビアを形成するステップと、一部が前記外部電極端子に接続し、他部が前記回路基板の前記導電性ビアに接続する外部回路パターンを形成するステップとを含むことができる。   According to an embodiment of the present invention, the step of forming the metal circuit structure includes the step of forming a conductive via that penetrates the circuit board, a part of which is connected to the external electrode terminal, Forming an external circuit pattern connected to the conductive via of the circuit board.

本発明の実施形態によれば、前記電気素子を準備するステップは、一面に前記外部電極端子が備わる半導体集積回路チップ（ＩＣ）を準備するステップを含むことができる。   According to the embodiment of the present invention, the step of preparing the electric element may include a step of preparing a semiconductor integrated circuit chip (IC) having the external electrode terminal on one surface.

本発明の実施形態によれば、前記電気素子を準備するステップは、両側に前記外部電極端子が備わる積層セラミックキャパシタ（Ｍｕｌｔｉｌａｙｅｒ Ｃｅｒａｍｉｃ Ｃａｐａｃｉｔｏｒ：ＭＬＣＣ）を準備するステップを含み、前記保護膜を形成するステップは、前記離型フィルムと接触される前記外部電極端子の部分だけ選択的に露出されないようにすることができる。   According to an embodiment of the present invention, the step of preparing the electric element includes a step of preparing a multilayer ceramic capacitor (MLCC) having the external electrode terminals on both sides, and forming the protective film In this case, only the portion of the external electrode terminal that is in contact with the release film is not selectively exposed.

本発明の実施形態によれば、前記絶縁膜を形成するステップは、前記回路基板にプリプレグ膜（ｐｒｅｐｒｅｇ １ａｙｅｒ）を形成するステップを含み、前記回路基板を製造する方法は、前記プリプレグ膜に銅薄膜を積層するステップをさらに含むことができる。
〔発明の効果〕 According to an embodiment of the present invention, the step of forming the insulating film includes the step of forming a prepreg film on the circuit board, and the method of manufacturing the circuit board includes a copper thin film on the prepreg film. Can be further included.
〔The invention's effect〕

本発明の実施形態による埋め込み回路基板の製造方法によれば、電気素子の外部電極端子に保護膜を形成し、該電気素子を回路基板のチップ実装キャビティに組み込ませ、前記チップ実装キャビティ内部を絶縁膜で満たし、該保護膜を除去して該外部電極端子を選択的に露出させた後、該回路基板に前記外部電極端子と接続する回路パターンを形成することができる。該絶縁膜の形成に際に、該絶縁膜が外部電極端子を覆うように形成しても該保護膜を除去することによって該外部電極端子を覆う絶縁膜を除去することができる。これにより、外部電極端子が絶縁膜により覆われて該外部電極端子に接続する回路パターンを形成する後続工程で前記回路パターンが前記外部電極端子に効果良く接続されない現象を防止することによって、前記電気素子と前記回路パターンとの電気的な接続信頼性が低下するのを防止ことができる。   According to the method of manufacturing the embedded circuit board according to the embodiment of the present invention, the protective film is formed on the external electrode terminal of the electric element, the electric element is incorporated into the chip mounting cavity of the circuit board, and the inside of the chip mounting cavity is insulated. After filling with a film and removing the protective film to selectively expose the external electrode terminals, a circuit pattern connected to the external electrode terminals can be formed on the circuit board. Even when the insulating film is formed so as to cover the external electrode terminal when the insulating film is formed, the insulating film covering the external electrode terminal can be removed by removing the protective film. This prevents the phenomenon that the circuit pattern is not effectively connected to the external electrode terminal in a subsequent process in which the external electrode terminal is covered with an insulating film to form a circuit pattern connected to the external electrode terminal. It is possible to prevent a decrease in electrical connection reliability between the element and the circuit pattern.

本発明の実施形態による埋め込み回路基板の製造方法は、回路基板に電気素子を実装する前に前記電気素子の外部電極端子に簡単に保護膜を形成した後、埋め込み製造工程を行うことによって、前記電気素子とこれに接続する回路パターンとの電気的な接続信頼性が低下するのを防止できるので、埋め込み回路基板の製造工程効率を向上させることができる。   According to an embodiment of the present invention, there is provided a method of manufacturing an embedded circuit board by performing an embedded manufacturing process after forming a protective film on an external electrode terminal of the electric element before mounting the electric element on the circuit board. Since the electrical connection reliability between the electric element and the circuit pattern connected to the electric element can be prevented from being lowered, the manufacturing process efficiency of the embedded circuit board can be improved.

本発明の実施形態による埋め込み回路基板の製造方法を示す順序図である。FIG. 6 is a flowchart illustrating a method for manufacturing an embedded circuit board according to an embodiment of the present invention. 本発明の実施形態による埋め込み回路基板の製造過程を説明するための図面である。6 is a view for explaining a manufacturing process of an embedded circuit board according to an embodiment of the present invention; 本発明の実施形態による埋め込み回路基板の製造過程を説明するための図面である。6 is a view for explaining a manufacturing process of an embedded circuit board according to an embodiment of the present invention; 同じく、埋め込み回路基板の製造過程を説明するための図面である。Similarly, it is a drawing for explaining a manufacturing process of an embedded circuit board. 同じく、埋め込み回路基板の製造過程を説明するための図面である。Similarly, it is a drawing for explaining a manufacturing process of an embedded circuit board. 同じく、埋め込み回路基板の製造過程を説明するための図面である。Similarly, it is a drawing for explaining a manufacturing process of an embedded circuit board. 同じく、埋め込み回路基板の製造過程を説明するための図面である。Similarly, it is a drawing for explaining a manufacturing process of an embedded circuit board.

以下、本発明の好適な実施の形態は図面を参考にして詳細に説明する。次に示される各実施の形態は当業者にとって本発明の思想が十分に伝達されることができるようにするために例として挙げられるものである。従って、本発明は以下示している各実施の形態に限定されることなく他の形態で具体化されることができる。そして、図面において、装置の大きさ及び厚さなどは便宜上誇張して表現されることができる。明細書全体に渡って同一の参照符号は同一の構成要素を示している。   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. Each embodiment shown below is given as an example so that those skilled in the art can sufficiently communicate the idea of the present invention. Therefore, the present invention is not limited to the embodiments described below, but can be embodied in other forms. In the drawings, the size and thickness of the device can be exaggerated for convenience. Like reference numerals refer to like elements throughout the specification.

本明細書で使われた用語は、実施形態を説明するためのものであって、本発明を制限しようとするものではない。本明細書において、単数形は文句で特別に言及しない限り複数形も含む。明細書で使われる「含む」とは、言及された構成要素、ステップと、動作及び／又は素子は、一つ以上の他の構成要素、ステップと、動作及び／又は素子の存在または追加を排除しないことに理解されたい。   The terminology used herein is for the purpose of describing embodiments and is not intended to limit the invention. In this specification, the singular includes the plural unless specifically stated otherwise. As used herein, “includes” a stated component, step, operation, and / or element excludes the presence or addition of one or more other component, step, operation, and / or element. Please understand that you do not.

以下、添付図面を参照して本発明の実施形態による埋め込み回路基板の製造方法について詳細に説明する。   Hereinafter, a method for manufacturing an embedded circuit board according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

図１は、本発明の実施形態による埋め込み回路基板の製造方法を示す順序図で、図２〜図６は、本発明の実施形態による埋め込み回路基板の製造過程を説明するための図面である。   FIG. 1 is a flow chart illustrating a method of manufacturing an embedded circuit board according to an embodiment of the present invention, and FIGS. 2 to 6 are diagrams for explaining a process of manufacturing the embedded circuit board according to an embodiment of the present invention.

図１、及び、図２ａおよび図２ｂを参照して、外部電極端子１１２を有する電気素子１１０を準備する（Ｓ１１０）。一例として、図２ａに示すように、該電気素子１１０を準備するステップは、一面に前記外部電極端子１１２が備わる半導体集積回路チップ（ＩＣ）を準備するステップを含むことができる。該外部電極端子１１２は前記半導体集積回路チップの一面に露出されるように備わるプラス端子及びマイナス端子であってもよい。   Referring to FIG. 1 and FIGS. 2a and 2b, an electric element 110 having an external electrode terminal 112 is prepared (S110). As an example, as shown in FIG. 2a, the step of preparing the electric element 110 may include a step of preparing a semiconductor integrated circuit chip (IC) having the external electrode terminal 112 on one surface. The external electrode terminal 112 may be a plus terminal and a minus terminal provided so as to be exposed on one surface of the semiconductor integrated circuit chip.

続いて、前記外部電極端子に保護膜１２０を形成する（Ｓ１２０）。該保護膜１２０を形成するステップは、多様な方法で行われることができる。一例として、前記保護膜１２０を形成するステップは、前記外部電極端子１１２に絶縁テープを付着させて行われることができる。他の例として、前記保護膜１２０を形成するステップは、前記外部電極端子１１２に絶縁膜を塗布して行われることができる。前記絶縁膜の塗布は、スピンコーティング法で行われてもよい。   Subsequently, a protective film 120 is formed on the external electrode terminal (S120). The step of forming the passivation layer 120 can be performed by various methods. As an example, the step of forming the protective layer 120 may be performed by attaching an insulating tape to the external electrode terminal 112. As another example, the step of forming the protective layer 120 may be performed by applying an insulating layer to the external electrode terminal 112. The insulating film may be applied by a spin coating method.

本実施形態では、電気素子が半導体集積回路チップの場合を例に挙げて説明したが、多様な種類の能動素子及び受動素子のうちの少なくともいずれか一つであってもよい。例えば、本発明の他の実施形態では、図２ｂに示すように、電気素子１１０ａを準備するステップは、両側に前記外部電極端子１１２ａが備わる積層セラミックキャパシタ（Ｍｕｌｔｉｌａｙｅｒ Ｃｅｒａｍｉｃ Ｃａｐａｃｉｔｏｒ：ＭＬＣＣ）を準備するステップを含むことができる。この場合、前記外部電極端子１１２ａは前記電気素子１１０ａの両側に備わる構造を有することができ、前記保護膜１２０は今後離型フィルム１４０と接触される前記外部電極端子１１２ａの接触領域１１２ａ’に選択的に形成されることができる。   In the present embodiment, the case where the electric element is a semiconductor integrated circuit chip has been described as an example. However, the electric element may be at least one of various types of active elements and passive elements. For example, in another embodiment of the present invention, as shown in FIG. 2b, the step of preparing the electrical element 110a includes the step of preparing a multilayer ceramic capacitor (MLCC) having the external electrode terminals 112a on both sides. Can be included. In this case, the external electrode terminal 112a may have a structure provided on both sides of the electric element 110a, and the protective film 120 may be selected as a contact region 112a ′ of the external electrode terminal 112a to be in contact with the release film 140 in the future. Can be formed automatically.

続いて、図１及び図３を参照して、チップ実装キャビティ１３６を有する回路基板１３０を準備する（Ｓ１３０）。例えば、前記回路基板１３０を準備するステップは、上面１３２及び下面１３４を有するベース基板を準備するステップと、該ベース基板を上下に貫通する貫通ホールを形成するステップとを含むことができる。これにより、開けられた上部１３６ａ及び下部１３６ｂを有するチップ実装キャビティ１３６が形成された前記回路基板１３０が製造されることができる。ここで、前記チップ実装キャビティ１３６は前記電気素子１１０に比べて、その幅が多少大きいように形成されることができる。これは、今後前記電気素子１１０を前記チップ実装キャビティ１３６内に容易に実装するためである。   Subsequently, referring to FIG. 1 and FIG. 3, a circuit board 130 having a chip mounting cavity 136 is prepared (S130). For example, the step of preparing the circuit board 130 may include a step of preparing a base substrate having an upper surface 132 and a lower surface 134, and a step of forming a through hole that penetrates the base substrate vertically. Accordingly, the circuit board 130 in which the chip mounting cavity 136 having the opened upper portion 136a and the lower portion 136b is formed can be manufactured. Here, the chip mounting cavity 136 may be formed to have a slightly larger width than the electric element 110. This is to easily mount the electric element 110 in the chip mounting cavity 136 in the future.

続いて、前記回路基板１３０に離型フィルム１４０を付着する（Ｓ１４０）。前記離型フィルム１４０は前記チップ実装キャビティ１３６の開けられた上部１３６ａが閉じられるように、前記回路基板１３０の前記上面１３２に付着されることができる。   Subsequently, a release film 140 is attached to the circuit board 130 (S140). The release film 140 may be attached to the upper surface 132 of the circuit board 130 such that the upper part 136a of the chip mounting cavity 136 is closed.

続いて、前記チップ実装キャビティ１３６内に前記電気素子１１０を位置させる（Ｓ１５０）。前記電気素子１１０を位置させるステップは、前記外部電極端子１１２に付着された保護膜１２０が前記離型フィルム１４０に密着されるように、前記電気素子１１０を前記チップ実装キャビティ１３６内に実装させて行われることができる。   Subsequently, the electric element 110 is positioned in the chip mounting cavity 136 (S150). The step of positioning the electric element 110 includes mounting the electric element 110 in the chip mounting cavity 136 such that the protective film 120 attached to the external electrode terminal 112 is in close contact with the release film 140. Can be done.

図１、図３及び図４を参照して、前記回路基板１３０に絶縁膜１５２を形成する（Ｓ１６０）。一例として、前記絶縁膜１５２を形成するステップは、前記回路基板１３０の下面１３４に対向するフィルム形状の絶縁材１５０を準備するステップと、前記絶縁材１５０を前記回路基板１３０に押圧するステップとを含むことができる。前記絶縁材１５０としては、所定の絶縁材料から成る絶縁フィルムが用いられることができる。該絶縁材１５０の一部は、前記電気素子１１０により満たされない前記チップ実装キャビティ１３６の余り空きに充填されることができる。これにより、前記回路基板１３０には前記チップ実装キャビティ１３６の余り空きを満たすと共に、前記回路基板１３０の前記下面１３４を均一に覆う絶縁膜１５２が形成されることができる。   Referring to FIGS. 1, 3 and 4, an insulating film 152 is formed on the circuit board 130 (S160). As an example, the step of forming the insulating film 152 includes a step of preparing a film-shaped insulating material 150 facing the lower surface 134 of the circuit board 130 and a step of pressing the insulating material 150 against the circuit board 130. Can be included. As the insulating material 150, an insulating film made of a predetermined insulating material can be used. A part of the insulating material 150 may be filled in the chip mounting cavity 136 that is not filled with the electric element 110. Accordingly, an insulating film 152 may be formed on the circuit board 130 so as to fill the remaining space of the chip mounting cavity 136 and uniformly cover the lower surface 134 of the circuit board 130.

他の例として、前記絶縁膜１５２を形成するステップは、前記回路基板１３０の下面１３４に対してプリプレグ膜（ｐｒｅｐｒｅｇ １ａｙｅｒ）を形成するステップを含むことができる。該プリプレグ膜は、前記チップ実装キャビティ１３６の余り空きを充填すると共に、前記回路基板１３０の前記下面１３４を均一に覆うことができる。   As another example, forming the insulating layer 152 may include forming a prepreg layer on the lower surface 134 of the circuit board 130. The prepreg film can fill the empty space of the chip mounting cavity 136 and can uniformly cover the lower surface 134 of the circuit board 130.

一方、前記絶縁膜１５２を形成する過程において、前記絶縁膜１５２に金属薄膜を積層するステップが行われることができる。例えば、前記絶縁膜１５２が樹脂膜（ｒｅｓｉｎ ｌａｙｅｒ）またはプリプレグ膜である場合、前記絶縁膜１５２を形成する過程で、前記樹脂膜または前記プリプレグ膜上に金属薄膜を積層するステップが付加されることができる。前記金属薄膜としては、銅（Ｃｕ）から成る銅薄膜であってもよい。このような銅薄膜は、前記絶縁膜１５２を前記回路基板１３０に形成する前に、前記絶縁膜１５２上に予め形成されることができる。この場合、フィルム形態の前記絶縁膜１５２上に銅薄膜を積層した状態で、前記絶縁膜１５２を前記回路基板１３０に付着することによって、前記回路基板１３０上に所定の金属回路パターンを形成することができる。   Meanwhile, in the process of forming the insulating film 152, a step of laminating a metal thin film on the insulating film 152 may be performed. For example, when the insulating film 152 is a resin layer or a prepreg film, a step of laminating a metal thin film on the resin film or the prepreg film is added in the process of forming the insulating film 152. Can do. The metal thin film may be a copper thin film made of copper (Cu). Such a copper thin film may be formed in advance on the insulating film 152 before the insulating film 152 is formed on the circuit board 130. In this case, a predetermined metal circuit pattern is formed on the circuit board 130 by attaching the insulating film 152 to the circuit board 130 in a state where a copper thin film is laminated on the insulating film 152 in a film form. Can do.

続いて、図１及び図５を参照して、回路基板１３０から離型フィルム１４０を除去する（Ｓ１７０）。一例として、前記離型フィルム１４０を除去するステップは、電気素子１１０の外部電極端子１１２を覆う保護膜１２０が除去されるように、前記回路基板１３０から前記離型フィルム１４０を分離して行われることができる。このために、前記保護膜１２０と前記外部電極端子１１２との間の接着力に比べて、前記離型フィルム１４０と前記保護膜１２０との間の接着力がより大きくなるように、前記離型フィルム１４０の接着力を調節することが望ましい。   Subsequently, referring to FIGS. 1 and 5, the release film 140 is removed from the circuit board 130 (S170). As an example, the step of removing the release film 140 is performed by separating the release film 140 from the circuit board 130 such that the protective film 120 covering the external electrode terminal 112 of the electric element 110 is removed. be able to. Therefore, the mold release is performed so that the adhesive force between the release film 140 and the protective film 120 is larger than the adhesive force between the protective film 120 and the external electrode terminal 112. It is desirable to adjust the adhesive strength of the film 140.

他の例として、前記離型フィルム１４０を除去するステップは、前記保護膜１２０が除去されない条件で、前記回路基板１３０から分離されることができる。この場合、前記保護膜１２０の除去のための別途のエッチング工程が付加されることができる。該エッチング工程としては、前記保護膜１２０に対してエッチング選択性を有する湿式エッチング工程、レーザー加工工程などが用いられることができる。   As another example, the step of removing the release film 140 may be separated from the circuit board 130 under a condition that the protective film 120 is not removed. In this case, a separate etching process for removing the protective layer 120 may be added. As the etching process, a wet etching process having etching selectivity with respect to the protective film 120, a laser processing process, or the like can be used.

前述の方法を行って、前記電気素子１１０の前記外部電極端子１１２が選択的に露出されることができる。   By performing the above-described method, the external electrode terminal 112 of the electric element 110 may be selectively exposed.

続いて、図１及び図６を参照して、前記回路基板１３０に金属回路構造物１６０を形成する（Ｓ１８０）。該金属回路構造物１６０を形成するステップは、前記回路基板１３０にビアホール１３８を形成するステップと、前記回路基板１３０の上面１３２、下面１３４及び前記ビアホール１３８に対してメッキ膜を形成するステップと、前記メッキ膜の一部を除去するステップとを順に行うことができる。これにより、前記回路基板１３０には、前記ビアホール１３８を満たす導電性ビア１６２と、電気素子１１０の外部電極端子１１２及び前記導電性ビア１６２に電気的に接続される回路パターン１６４とが形成されることができる。   Subsequently, referring to FIGS. 1 and 6, a metal circuit structure 160 is formed on the circuit board 130 (S180). The step of forming the metal circuit structure 160 includes forming a via hole 138 in the circuit board 130, forming a plating film on the upper surface 132, the lower surface 134 and the via hole 138 of the circuit board 130; And removing the part of the plating film in sequence. As a result, a conductive via 162 that fills the via hole 138 and a circuit pattern 164 that is electrically connected to the external electrode terminal 112 of the electric element 110 and the conductive via 162 are formed on the circuit board 130. be able to.

前述のように、本発明の実施形態による埋め込み回路基板の製造方法は、電気素子１１０の外部電極端子１１２に保護膜１２０を形成し、前記電気素子１１０を前記回路基板１３０のチップ実装キャビティ１３６に組み込ませ、前記チップ実装キャビティ１３６内部を満たす絶縁膜１５２を形成し、前記保護膜１２０を除去して前記外部電極端子１１２を選択的に露出させた後、前記回路基板１３０に前記外部電極端子１１２と電気的に接続される金属回路構造物１６０を形成することができる。前記絶縁膜１５２を形成する過程で、前記外部電極端子１１２は保護膜１２０により保護されるので、前記絶縁膜１５２が前記外部電極端子１１２を覆う現象を防止することができる。これにより、本発明による埋め込み回路基板の製造方法は、製造過程において前記外部電極端子１１２が前記絶縁膜１５２により覆われて、前記金属回路構造物１６０の形成時に前記外部電極端子１１２に効果良く接続されないという現象を防止することによって、前記電気素子１１０と前記金属回路構造物１６０との電気的な接続の信頼性が低下するのを防止することができる。   As described above, in the method of manufacturing the embedded circuit board according to the embodiment of the present invention, the protective film 120 is formed on the external electrode terminal 112 of the electric element 110, and the electric element 110 is formed in the chip mounting cavity 136 of the circuit board 130. The insulating film 152 filling the chip mounting cavity 136 is formed, the protective film 120 is removed, and the external electrode terminals 112 are selectively exposed, and then the external electrode terminals 112 are mounted on the circuit board 130. A metal circuit structure 160 that is electrically connected to the substrate can be formed. In the process of forming the insulating film 152, the external electrode terminal 112 is protected by the protective film 120, so that the phenomenon that the insulating film 152 covers the external electrode terminal 112 can be prevented. Accordingly, in the manufacturing method of the embedded circuit board according to the present invention, the external electrode terminal 112 is covered by the insulating film 152 in the manufacturing process, and the external circuit terminal 112 is effectively connected when the metal circuit structure 160 is formed. By preventing the phenomenon of not being performed, it is possible to prevent the reliability of the electrical connection between the electric element 110 and the metal circuit structure 160 from being lowered.

また、本発明の実施形態による埋め込み回路基板の製造方法は、前記電気素子１１０の外部電極端子１１２に簡単に保護膜１２０を形成した後に工程を行うことによって、前記電気素子１１０とこれに接続される回路パターン１６４との電気的な接続信頼性が低下するのを防止して、埋め込み回路基板の製造工程の効率を向上させることができる。   Also, in the method of manufacturing the embedded circuit board according to the embodiment of the present invention, the protective layer 120 is simply formed on the external electrode terminal 112 of the electric element 110 and then the process is performed to connect the electric element 110 to the electric element 110. Therefore, it is possible to prevent the reliability of electrical connection with the circuit pattern 164 from decreasing, and to improve the efficiency of the manufacturing process of the embedded circuit board.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した実施の形態の説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内でのすべての変更が含まれることが意図される。   The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

１１０ 電気素子
１１２ 外部電極端子
１２０ 保護膜
１３０ 回路基板
１３２ 上面
１３４ 下面
１３６ チップ実装キャビティ
１３８ ビアホール
１４０ 離型フィルム
１５０ 絶縁材
１５２ 絶縁膜
１６０ 金属回路構造物
１６２ 導電性ビア
１６４ 回路パターン DESCRIPTION OF SYMBOLS 110 Electrical element 112 External electrode terminal 120 Protective film 130 Circuit board 132 Upper surface 134 Lower surface 136 Chip mounting cavity 138 Via hole 140 Release film 150 Insulating material 152 Insulating film 160 Metal circuit structure 162 Conductive via 164 Circuit pattern

Claims (9)

外部電極端子を有する電気素子を準備するステップと、
前記外部電極端子が露出されないように、前記外部電極端子を覆う保護膜を形成するステップと、
上面及び下面を有し、上下部が開けられたチップ実装キャビティを有する回路基板を準備するステップと、
前記チップ実装キャビティの開けられた上部が閉じられるように、前記回路基板の前記上面に離型フィルムを付着するステップと、
前記保護膜が前記離型フィルムに密着されるように、前記電気素子を前記チップ実装キャビティ内に位置させるステップと、
前記チップ実装キャビティの開けられた下部を通じて、前記チップ実装キャビティの余り空きを満たすと共に前記回路基板の前記下面を覆う絶縁膜を形成するステップと、
前記回路基板から前記離型フィルムを分離するステップと、
前記外部電極端子が露出するように、前記保護膜を除去するステップと、
前記回路基板に前記外部電極端子と電気的に接続される金属回路構造物を形成するステップ
とを含む埋め込み回路基板の製造方法。 Preparing an electrical element having external electrode terminals;
Forming a protective film covering the external electrode terminal so that the external electrode terminal is not exposed;
Providing a circuit board having a chip mounting cavity having an upper surface and a lower surface, the upper and lower portions being opened; and
Attaching a release film to the upper surface of the circuit board such that the opened top of the chip mounting cavity is closed;
Positioning the electrical element in the chip mounting cavity such that the protective film is in close contact with the release film;
Forming an insulating film that fills the remainder of the chip mounting cavity through the lower part of the chip mounting cavity and covers the lower surface of the circuit board;
Separating the release film from the circuit board;
Removing the protective film so that the external electrode terminal is exposed;
Forming a metal circuit structure electrically connected to the external electrode terminal on the circuit board. 前記保護膜を形成するステップは、前記外部電極端子に絶縁テープを付着するステップを含む請求項１に記載の埋め込み回路基板の製造方法。   The method of manufacturing an embedded circuit board according to claim 1, wherein the step of forming the protective film includes a step of attaching an insulating tape to the external electrode terminal. 前記保護膜を形成するステップは、前記外部電極端子に絶縁膜を塗布するステップを含む請求項１に記載の埋め込み回路基板の製造方法。   The method for manufacturing an embedded circuit board according to claim 1, wherein the step of forming the protective film includes a step of applying an insulating film to the external electrode terminals. 前記保護膜を除去するステップは、前記回路基板から前記離型フィルムを分離するステップで行なわれる請求項１に記載の埋め込み回路基板の製造方法。   The method of manufacturing an embedded circuit board according to claim 1, wherein the step of removing the protective film is performed in a step of separating the release film from the circuit board. 前記保護膜と前記離型フィルムとの間の接着力は、前記外部電極端子と前記保護膜との間の接着力に比べて大きい請求項４に記載の埋め込み回路基板の製造方法。   The method for manufacturing an embedded circuit board according to claim 4, wherein an adhesive force between the protective film and the release film is larger than an adhesive force between the external electrode terminal and the protective film. 前記金属回路構造物を形成するステップは、
前記回路基板を貫通する導電性ビアを形成するステップと、
一部が前記外部電極端子に接続し、他部が前記回路基板の前記導電性ビアに接続する外部回路パターンを形成するステップ
とを備える請求項１に記載の埋め込み回路基板の製造方法。 Forming the metal circuit structure comprises:
Forming a conductive via passing through the circuit board;
The method for manufacturing an embedded circuit board according to claim 1, further comprising: forming an external circuit pattern in which a part is connected to the external electrode terminal and another part is connected to the conductive via of the circuit board. 前記電気素子を準備するステップは、一面に前記外部電極端子が備わる半導体集積回路チップ（ＩＣ）を準備するステップを備える請求項１に記載の埋め込み回路基板の製造方法。   The method of manufacturing an embedded circuit board according to claim 1, wherein the step of preparing the electric element includes a step of preparing a semiconductor integrated circuit chip (IC) having the external electrode terminal on one surface. 前記電気素子を準備するステップは、両側に前記外部電極端子が備わる積層セラミックキャパシタ（ＭｕｌｔｉＬａｙｅｒ Ｃｅｒａｍｉｃ Ｃａｐａｃｉｔｏｒ：ＭＬＣＣ）を準備するステップを含み、
前記保護膜を形成するステップは、前記離型フィルムと接触される前記外部電極端子の部分だけ選択的に露出されないようにする請求項１に記載の埋め込み回路基板の製造方法。 The step of preparing the electric element includes a step of preparing a multilayer ceramic capacitor (MLCC) having the external electrode terminals on both sides,
2. The method of manufacturing an embedded circuit board according to claim 1, wherein in the step of forming the protective film, only a portion of the external electrode terminal that is in contact with the release film is not selectively exposed. 前記絶縁膜を形成するステップは、前記回路基板にプリプレグ膜（ｐｒｅｐｒｅｇ １ａｙｅｒ）を形成するステップを含み、
前記回路基板を製造する方法は、前記プリプレグ膜に銅薄膜を積層するステップをさらに含む請求項１に記載の回路基板の製造方法。 Forming the insulating layer includes forming a prepreg layer on the circuit board;
The method for manufacturing a circuit board according to claim 1, wherein the method for manufacturing the circuit board further includes a step of laminating a copper thin film on the prepreg film.
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