JP2012033032A - 情報処理装置および情報処理方法 - Google Patents

情報処理装置および情報処理方法 Download PDF

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Publication number
JP2012033032A
JP2012033032A JP2010172614A JP2010172614A JP2012033032A JP 2012033032 A JP2012033032 A JP 2012033032A JP 2010172614 A JP2010172614 A JP 2010172614A JP 2010172614 A JP2010172614 A JP 2010172614A JP 2012033032 A JP2012033032 A JP 2012033032A
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JP
Japan
Prior art keywords
bit
output
input
register
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010172614A
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English (en)
Japanese (ja)
Other versions
JP2012033032A5 (enExample
Inventor
Eiji Iwata
英次 岩田
Ryohei Okada
良平 岡田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Sony Corp
Original Assignee
Sony Corp
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sony Computer Entertainment Inc filed Critical Sony Corp
Priority to JP2010172614A priority Critical patent/JP2012033032A/ja
Priority to US13/189,809 priority patent/US20120047355A1/en
Priority to CN2011102172973A priority patent/CN102347773A/zh
Publication of JP2012033032A publication Critical patent/JP2012033032A/ja
Publication of JP2012033032A5 publication Critical patent/JP2012033032A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Executing Machine-Instructions (AREA)
JP2010172614A 2010-07-30 2010-07-30 情報処理装置および情報処理方法 Pending JP2012033032A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2010172614A JP2012033032A (ja) 2010-07-30 2010-07-30 情報処理装置および情報処理方法
US13/189,809 US20120047355A1 (en) 2010-07-30 2011-07-25 Information Processing Apparatus Performing Various Bit Operation and Information Processing Method Thereof
CN2011102172973A CN102347773A (zh) 2010-07-30 2011-08-01 信息处理装置及信息处理方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010172614A JP2012033032A (ja) 2010-07-30 2010-07-30 情報処理装置および情報処理方法

Publications (2)

Publication Number Publication Date
JP2012033032A true JP2012033032A (ja) 2012-02-16
JP2012033032A5 JP2012033032A5 (enExample) 2013-09-12

Family

ID=45546096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010172614A Pending JP2012033032A (ja) 2010-07-30 2010-07-30 情報処理装置および情報処理方法

Country Status (3)

Country Link
US (1) US20120047355A1 (enExample)
JP (1) JP2012033032A (enExample)
CN (1) CN102347773A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017529597A (ja) * 2014-09-25 2017-10-05 インテル・コーポレーション ビット群インターリーブプロセッサ、方法、システムおよび命令
JP2018500666A (ja) * 2014-12-27 2018-01-11 インテル・コーポレーション ベクトルビットギャザーを実行するための方法および装置
JP2018506096A (ja) * 2014-12-27 2018-03-01 インテル・コーポレーション ベクトルビットシャッフルを実行するための方法および装置
JP2022546615A (ja) * 2019-09-10 2022-11-04 アップル インコーポレイテッド 圧縮支援命令

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113436364B (zh) * 2021-06-22 2022-04-08 广汽埃安新能源汽车有限公司 Tbox无效信号值判断方法、装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04142618A (ja) * 1990-10-04 1992-05-15 Toshiba Corp 情報処理装置
US6125406A (en) * 1998-05-15 2000-09-26 Xerox Corporation Bi-directional packing data device enabling forward/reverse bit sequences with two output latches
JP2005352568A (ja) * 2004-06-08 2005-12-22 Hitachi-Lg Data Storage Inc アナログ信号処理回路、並びに、そのデータレジスタ書換方法とそのデータ通信方法
JP2008067361A (ja) * 2006-08-07 2008-03-21 Fuji Xerox Co Ltd 符号化装置、復号化装置、符号化方法及びプログラム
US20090138534A1 (en) * 2007-05-23 2009-05-28 The Trustees Of Princeton University Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233690A (en) * 1989-07-28 1993-08-03 Texas Instruments Incorporated Video graphics display memory swizzle logic and expansion circuit and method
US5210839A (en) * 1990-12-21 1993-05-11 Sun Microsystems, Inc. Method and apparatus for providing a memory address from a computer instruction using a mask register
SG43256A1 (en) * 1995-03-29 1997-10-17 Toshiba Kk Apparatus and method for reading and writing data
US8463837B2 (en) * 2001-10-29 2013-06-11 Intel Corporation Method and apparatus for efficient bi-linear interpolation and motion compensation
KR100486251B1 (ko) * 2002-08-03 2005-05-03 삼성전자주식회사 가변 길이 코드 복호화 장치 및 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04142618A (ja) * 1990-10-04 1992-05-15 Toshiba Corp 情報処理装置
US6125406A (en) * 1998-05-15 2000-09-26 Xerox Corporation Bi-directional packing data device enabling forward/reverse bit sequences with two output latches
JP2005352568A (ja) * 2004-06-08 2005-12-22 Hitachi-Lg Data Storage Inc アナログ信号処理回路、並びに、そのデータレジスタ書換方法とそのデータ通信方法
JP2008067361A (ja) * 2006-08-07 2008-03-21 Fuji Xerox Co Ltd 符号化装置、復号化装置、符号化方法及びプログラム
US20090138534A1 (en) * 2007-05-23 2009-05-28 The Trustees Of Princeton University Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017529597A (ja) * 2014-09-25 2017-10-05 インテル・コーポレーション ビット群インターリーブプロセッサ、方法、システムおよび命令
JP2018500666A (ja) * 2014-12-27 2018-01-11 インテル・コーポレーション ベクトルビットギャザーを実行するための方法および装置
JP2018506096A (ja) * 2014-12-27 2018-03-01 インテル・コーポレーション ベクトルビットシャッフルを実行するための方法および装置
JP2022546615A (ja) * 2019-09-10 2022-11-04 アップル インコーポレイテッド 圧縮支援命令
JP7385009B2 (ja) 2019-09-10 2023-11-21 アップル インコーポレイテッド 圧縮支援命令

Also Published As

Publication number Publication date
US20120047355A1 (en) 2012-02-23
CN102347773A (zh) 2012-02-08

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