CN102347773A - 信息处理装置及信息处理方法 - Google Patents

信息处理装置及信息处理方法 Download PDF

Info

Publication number
CN102347773A
CN102347773A CN2011102172973A CN201110217297A CN102347773A CN 102347773 A CN102347773 A CN 102347773A CN 2011102172973 A CN2011102172973 A CN 2011102172973A CN 201110217297 A CN201110217297 A CN 201110217297A CN 102347773 A CN102347773 A CN 102347773A
Authority
CN
China
Prior art keywords
input
register
output
bit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011102172973A
Other languages
English (en)
Chinese (zh)
Inventor
岩田英次
冈田良平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Sony Corp
Original Assignee
Sony Corp
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp, Sony Computer Entertainment Inc filed Critical Sony Corp
Publication of CN102347773A publication Critical patent/CN102347773A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/40—Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Executing Machine-Instructions (AREA)
CN2011102172973A 2010-07-30 2011-08-01 信息处理装置及信息处理方法 Pending CN102347773A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010-172614 2010-07-30
JP2010172614A JP2012033032A (ja) 2010-07-30 2010-07-30 情報処理装置および情報処理方法

Publications (1)

Publication Number Publication Date
CN102347773A true CN102347773A (zh) 2012-02-08

Family

ID=45546096

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011102172973A Pending CN102347773A (zh) 2010-07-30 2011-08-01 信息处理装置及信息处理方法

Country Status (3)

Country Link
US (1) US20120047355A1 (enExample)
JP (1) JP2012033032A (enExample)
CN (1) CN102347773A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113436364A (zh) * 2021-06-22 2021-09-24 广汽埃安新能源汽车有限公司 Tbox无效信号值判断方法、装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3001306A1 (en) * 2014-09-25 2016-03-30 Intel Corporation Bit group interleave processors, methods, systems, and instructions
US10296489B2 (en) * 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit shuffle
US10296334B2 (en) * 2014-12-27 2019-05-21 Intel Corporation Method and apparatus for performing a vector bit gather
US11086625B2 (en) * 2019-09-10 2021-08-10 Apple Inc. Compression assist instructions

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6125406A (en) * 1998-05-15 2000-09-26 Xerox Corporation Bi-directional packing data device enabling forward/reverse bit sequences with two output latches
CN1707456A (zh) * 2004-06-08 2005-12-14 日立乐金资料储存股份有限公司 模拟信号处理电路、其数据寄存器重写方法及其数据通信方法
US20080030384A1 (en) * 2006-08-07 2008-02-07 Fuji Xerox Co., Ltd. Encoding apparatus, decoding apparatus, encoding method, computer readable medium storing program thereof, and computer data signal
US20090138534A1 (en) * 2007-05-23 2009-05-28 The Trustees Of Princeton University Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5233690A (en) * 1989-07-28 1993-08-03 Texas Instruments Incorporated Video graphics display memory swizzle logic and expansion circuit and method
JP2760649B2 (ja) * 1990-10-04 1998-06-04 株式会社東芝 情報処理装置
US5210839A (en) * 1990-12-21 1993-05-11 Sun Microsystems, Inc. Method and apparatus for providing a memory address from a computer instruction using a mask register
SG43256A1 (en) * 1995-03-29 1997-10-17 Toshiba Kk Apparatus and method for reading and writing data
US8463837B2 (en) * 2001-10-29 2013-06-11 Intel Corporation Method and apparatus for efficient bi-linear interpolation and motion compensation
KR100486251B1 (ko) * 2002-08-03 2005-05-03 삼성전자주식회사 가변 길이 코드 복호화 장치 및 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6125406A (en) * 1998-05-15 2000-09-26 Xerox Corporation Bi-directional packing data device enabling forward/reverse bit sequences with two output latches
CN1707456A (zh) * 2004-06-08 2005-12-14 日立乐金资料储存股份有限公司 模拟信号处理电路、其数据寄存器重写方法及其数据通信方法
US20080030384A1 (en) * 2006-08-07 2008-02-07 Fuji Xerox Co., Ltd. Encoding apparatus, decoding apparatus, encoding method, computer readable medium storing program thereof, and computer data signal
US20090138534A1 (en) * 2007-05-23 2009-05-28 The Trustees Of Princeton University Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113436364A (zh) * 2021-06-22 2021-09-24 广汽埃安新能源汽车有限公司 Tbox无效信号值判断方法、装置
CN113436364B (zh) * 2021-06-22 2022-04-08 广汽埃安新能源汽车有限公司 Tbox无效信号值判断方法、装置

Also Published As

Publication number Publication date
JP2012033032A (ja) 2012-02-16
US20120047355A1 (en) 2012-02-23

Similar Documents

Publication Publication Date Title
KR100435052B1 (ko) 암호화장치
CN115756391B (zh) 用于实现非对称算法rsa模幂计算的硬件电路及方法
CN110138541A (zh) 用于对称密钥密码的统一硬件加速器
CN111427891A (zh) 区块挖掘装置
CN110768785A (zh) 一种编、解码方法、相关装置及计算机设备
CN114968173A (zh) 基于ntt和intt结构的多项式乘法运算方法和多项式乘法器
CN102347773A (zh) 信息处理装置及信息处理方法
JP6159240B2 (ja) 二値算術符号化装置、二値算術符号化方法及び二値算術符号化プログラム
CN115333718A (zh) 基于gpu优化全同态加密电路自举的并行计算方法
CN102184086B (zh) 一种Booth编码器及乘法器
CN101981542B (zh) 多项式数据处理运算
JP2502836B2 (ja) 除算回路の前処理装置
CN116318660A (zh) 一种消息扩展与压缩方法及相关装置
JP3661663B2 (ja) 乱数生成装置、乱数生成方法、乱数生成プログラムおよびオーディオ復号装置と復号方法
CN111190571B (zh) 一种基于二元扩域的模乘电路及其控制方法
JP5354914B2 (ja) 暗号処理装置及び復号処理装置及びプログラム
US7472154B2 (en) Multiplication remainder calculator
JP5606516B2 (ja) Ｎａｆ変換装置
CN113971015B (zh) Uia2计算电路及其数据处理方法、芯片、电子设备及存储介质
JP3742293B2 (ja) 剰余演算装置
CN121070307A (zh) 寄存器状态值处理方法、密钥处理方法、电子设备及介质
JP5267038B2 (ja) 線形帰還シフト演算装置、通信装置、マイクロプロセッサ、及び線形帰還シフト演算装置におけるデータ出力方法
JP2508864B2 (ja) ディジタル論理演算回路
JP3477866B2 (ja) 除算器の除算方法
CN115879555A (zh) 量子模数快速乘法运算方法、装置及模数算术组件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120208