JP2012019338A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which an interlaced to progressive (IP) conversion circuit is integrated thereon so as to reduce a chip area.SOLUTION: A write control regulation circuit 31 generates a write control signal so that writing video data in 1 port SRAMs 22, 23 is performed at a rate of once every four cycles of read-out clock. A read-out control regulation circuit 34 generates a read-out control signal so that reading out video data from the 1 port SRAMs 22, 23 is performed at a rate of once every two cycles of read-out clock. When writing video data in the 1 port SRAMs 22, 23 and reading out video data from the 1 port SRAMs 22, 23 simultaneously are performed, a selector 38 selects and outputs a write control signal delayed by a delay circuit 35. Therefore a 2 ports SRAM can be replaced with the 1 port SRAMs 22, 23, and a chip area of the IP conversion circuit can be reduced.

Description

  The present invention relates to a technique for converting an interlaced video signal into a progressively scanned video signal, and more particularly to reading out a progressively scanned video signal while writing the interlaced video signal and the interpolated video signal into a one-port memory. The present invention relates to an output semiconductor device.

  Conventionally, an interlace method has been adopted in television broadcasting where there are many opportunities to broadcast videos with a lot of movement. However, since flat panel displays such as liquid crystal televisions and plasma televisions that have recently appeared have a high clock frequency, television broadcasts can be reproduced in a progressive manner.

  In this case, it is necessary to convert an image in advance by an IP (Interlace Progressive) conversion circuit in order to display an image created for a conventional interlace method on a progressive television. As a technology related to this, there is an invention disclosed in Patent Document 1 below.

  Patent Document 1 aims to realize an intra-field interpolation scanning line conversion circuit with a memory capacity capable of storing pixels for two lines. A read / write asynchronous memory capable of storing pixels for two lines, an averaging means, a read cycle delay means, and a data holding means are provided at the subsequent stage, and the data stored in the memory is four times the write data rate. After reading, the calculation processing is performed on the read data to generate an intra-field interpolation signal.

  Patent Document 2 aims to reduce the size of the apparatus by enabling competitive control of a write phase and a read phase while using a single port RAM. A register inserted between the serial-parallel conversion circuit and the single-port RAM to temporarily store write data from the serial-parallel conversion circuit to the single-port RAM, and a single register from the register when the write timing and the read timing of the single-port RAM conflict. And a contention control circuit that controls to delay writing to the port RAM.

Japanese Patent Laid-Open No. 10-294926 JP 05-158655 A

  When an interlaced scanning video signal is converted into a sequential scanning video signal and output, it is necessary to read out a video signal of another line while writing a video signal of one line, so a 2-port SRAM (Static Random Access Memory) is used. Often used. However, since the 2-port SRAM has a larger circuit scale than the 1-port SRAM, it is difficult to reduce the chip area of the IP conversion circuit.

  On the other hand, a 1-port SRAM cannot perform a read operation and a write operation in the same cycle. In addition, since there is a restriction that the frequency of writing and the frequency of reading must be the same, in order to use the 1-port SRAM for the IP conversion circuit, some device is required.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which an IP conversion circuit configured to reduce the chip area is integrated. is there.

  According to one embodiment of the present invention, there is provided a semiconductor device that controls conversion from an interlaced video signal to a progressively scanned video signal. The 1-port SRAM is configured to simultaneously write and read video data for two pixels of interlaced video signals. The write control adjustment circuit generates a write control signal so that writing of video data to the 1-port SRAM occurs once every 4 cycles of the read clock. The read control adjustment circuit generates a read control signal so that the video data read from the 1-port SRAM occurs once every two cycles of the read clock. The selector selects and outputs the write control signal delayed by the delay circuit when the video data writing to the 1-port SRAM and the video data reading from the 1-port SRAM occur simultaneously. The video interpolation circuit interpolates and outputs the interlaced video signal. Then, the selector switches between the interlaced video signal read from the 1-port SRAM and the video signal interpolated by the video interpolation circuit, and outputs the video signal as a sequential scanning video signal.

  According to one embodiment of the present invention, the write control adjustment circuit generates the write control signal so that the writing of the video data to the 1-port SRAM occurs once every four cycles of the read clock, and the read control adjustment circuit A readout control signal is generated so that readout of video data from the 1-port SRAM occurs once every two cycles of the readout clock. When the video data writing to the 1-port SRAM and the video data reading from the 1-port SRAM occur simultaneously, the selector selects and outputs the write control signal delayed by the delay circuit. Therefore, the 2-port SRAM can be replaced with the 1-port SRAM, and the chip area of the IP conversion circuit can be reduced.

It is a figure which shows the structural example of the IP conversion circuit at the time of using 2 port SRAM. It is a figure which shows the structural example of the semiconductor device with which the IP conversion circuit 1 in embodiment of this invention was integrated. 3 is a timing chart for explaining the operation of the IP conversion circuit 1 in the embodiment of the present invention shown in FIG. It is a figure which shows the structural example of SRAM11 and 12 shown in FIG. FIG. 5 is a diagram for explaining the configuration of SRAMs 11 and 12 shown in FIG. 4 in more detail. 6 is a timing chart for explaining the operation of the control circuit 21 shown in FIG. 5. 3 is a diagram illustrating a configuration example of a write control adjustment circuit 31 and a timing chart for explaining an operation thereof. FIG. It is a figure which shows the structural example of the frequency change circuit 32 and 33. FIG. 3 is a diagram illustrating a configuration example of a read control adjustment circuit 34 and a timing chart for explaining an operation thereof. FIG. 5 is a diagram illustrating a configuration example of an upper / lower selection circuit 37. FIG. 3 is a diagram illustrating a configuration example of an upper / lower selection circuit 24. FIG.

  FIG. 1 is a diagram illustrating a configuration example of an IP conversion circuit when a 2-port SRAM is used. The IP conversion circuit includes an SRAM 101 that stores interlaced video signals, an SRAM 102 that stores interpolated video signals, and a selector 103.

  The SRAM 101 includes two-port SRAMs 111 and 112 of 20 bits × 1024 words, and a selector 113. Note that the configuration of the SRAM 102 is the same as the configuration of the SRAM 101.

  When writing interlaced video signal data, the 2-port SRAMs 111 and 112 in the SRAM 101 receive continuous write control signals of a maximum frequency of 85 MHz and a maximum of 1920 cycles, and write addresses from 0 to 1919 are synchronized with this. And 20-bit interlaced video signal data are sequentially input.

  In addition, when reading interlaced video signal data, the 2-port SRAMs 111 and 112 in the SRAM 101 are input with a continuous read control signal having a maximum frequency of 170 MHz and a maximum of 1920 cycles, and read addresses from 0 to 1919. , 20-bit interlaced video signal data is sequentially output. The selector 113 switches the video data signal output from the 2-port SRAMs 111 and 112 as appropriate.

  When the interpolated video signal data is written, the 2-port SRAMs 111 and 112 in the SRAM 102 are inputted with continuous write control signals of a maximum frequency of 85 MHz and a maximum of 1920 cycles, and in synchronization therewith, write addresses of addresses 0-1919. And 20-bit interpolated video signal data are sequentially input.

  In addition, when reading the interpolated video signal data, the 2-port SRAMs 111 and 112 in the SRAM 102 are input with a continuous read control signal having a maximum frequency of 170 MHz and a maximum of 1920 cycles, and read addresses at addresses 0 to 1919. , 20-bit interpolated video signal data is sequentially output. The selector 113 switches the video signal data output from the 2-port SRAMs 111 and 112 as appropriate.

  The selector 103 sequentially switches between the interlaced video signal data output from the SRAM 101 and the interpolated video signal data output from the SRAM 102, thereby outputting the sequentially scanned video signal data.

  As described above, it is difficult to reduce the chip area in the IP conversion circuit using the 2-port SRAM. The IP conversion circuit according to the embodiment of the present invention is intended to reduce the circuit scale by using a 1-port SRAM.

(Embodiment)
FIG. 2 is a diagram showing a configuration example of a semiconductor device in which the IP conversion circuit 1 according to the embodiment of the present invention is integrated. The IP conversion circuit 1 includes SRAMs 11 and 12, a video interpolation circuit 13, and a selector 14. Compared with the IP conversion circuit using the 2-port SRAM shown in FIG. 1, four 40-bit × 512-word 1-port SRAMs are used for each of the SRAMs 11 and 12, and a control circuit for controlling them is added. The point is different.

  That is, in the IP conversion circuit 1 according to the present embodiment, the amount of data written or read in one cycle is doubled by doubling the SRAM bit width and halving the number of words. The control signals for writing and data reading are changed from continuous to once every two cycles.

  FIG. 3 is a timing chart for explaining the operation of the IP conversion circuit 1 according to the embodiment of the present invention shown in FIG. The SRAM 11 receives a continuous write control signal having a maximum frequency of 85 MHz and a maximum of 1920 cycles, and in synchronization therewith, a write address of addresses 0 to 1919 and video signal data of 20-bit interlaced scanning are sequentially input.

  The SRAM 12 receives a continuous write control signal having a maximum frequency of 85 MHz and a maximum of 1920 cycles, and in synchronization with this, a write address of addresses 0 to 1919 and 20-bit interpolated video signal data are sequentially input. The

  The video interpolation circuit 13 generates the interpolated video signal data of the second line from the interlaced video signal data of the first line and the third line, for example, and outputs it to the SRAM 12.

  The SRAM 11 receives a continuous read control signal having a maximum frequency of 170 MHz and a maximum of 1920 cycles and a read address of addresses 0 to 1919, and sequentially outputs video signal data of 20-bit interlaced scanning.

  Further, the SRAM 12 receives a continuous read control signal having a maximum frequency of 170 MHz and a maximum of 1920 cycles and a read address of addresses 0 to 1919, and sequentially outputs 20-bit interpolated video signal data.

  The selector 14 sequentially switches the interlaced video signal data output from the SRAM 11 and the interpolated video signal data output from the SRAM 12, thereby outputting the video signal data of the progressive scan.

  FIG. 4 is a diagram showing a configuration example of the SRAMs 11 and 12 shown in FIG. The SRAM 11 includes a control circuit 21, 1-port SRAMs 22 and 23 of 40 bits × 512 words, and a selector 24. Note that the configuration of the SRAM 12 illustrated in FIG. 4 is the same as the configuration of the SRAM 11.

  FIG. 5 is a diagram for explaining the configuration of SRAMs 11 and 12 shown in FIG. 4 in more detail. The control circuit 21 includes a write control adjustment circuit 31, a write address frequency change circuit 32, a write data frequency change circuit 33, a read control adjustment circuit 34, a delay circuit 35, and a timing comparison circuit 36. And an upper / lower selection circuit 37 for write data, selectors 38 and 40, and an OR circuit 39. In FIG. 5, the selector 24 shown in FIG. 4 is described as an upper / lower selection circuit 24 for read data.

  FIG. 6 is a timing chart for explaining the operation of the control circuit 21 shown in FIG. The write control adjustment circuit 31 “1” from a continuous write control signal (pre-adjustment write control signal (a)) once every two cycles of the write clock and once every four cycles of the adjusted write clock (read clock). A post-adjustment write control signal is generated and output. The adjusted write clock is the same clock as the read clock.

  Further, the frequency transfer circuits 32 and 33 put the write address and the write data on the frequency of the adjusted write clock (read clock) so as to be synchronized with the adjusted write control signal generated by the write control adjusting circuit 31. Change.

  The read control adjustment circuit 34 generates and outputs an adjusted read control signal (d) that becomes “1” once every two cycles of the read clock from a continuous read control signal (read control signal (c) before adjustment). To do.

  The delay circuit 35 delays the adjusted write control signal output from the write control adjustment circuit 31 by one clock of the adjusted write clock (read clock) and outputs the delayed control signal to the selector 38.

  The timing comparison circuit 36 compares the adjusted write control signal output from the write control adjustment circuit 31 with the adjusted read control signal output from the read control adjustment circuit 34, and the two control signals have the same timing. In the case of 1 ″, the selector 38 selects the signal output from the delay circuit 35. In other cases, the selector 38 selects the signal output from the write control adjustment circuit 31, and the adjusted write control is performed. Output as signal (b).

  As described above, when the adjusted write control signal and the adjusted read control signal become “1” at the same timing, the data read is prioritized and the data write is delayed by one cycle of the adjusted write clock. To do. This is because the read data needs to be output at a constant cycle and cannot be delayed.

  The upper / lower selection circuit 37 holds 20-bit video signal data for two pixels and outputs it to the 1-port SRAMs 22 and 23 as 40-bit video signal data. At this time, the upper and lower selection circuit 37 refers to the least significant bit of the write address. If the write address is an even address, the video signal data is arranged in the lower 20 bits, and if the write address is an odd address, the video signal data is assigned to the upper 20 bits. Place in bits.

  The OR circuit 39 uses the logical sum of the adjusted write control signal (b) output from the selector 38 and the adjusted read control signal (d) output from the read control adjustment circuit 34 as an SRAM selection control signal as one port. Output to SRAMs 22 and 23.

  The selector 40 selects the upper 10 bits of the write address output from the frequency transfer circuit 32 when the adjusted read control signal (d) output from the read control adjustment circuit 34 is “0”, and uses it as the SRAM address. The data is output to the 1-port SRAMs 22 and 23. When “1”, the upper 10 bits of the read address are selected and output to the 1-port SRAMs 22 and 23 as the SRAM address.

  The upper and lower selection circuit 24 refers to the least significant bit of the read address. If the read address is an even address, the lower 20 bits of the video signal data output from the 1-port SRAMs 22 and 23 are output. If the read address is an odd address, the upper 20 bits of video signal data are selected and output.

  FIG. 7 is a timing chart for explaining a configuration example of the write control adjustment circuit 31 and its operation. As shown in FIG. 7A, the write control adjustment circuit 31 includes flip-flops (hereinafter abbreviated as FF) 51, 52, 54 and 56 and combinational circuits 53 and 55. The FF 54 is a 2-bit FF.

  The FF 51 holds the write control signal (a) at the rising edge of the write clock. The FF 52 holds the output from the FF 51 at the rising edge of the adjusted write clock (read clock).

  The combinational circuit B ′ outputs “0” when the value B output from the FF 54 is “3” or the signal A output from the FF 52 is “0”, and the value B otherwise. Is incremented and output to FF54. The FF 54 holds the value output from the combinational circuit B ′ 53 at the rising edge of the adjusted write clock (read clock).

  The combinational circuit C′55 outputs “1” when the value B output from the FF 54 is “2”, and outputs “0” otherwise. The FF 56 holds the value output from the combinational circuit C′55 at the rising edge of the adjusted write clock (read clock).

  As shown in FIG. 7B, “1” is output from the FF 56 at the next rising edge of the adjusted write clock after the value B output from the FF 54 becomes “2”, and four cycles of the adjusted write clock. An adjusted write control signal that is “1” once is generated.

  FIG. 8 is a diagram illustrating a configuration example of the frequency changing circuits 32 and 33. The frequency transfer circuit 32 includes FFs 41 and 42. The FF 41 holds the write address at the rising edge of the write clock. The FF 42 holds the value output from the FF 41 at the rising edge of the adjusted write clock. It is assumed that there are as many FFs 41 and 42 as there are bits corresponding to the number of bits of the write address.

  The frequency transfer circuit 33 includes FFs 43 and 44. The FF 43 holds the write data at the rising edge of the write clock. The FF 44 holds the value output from the FF 43 at the rising edge of the adjusted write clock. It is assumed that there are as many FFs 43 and 44 as there are bits corresponding to the number of bits of write data.

  FIG. 9 is a diagram showing a configuration example of the read control adjustment circuit 34 and a timing chart for explaining the operation thereof. As shown in FIG. 9A, the read control adjustment circuit 34 includes a combinational circuit 61, an FF 62, and an AND circuit 63.

  The combinational circuit E′61 outputs “0” when the value E output from the FF 62 is “1” or the read control signal D is “0”, and is output from the FF 62 otherwise. Invert the value to be output.

  The FF 62 holds the value output from the combinational circuit E′61 at the rising edge of the read clock. The AND circuit 63 outputs a logical product of a value obtained by inverting the value output from the FF 62 and the read control signal D as an adjusted read control signal F.

  As shown in FIG. 9B, after the read control signal D becomes “1”, an adjusted read control signal that becomes “1” once every two cycles of the read clock is output.

  FIG. 10 is a diagram illustrating a configuration example of the upper / lower selection circuit 37. The upper / lower selection circuit 37 includes selectors 71 and 72 and FFs 73 and 74. It is assumed that there are as many selectors 71 and 72 and FFs 73 and 74 as there are bits corresponding to the number of bits of write data.

  The selector 71 selects the value output from the FF 73 when the least significant bit of the write address is “0” and outputs the selected value to the FF 73, and selects the write data when the least significant bit is “1” to the FF 73. Output. The FF 73 holds the value output from the selector 71 at the rising edge of the adjusted write clock. Therefore, the FF 73 holds and outputs the upper 20 bits of video signal data whose write address is an odd address.

  The selector 72 selects the value output from the FF 74 when the least significant bit of the write address is “1” and outputs the selected value to the FF 74, and selects the write data when the least significant bit is “0”. Output. The FF 74 holds the value output from the selector 72 at the rising edge of the adjusted write clock. Therefore, the FF 74 holds and outputs the lower 20 bits of video signal data whose write address is an even address.

  FIG. 11 is a diagram illustrating a configuration example of the upper / lower selection circuit 24. The upper / lower selection circuit 24 includes a selector 81 and an FF 82. It is assumed that there are as many selectors 81 and FFs 82 as the number corresponding to the number of bits of the video signal data.

  The selector 81 selects the lower 20 bits of video signal data when the least significant bit of the read address is “0” and outputs it to the FF 82, and the upper 20 bits of video signal data when the least significant bit is “1”. Is selected and output to the FF 82. The FF 82 holds the value output from the selector 81 at the rising edge of the read clock and outputs it as 20-bit video signal data.

  In the above description, the SRAMs 11 and 12 are composed of 40-bit × 512-word 1-port SRAMs 22 and 23, and two pixels of the video signal data are written and read simultaneously. However, the SRAMs 11 and 12 may be configured by a 1-port SRAM having a larger number of bits, and three or more pixels of video signal data may be simultaneously read and written.

  The SRAMs 11 and 12 are composed of two 40-bit × 512-word 1-port SRAMs, and addresses 0 to 511 are allocated to the 1-port SRAM 22 and addresses 512 to 1023 are allocated to the 1-port SRAM 23. . However, it may be configured by one 1-port SRAM having a larger number of words, or may be configured by three or more 1-port SRAMs having a smaller number of words. These are items that should be selected for the convenience of implementation.

  As described above, according to the IP conversion circuit 1 in the present embodiment, the SRAMs 22 and 23 are composed of one-port SRAMs that can simultaneously write and read two pixels of the video signal data, and the read clock has four cycles. The video signal data is written once, and the video signal data is read once every two cycles of the read clock. As a result, the 2-port SRAM can be replaced with the 1-port SRAM, and the chip area can be reduced.

  When the present applicant applied the present invention to the IP conversion circuit, the chip area was reduced by replacing the 2-port SRAM with the 1-port SRAM as compared with the increase in the chip area due to the increase in circuit scale accompanying the change of the control circuit. It was confirmed that the effect was much larger and the chip area was roughly halved.

  Further, when the adjusted write control signal and the adjusted read control signal become “1” at the same timing, the data read is preferentially performed, so that the reading of the video signal data is prevented from being delayed. It became possible.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 IP conversion circuit, 11, 12, 101, 102 SRAM, 13 video interpolation circuit, 14, 38, 40, 71, 72, 81, 103, 113 selector, 21 control circuit, 22, 23 1-port SRAM, 24 upper and lower Selection circuit, 31 Write control adjustment circuit, 32, 33 Frequency switching circuit, 34 Read control adjustment circuit, 35 Delay circuit, 36 Timing comparison circuit, 37 Upper / lower selection circuit, 39 OR circuit, 41-44, 51, 52, 54, 56, 62, 73, 74, 82 FF, 53, 55, 61 combinational circuit, 63 AND circuit, 111, 112 2-port SRAM.

Claims (4)

A semiconductor device for controlling the conversion from interlaced video signals to progressively scanned video signals,
A 1-port memory for simultaneously writing and simultaneously reading video data for at least two pixels of the interlaced video signal;
Write control means for generating a write control signal so that writing of video data to the 1-port memory occurs once in a first plurality of cycles of the clock;
Read control means for generating a read control signal so that reading of video data from the one-port memory occurs once in a second plurality of cycles of the clock;
Delay means for delaying the writing of the video data when the writing of the video data to the 1-port memory and the reading of the video data from the 1-port memory occur simultaneously;
Video interpolation means for interpolating the interlaced video signal;
A semiconductor device comprising: interlaced scanning video signals read from the one-port memory; and selection means for switching between the video signals interpolated by the video interpolating means and outputting them as sequential scanning video signals. The delay unit includes a comparison circuit that compares timings of a write control signal output from the write control unit and a read control signal output from the read control unit;
A delay circuit for delaying the write control signal output from the write control means by one cycle of the clock;
When the comparison circuit detects the coincidence between the timing of the write control signal and the timing of the read control signal, the write control signal output from the delay circuit is selected and output, and a timing mismatch is detected. The semiconductor device according to claim 1, further comprising: a selector that selects and outputs a write control signal output from the write control means. The semiconductor device further includes a second one-port memory for simultaneously writing and simultaneously reading video data for at least two pixels of the video signal interpolated by the video interpolating means;
Second write control means for generating a write control signal so that writing of video data to the second one-port memory occurs once in the first plurality of cycles of the clock;
Second read control means for generating a read control signal such that reading of video data from the second one-port memory occurs once in the second plurality of cycles of the clock;
Second delay means for delaying the writing of the video data when the writing of the video data to the second one-port memory and the reading of the video data from the second one-port memory occur simultaneously; The semiconductor device of Claim 1 or 2 containing. A second comparison circuit configured to compare a timing of a write control signal output from the second write control unit and a read control signal output from the second read control unit; ,
A second delay circuit for delaying a write control signal output from the second write control means by one cycle of the clock;
When coincidence between the timing of the write control signal and the timing of the read control signal is detected by the second comparison circuit, the write control signal output from the second delay circuit is selected and output, 4. The semiconductor device according to claim 3, further comprising: a second selector that selects and outputs a write control signal output from the second write control means when timing mismatch is detected.

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