JP4626404B2 - Video signal phase adjustment circuit - Google Patents

Description

  The present invention relates to a video signal phase adjustment circuit, and more particularly, to a video signal phase adjustment circuit that synchronizes an input digital video signal with a reference clock, performs phase adjustment, and field delay or frame delay.

  An automatic phase adjustment circuit for a television video signal is used in a production switcher, a transmission switcher, an automatic phase adjustment device called an AVDL (Automatic Video Delay Line), and the like. This is a circuit for automatically adjusting the phase.

  As an example of this type of phase adjustment circuit, a circuit having a phase adjustment range of a little less than n (H) (n is a positive integer and may be a value larger than 1 in particular. H represents a horizontal period) is known. (For example, refer to Patent Document 1).

  FIG. 10 is a block diagram of an example of a conventional production switcher or transmission switcher. Referring to the figure, an example of a conventional production switcher or transmission switcher includes phase adjustment circuits 65 to 67, a super signal synthesizer 68, and a super processor device 69.

  The super processor device 69 includes super processor pre-processing circuits 72 and 73, field memories or frame memories 74 and 75, and a super processor post-processing circuit 76. Reference numeral 70 denotes a signal output terminal, and 71 denotes a reference phase signal input terminal.

  The phase adjustment circuit 65 is a phase adjustment circuit for base signals, the phase adjustment circuit 66 is a phase adjustment circuit for super video signals, and the phase adjustment circuit 67 is a phase adjustment circuit for key signals.

  In many cases, the phase adjustment range of the phase adjustment circuit 65 is slightly less than n (H) (n is a positive integer greater than 1). Even in such a case, the phase adjustment range of the phase adjustment circuits 66 and 67 needs to include at least a part in front of the phase adjustment range of the phase adjustment circuit 65. This is because the input base signal 61 is often delayed by nearly n (H) from the same phase with respect to the reference phase (0 (H)) signal input from the input terminal 71, while the input super video signal and the input key signal 63. This is because the phase is often in phase with or close to the reference phase signal. Therefore, the phase adjustment range of the phase adjustment circuits 66 and 67 is set to be slightly less than n (H) as in the case of the input base signal 61 (n is a positive integer greater than 1).

  In addition, the super processor device 69 of a production switcher or a transmission switcher often has a field memory or a frame memory at the video signal or key signal input unit (see, for example, Patent Document 2).

  11 is a circuit diagram from the phase adjustment circuit 66 to the field memory or frame memory 74 in FIG. 10, or a circuit diagram from the phase adjustment circuit 67 to the field memory or frame memory 75. Note that the superprocessor preprocessing circuits 72 and 73 are either fixed delay circuits or no circuits, and are omitted because they do not affect the following discussion.

  Referring to FIG. 11, the circuit from the phase adjustment circuit 66 to the field memory or frame memory 74, or the circuit from the phase adjustment circuit 67 to the field memory or frame memory 75 includes an input parallel digital video signal and an input parallel video clock signal. , A write address reset pulse generation circuit 52 that resets a write address of the line memory 51, a read address reset pulse generation circuit 53 that resets a read address, and the output of the line memory 51 1-field memory or 1-frame memory 54 for inputting a reference synchronization clock signal, a write-address generating circuit 55 for generating an address for writing to the 1-field memory or 1-frame memory 54, and reading Configured to include a read address generating circuit 56 for generating the address.

  The write address reset pulse generation circuit 52 generates a write address reset pulse synchronized with the corresponding parallel video clock signal from the parallel digital video signal and the parallel video clock signal, supplies the pulse to the line memory 51, and reads the read address. The reset pulse generation circuit 53 generates a read address reset pulse signal synchronized with the reference clock signal from the reference synchronization signal and the reference synchronization clock signal (hereinafter simply referred to as a reference clock signal), and generates the line memory 51, the write address The corresponding pulse is supplied to the generation circuit 55 and the read address generation circuit 56.

  The write address generation circuit 55 generates a write address signal synchronized with the corresponding reference clock signal and the corresponding pulse signal from the reference synchronization signal, the reference clock signal, and the read address reset pulse signal, and supplies the write address signal to the one field memory or the one frame memory 54. The read address generation circuit 56 supplies a corresponding address, generates a read address signal synchronized with the corresponding reference clock signal and the corresponding pulse signal from the reference synchronization signal, the reference clock signal, and the read address reset pulse signal, and generates one field memory. Alternatively, the corresponding address is supplied to the 1-frame memory 54.

  As a result, a parallel digital video signal that is synchronized with the reference clock signal and phase-adjusted by the reference synchronization signal and delayed by one field or one frame is output.

  In recent devices, there is an inexpensive and large-capacity memory such as an SDRAM (Synchronous DRAM). Many FPGAs and PLDs have a large capacity and have a built-in memory. Combining SDRAM with logic circuits built in FPGA or PLD and configuring field memory or frame memory, or configuring line memory using memory in FPGA or PLD, etc. It is possible to reduce.

Japanese Patent No. 2890861 (paragraph 0002) JP 2001-128063 A (paragraph 0002)

  However, the conventional phase adjustment circuit (for example, the phase adjustment circuit 66 for the super video signal and the phase adjustment circuit 67 for the key signal) has the following problems.

  The first problem is that the phase adjustment range of a conventional phase adjustment circuit (for example, the above-described phase adjustment circuits 66 and 67) is set to be slightly less than n (H) (n is a positive integer greater than 1). This is difficult due to the above constraints. On the other hand, it takes a relatively large cost to realize this.

  This is because the memory capacity of FPGA (Field Programmable Gate Array) or PLD (Programmable Logic Device) is limited. As described above, the phase adjustment range of the phase adjustment circuit for the base signal often needs to be wide as n (H) (n is a positive integer greater than 1). In some cases, there is a shortage of memory used for the super video signal and the key signal. Further, in order to make up for this shortage, it is necessary to add another line memory device, which increases the cost.

  The second problem is that when the phase adjustment range of the phase adjustment circuit is set to a little less than 1 (H) or n ′ (H) (n ′ is an integer smaller than n) due to device restrictions, a desired phase is set. This means that it may not be included in the phase adjustment range.

  This is because the conventional circuit does not have a circuit for finely adjusting the phase adjustment range in units of 1 (H) or in a range smaller than 1 (H).

  Accordingly, an object of the present invention is to realize phase adjustment of a phase adjustment circuit (for example, the phase adjustment circuit 66 for the super video signal and the phase adjustment circuit 67 for the key signal) using a memory having a relatively small capacity. In addition, even when the phase adjustment range is less than 1 (H) or n ′ (H) (n ′ is an integer smaller than n), an image that can include a desired specific phase in the phase adjustment range The object is to provide a signal phase adjustment circuit.

  In order to solve the above problems, a phase adjustment circuit for a video signal according to the present invention is a phase adjustment circuit for a video signal that performs synchronization with a reference clock of an input digital video signal, phase adjustment, and field delay or frame delay. The circuit includes a first line memory that synchronizes and adjusts the phase of the input digital video signal with the reference clock, and a second line memory that provides a delay of one horizontal period or less to the output of the first line memory. And a field or frame memory that gives a delay of an integer multiple of one horizontal period to the output of the second line memory.

  In the present invention, a two-field memory or a two-frame memory is provided, and this memory realizes a field delay or a frame delay and a delay of an integer multiple of 1 (H) at a time. In addition to the first line memory for phase adjustment, a second line memory is added to realize an arbitrary fixed delay of a reference clock signal unit of 1 (H) or less.

  The first effect is that a field delay or a frame delay and a delay of an integer multiple of 1 (H) can be realized at a time by providing a memory having a relatively small capacity such as a two-field memory or a two-frame memory. is there.

  The reason is that the field memory or the frame memory can be constituted by an inexpensive SDRAM, etc., and doubling the required capacity can be done at an inexpensive cost, and it is easy to add a device if necessary. The reason why the address space of the peripheral logic circuit is doubled is that it is inexpensive and easy. Further, the capacity of the line memory required for the phase adjustment circuit is from a minimum of 2 (H), and when the pull-in range of the phase adjustment circuit for the base signal is 3 (H) or more, the capacity of the line memory is the prior art. It is also because it will save more.

  The second effect is that even when the phase adjustment range of the phase adjustment circuit is less than 1 (H) or n ′ (H) (n ′ is an integer smaller than n), a desired specific phase is set in the phase adjustment range. It can be included.

  This is because a circuit (second line memory circuit) that finely adjusts the phase adjustment range in units of 1 (H) or in a range smaller than 1 (H) is provided.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a first embodiment of a video signal phase adjusting circuit according to the present invention. Referring to the figure, the video signal phase adjusting circuit according to the present invention includes a first line memory 1, a first write address reset pulse generating circuit 2, and a first read address reset pulse / second write. Address reset pulse generation circuit 3, 2-field memory or 2-frame memory 4, write address generation circuit 5, read address generation circuit 6, second line memory 7, and second read address reset pulse generation circuit 8 And a control circuit 9.

  The control circuit 9 supplies the control signal n to the second read address reset pulse generation circuit 8 and supplies the control signal p to the write address generation circuit 5.

  The first write address reset pulse generation circuit 2 generates a first write address reset pulse c synchronized with the parallel video clock signal b from the parallel digital video signal a and the parallel video clock signal b. The pulse c is supplied to the line memory 1.

  The first read address reset pulse / second write address reset pulse generation circuit 3 also uses the first read address reset pulse / second pulse synchronized with the reference clock signal e from the reference synchronization signal d and the reference clock signal e. Write address reset pulse signal f is generated and the corresponding address reset pulse signal f is supplied to the first line memory 1, the second line memory 7 and the second read address reset pulse generation circuit 8.

  The first line memory 1 includes a parallel digital video signal a, a parallel video clock signal b, a first write address reset pulse c, a first read address reset pulse / second write address reset pulse signal f, and a reference clock. By receiving the signal e, a video signal output g synchronized with the corresponding reference clock signal e is obtained.

  The second read address reset pulse generation circuit 8 corresponds to the first read address reset pulse and second write address reset pulse signal f, the control signal n supplied from the control circuit 9, and the reference clock signal e. A second read address reset pulse signal i synchronized with the reference clock signal e is generated, and the corresponding second read address reset pulse signal is sent to the second line memory 7, write address generation circuit 5, and read address generation circuit 6. i is supplied.

  The second line memory 7 receives the parallel digital video signal g, the first read address reset pulse / second write address reset pulse signal f, the second read address reset pulse signal i, and the reference clock signal e. A video signal output j synchronized with the reference clock signal e is obtained.

  The read address generation circuit 6 generates a read address re-signal l synchronized with the reference clock signal e from the reference synchronization signal d, the reference clock signal e, and the second read address reset pulse signal i to generate two fields. The corresponding read address signal 1 is supplied to the memory or 2-frame memory 4 and the write address generation circuit 5.

  The write address generation circuit 5 writes data synchronized with the reference clock signal e from the read address signal l, the second read address reset pulse signal i, the control signal p supplied from the control circuit 9, and the reference clock signal e. The address signal k is generated and the corresponding write address signal k is supplied to the 2-field memory or 2-frame memory 4.

  The two-line memory or the two-frame memory 4 obtains a parallel video signal m synchronized with the reference clock signal e from the write address signal k, the read address signal l, and the reference clock signal e.

  Next, the operation of the circuit shown in FIG. 1 will be described with reference to FIGS. FIG. 2 is a time chart of signals from the input of the first line memory 1 to the output of the second line memory 7 in the first embodiment. FIG. 3 is an input / output signal of the two-field memory or the two-frame memory 4 in FIG. It is a time chart including 2 and FIG. 3 are assumed to be equivalent to the signals a to p in FIG.

  Taking a HDTV (High Definition Television) video signal standardized by BTA (Broadcasting Technology Association) S-002B as an example, specific video signals and clock signals are as shown in FIGS.

  The first write address reset pulse generation circuit 2 detects an EAV (End of Active Video) synchronization signal from the parallel digital video signal and outputs a pulse (c in FIG. 2) based on the horizontal period.

  Here, the cycle of the pulse c is not only one horizontal cycle (1 (H)), but also a positive integer multiple of the horizontal cycle, such as three horizontal cycles according to the memory capacity of the first line memory 1. The first write address reset pulse generation circuit 2 can easily generate a pulse having a period that is a multiple of the horizontal period by detecting the line number ID from the parallel digital video signal. . Here, for simplification, the case of one horizontal cycle will be described as an example.

  The first read address reset pulse / second read address reset pulse generation circuit 3 receives the reference synchronization signal d and the reference clock signal e, and receives the first read address reset pulse / second write address reset pulse signal f. Is generated. Based on these signals, the output of the first line memory 1 becomes the read data g of the first line memory synchronized with the reference clock signal e.

  Next, the second line memory 7 and its control circuit part will be described. As described above, the capacity of the second line memory 7 will be described by taking one horizontal cycle as an example. The second read address reset pulse generation circuit 8 receives the first read address reset pulse and the second write address reset pulse signal (f in FIG. 2), the reference clock signal (e in FIG. 2), and the control signal n. In response, a second read address reset pulse signal (i in FIG. 2) is generated. Here, the phase difference between f and i depends on the control signal n. The phase difference between f and i is in units of one clock of the reference clock signal (e in FIG. 2). Since both the periods of f and i are one horizontal period, the phase difference between f and i is also a maximum of one horizontal period.

  The second line memory 7 includes a parallel digital video signal (g in FIG. 2), a first read address reset pulse / second write address reset pulse signal (f in FIG. 2), and a second read address reset pulse signal. (I in FIG. 2) and the reference clock signal (e in FIG. 2) are received, and a video signal output (j in FIG. 2) synchronized with the reference clock signal (e in FIG. 2) is obtained. Here, since the phase difference between f and i is a maximum of one horizontal period, the phase difference between g and j is also a maximum of one horizontal period. The phase difference between g and j depends on the control signal n. Therefore, the phase difference between g and j, that is, the delay time in the second line memory 7 is a maximum of one horizontal cycle, and can be arbitrarily set in units of one clock of the reference clock signal (e in FIG. 2) by the control signal n. It can be set.

  Next, FIG. 3 will be described. For the sake of simplicity, the case of 1 frame delay is shown below. In that case, it becomes a two-frame memory. In FIG. 3, the data or address is shown in units of one horizontal period.

  One frame = Nf (H) (H is a horizontal period). Nf is an integer. Taking an HDTV video signal standardized by BTA S-002B as an example, Nf = 1125.

  The read address generation circuit 6 receives the reference synchronization signal d, the reference clock signal (e in FIG. 2), and the second read address reset pulse signal (i in FIGS. 2 and 3) and receives the read address signal (FIG. 3). Of l). Here, the value of the read address signal (l in FIG. 3) is Nr, and the value of Nr in a specific period is Nro. Nr free-runs with a cycle of 2 × Nf. Here, it is assumed that the count is incremented from 1, and the next after 2 × Nf is reset and returned to 1.

  The write address generation circuit 5 receives the read address signal (l in FIG. 3), the reference clock signal (e in FIG. 2), the second read address reset pulse signal (i in FIG. 2), and the control signal p. A write address signal (k in FIG. 3) is generated. Here, it is assumed that the value of the write address signal (k in FIG. 3) is Nw, and the value of Nw in a specific period same as Nro is Nwo. Nw is also a cycle of 2 × Nf. Here, it is assumed that the count is incremented from 1, and the next after 2 × Nf is reset and returned to 1.

  The phase difference between the case where the write address Nw is Nro and the case where it is Nwo is Nf−ΔNf + ΔNos (H). Here, ΔNf is the number of lines (integer) to be read out quickly for other processing (edge / shadow generation, etc.) in the subsequent stage of the apparatus using this phase adjustment circuit. This is a device specific value. Usually larger than 0, but may be 0. In general, ΔNf is sufficiently smaller than Nf. ΔNos is an integer of 0 or more given by the control signal p. That is, the write address generation circuit 5 generates a read address signal (l in FIG. 3) and a signal having a phase difference Nf−ΔNf + ΔNos (H).

  When the value of the write address signal (k in FIG. 3) is Nw, the value of the write data j written to the two-frame memory 4 is DNw, and particularly the value of the corresponding data when Nw = Nwo is DNwo.

  When the value of the read address signal (l in FIG. 3) is Nr, the value of read data m read from the two-frame memory 4 is DNr, and in particular, the value of the corresponding data when Nr = Nro is DNro.

  Here, when the write address Nw is Nro, the value DNw of the data j written to the 2-frame memory 4 is DNwo.

  Viewing the above contents from another angle, the data DNro written in the two-line memory 4 when the write address Nw is Nro is read after Nf−ΔNf + ΔNos (H). Here, since ΔNos (H) is an integer equal to or greater than 0 given by the control signal p, ΔNos (H) is added by the control in addition to the delay of reading in addition to Nf−ΔNf (H).

  Here, Nf−ΔNf (H) corresponds to one frame delay in the prior art. Alternatively, when ΔNf = 0, Nf (H) = 1 frame delay, and for simplicity, one frame delay may be considered as a special case of ΔNf = 0.

  From the above description, it can be seen that the 2-frame memory 4 and its peripheral circuits have a delay of an arbitrary integral multiple of 1 (H) in addition to the delay of 1 frame.

  Here, in particular, when ΔNf ≧ ΔNos, it can be seen that the two-frame memory 4 is actually sufficient for one-frame memory.

  In the two-frame memory 4 described above, writing and reading are restricted in units of one horizontal. This regulation is a condition that can be applied to an inexpensive frame memory using SDRAM. Of course, the present invention can also be applied to expensive memories such as DPRAM (Dual port RAM) and FIFO (Fast In Fast Out) that support asynchronous reading and writing.

  FIG. 4 is a diagram showing an example of a phase chart of a switcher using the video signal phase adjusting circuit according to the present invention as the super video signal phase adjusting circuit.

  First, the operations of the conventional base signal phase adjusting circuit 65 (see FIG. 10) and the conventional super video signal phase adjusting circuit 66 (see FIG. 10) will be described with reference to FIG.

  As can be seen from the figure, the phase adjustment circuit 65 for the base signal requires a phase adjustment range of a little less than n (H) (n is an integer greater than 1). This is the same in the prior art and in the present invention.

  On the other hand, the conventional super video signal phase adjustment circuit 66 has a phase adjustment range of less than 1 (H), but the phase adjustment range is sufficient for the base signal phase adjustment range n (H). Since it exists in a part in front of the weak, the actual phase adjustment range requires n (H) slightly as in the case of the phase adjustment circuit 65 for the base signal. For this reason, the conventional super video signal phase adjustment circuit 66 requires a sufficient memory capacity to hold the phase adjustment range n (H) slightly below.

  On the other hand, the super video signal phase adjustment circuit 66 according to the present invention performs phase adjustment of slightly less than 1 (H) in the first line memory 1 and shifts the phase adjustment range by n−1 (H) in a two-field memory. Alternatively, phase adjustment is divided into two stages so as to be performed by the two-frame memory 4. As a result, the phase of the super video signal can be adjusted with a line memory having a relatively small capacity as a whole.

  Further, when the phase adjustment is performed in this way, the phase of the material to be phase-adjusted (for example, the reference phase 0 (H) just) is the phase adjustment range of the first line memory ("first line memory pull-in" in FIG. If it is on the boundary of “range”, ideally the phase is adjusted. However, there is an error in reality, and it is necessary to consider the possibility of deviating from the phase adjustment range. Therefore, in the present invention, the second line memory 7 is used to cope with this error. In order to cope with this error, the second line memory 7 shifts the phase adjustment range of the first line memory 1 in units of clocks. The value to be shifted can be arbitrarily adjusted within a range of 1 (H) or less by adjusting the reset pulse applied to the second line memory 7.

  Referring to the figure, the pull-in range of the phase adjustment circuit for the base signal is slightly less than n (H) (n is an integer greater than 1), and the phase adjustment range for the super signal is less than 1 (H). Due to the delay of the second line memory 7 and the delay Nf−ΔNf + ΔNos (H) of the two-frame memory 4, the front of the base signal pulling range (near the reference phase) is included in the pulling range.

  As described above, according to the first embodiment of the present invention, the first line memory 1, the second line memory 7, and the two-field memory or the two-frame memory 4 can be realized with a relatively small capacity memory. It becomes possible. In addition, even when the phase adjustment range is less than 1 (H) or n ′ (H) (n ′ is an integer smaller than n), a desired specific phase can be included in the phase adjustment range.

  The first read address reset pulse / second write address reset pulse signal f and the second read address reset pulse signal i need only be controlled in relative phase by the control signal n. It may be a form.

FIG. 5 is a block diagram of a second embodiment of the video signal phase adjusting circuit according to the present invention.
Referring to the figure, the second read address reset pulse generation circuit 8 generates a second write address reset pulse signal i synchronized with the reference clock signal e from the reference synchronization signal d and the reference clock signal e. Thus, the corresponding pulse i is supplied to the second line memory 7, the write address generation circuit 5, and the read address generation circuit 6.

  The first read address reset pulse / second write address reset pulse generation circuit 3 applies the second read address reset pulse signal i, the control signal n supplied from the control circuit 9, and the reference clock signal e. A first read address reset pulse / second write address reset pulse signal f synchronized with the reference clock signal e is generated, and the corresponding pulse f is supplied to the first line memory 1 and the second line memory 7.

  That is, in the first embodiment, the control signal n from the control circuit 9 is input to the second read address reset pulse generating circuit 8, but in the second embodiment, the control signal n is used as the first read address reset pulse. The second write address reset pulse generation circuit 3 is also input.

  The effect of the second embodiment is the same as that of the first embodiment.

  The write address to the two-field memory or the two-frame memory 4 may be generated from the line number ID of the write data (input signal j of the two-field memory or the two-frame memory 4), and the following embodiment may be used. .

  FIG. 6 is a block diagram of a third embodiment of the video signal phase adjusting circuit according to the present invention. Referring to the figure, the write address generation circuit 11 is based on an input signal j, a read address signal l, a second write address reset pulse signal i, and a reference clock signal e of the 2-field memory or the 2-frame memory 4. A write address signal q synchronized with the clock signal e is generated and the corresponding address q is supplied to the 2-field memory or 2-frame memory 4.

FIG. 7 is a diagram showing a time chart including input / output of the 2-field memory or 2-frame memory 4 of the third embodiment. As in the case described above, for simplicity, the case of 1 frame delay is shown. In that case, it becomes a two-frame memory.
FIG. 7 is the same as FIG. 3, and data or addresses are shown in units of one horizontal period. One frame = Nf (H) (H is a horizontal period). Nf is an integer. Taking an HDTV video signal standardized by BTA S-002B as an example, Nf = 1125.

  As in FIG. 3, the read address generation circuit 6 receives the reference synchronization signal d, the reference clock signal (e in FIG. 6), and the second read address reset pulse signal (i in FIGS. 2 and 7). A read address signal (l in FIG. 7) is generated. Here, the value of the read address signal (l in FIG. 7) is Nr, and the value of Nr in a specific period is Nro. Nr has a period of 2 × Nf. Here, it is assumed that the count is incremented from 1, and the next after 2 × Nf is reset and returned to 1.

  When 0 <Nr ≦ Nf, the data of line number ID = Nr is read out. When Nf <Nr ≦ 2 × Nf, the data of line number ID = Nr−Nf is read out.

  The write address generation circuit 11 includes an input signal (j in FIG. 2), a read address signal (l in FIG. 3), a reference clock signal (e in FIG. 2), and a second read address. In response to the reset pulse signal (i in FIG. 3), a write address signal (q in FIG. 6) is generated.

  Here, it is assumed that the value of the write address signal (q in FIG. 6) is NW, and the value of Nw in a specific period same as Nro is Nwo. Nw is also a cycle of 2 × Nf. Here, it is assumed that the count is incremented from 1, and the next after 2 × Nf is reset and returned to 1. Further, the line number ID of the input signal (j in FIG. 2) of the 2-field memory or 2-frame memory 4 is LNw, and the value of LNw in a specific period same as Nro is LNwo.

  Nw = LNw−ΔNf, LNw−ΔNf + Nf, or LNw−ΔNf + 2 × Nf, and the phase difference from Nr is ≧ Nf−ΔNf and <2 × Nf−ΔNf. The value of Nw is uniquely determined by the condition of the inequality regarding the phase difference. For example, when 0 <Nr ≦ Nf and Nr ≦ LNw, Nw = LNw−ΔNf + Nf.

  From the above, it can be seen that the write address generation circuit 11 can be configured by combining an adder circuit, a comparison circuit, a selection circuit, and the like.

  When the value of the write address signal (q in FIG. 7) is Nw, the value of the write data j written to the two-frame memory 4 is DNw, and particularly the value of the corresponding data when Nw = Nwo is DNwo.

  When the value of the read address signal (l in FIG. 7) is Nr, the value of the read data m read from the two-frame memory 4 is DNr, and in particular, the value of the corresponding data when Nr = Nro is DNro.

  Here, when the write address Nw is Nro, the value DNw of data written to the 2-frame memory 4 is DNro.

  Considering the case of 0 <Nro ≦ Nf and Nro ≦ LNwo, Nwo = LNwo−ΔNf + Nf. In this case, the phase difference from writing to reading Nwo−Nro = (LNwo−ΔNf + Nf) −Nro = Nf−ΔNf + (LNwo−Nro), which corresponds to the case of ΔNos = (LNwo−Nro) in FIG.

  Here, since (LNwo-Nro) corresponds to the phase difference between the write data and the read data in the 2-frame memory 4, the delay of 1 (H) unit applied to the frame memory controlled by the control circuit in the circuit of FIG. In the circuit of FIG. 6, the adjustment is automatically performed based on the phase difference of each line.

  In other cases, the same consideration shows that the circuit of FIG. 6 automatically adjusts the delay of the two-frame memory 4 based on the phase difference in units of lines. Therefore, in the case of the circuit of FIG. 6, the phase difference in units of lines is automatically adjusted.

  According to the third embodiment, the write address generation circuit 11 can be configured by combining an adder circuit, a comparison circuit, a selection circuit, and the like. In addition, it is possible to automatically adjust the phase difference in units of lines.

  In the circuit of the third embodiment shown in FIG. 6, when the 2-frame memory 4 is replaced with a 1-frame memory and the write address q is Nw = LNw−ΔNf or LNw−ΔNf + Nf, the phase adjustment without frame delay is performed. It becomes a circuit.

  According to the fourth embodiment, even when there is no frame delay, the second line memory 7 can perform phase adjustment for absorbing an error from the reference phase 0 (H).

  FIG. 8 is a block diagram of a fifth embodiment of the video signal phase adjusting circuit according to the present invention. The configuration of this embodiment is different from the configuration of the first embodiment (see FIG. 1) in that the second line memory 7 is deleted. Accordingly, the first read address reset pulse and second write address reset pulse generation circuit 3 in the first embodiment is changed to the read address reset pulse generation circuit 3, and the second read address reset pulse generation circuit 8 and The control circuit 9 is deleted. Other configurations are the same as those of the first embodiment.

  According to the fifth embodiment, even when the second line memory 7 is deleted, the first line memory 1 and the two-field memory or the two-frame memory 4 share the phase adjustment in two stages. As a result, it is possible to adjust the phase of the super video signal with a relatively small memory.

  As the sixth embodiment, the connection order of the first line memory 1, the second line memory 7 and the two-field memory or the two-frame memory 4 in the above-described embodiment (see FIGS. 1, 5, 6, and 8) is arbitrarily set An exchanged configuration is also possible. In this case, the address reset pulse generation circuits of the line memories 1 and 7 are appropriately separated or added. The effect is the same as in the previous embodiment.

  FIG. 9 is a block diagram of a seventh embodiment of the video signal phase adjusting circuit according to the present invention. The configuration of this embodiment is different from the configuration of the first embodiment (see FIG. 1) in that a fixed delay circuit 21 is inserted between the first line memory 1 and the second line memory 7, and the second The fixed delay circuit 22 is inserted between the line memory 7 and the two-field memory or the two-frame memory 4, and the other configuration is the same as that of the first embodiment. Also in this case, the address reset pulse generation circuits of the line memories 1 and 7 are appropriately separated or added.

  According to the seventh embodiment, a fixed delay circuit can be further added.

1 is a configuration diagram of a first embodiment of a video signal phase adjustment circuit according to the present invention; FIG. It is a time chart of the signal from the input of the 1st line memory 1 of the 1st example to the output of the 2nd line memory. FIG. 2 is a time chart including input / output signals of the 2-field memory or 2-frame memory 4 in FIG. It is a figure which shows an example of the phase chart of the switcher which used the phase adjustment circuit of the video signal which concerns on this invention for the phase adjustment circuit of the super video signal. It is a block diagram of 2nd Example of the phase adjustment circuit of the video signal which concerns on this invention. It is a block diagram of 3rd Example of the phase adjustment circuit of the video signal which concerns on this invention. It is a figure which shows the time chart including the input / output of 2 field memory or 2 frame memory 4 of 3rd Example. It is a block diagram of 5th Example of the phase adjustment circuit of the video signal which concerns on this invention. It is a block diagram of 7th Example of the phase adjustment circuit of the video signal which concerns on this invention. It is a block diagram of an example of the conventional production switcher or sending switcher. FIG. 11 is a circuit diagram from the phase adjustment circuit 66 to the field memory or frame memory 74 in FIG. 10, or a circuit diagram from the phase adjustment circuit 67 to the field memory or frame memory 75.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st line memory 2 1st write address reset pulse generation circuit 3 1st read address reset pulse and 2nd write address reset pulse generation circuit 4 2 field memory or 2 frame memory 5 Write address generation circuit 6 Read address Generation circuit 7 Second line memory 8 Second read address reset pulse generation circuit 8
9 Control Circuit 21 Fixed Delay Circuit 22 Fixed Delay Circuit

Claims (12)

A phase adjustment circuit for synchronizing an input digital video signal with a reference clock, phase adjustment, and field delay or frame delay of a video signal,
A first line memory for synchronizing and phase adjusting the input digital video signal to the reference clock;
A second line memory that gives a delay of one horizontal period or less to the output of the first line memory;
A video signal phase adjusting circuit comprising: a field or frame memory that gives a delay of an arbitrary integral multiple of one horizontal period to the output of the second line memory. The delay given by the second line memory is the output time of the read address reset pulse signal of the first line memory and the write address reset pulse signal of the second line memory and the read address of the second line memory. 2. The video signal phase adjusting circuit according to claim 1, wherein the phase adjusting circuit is equal to a time difference from an output time of the reset pulse signal. Including a control circuit,
3. The video signal phase adjusting circuit according to claim 2, wherein the control circuit sets the time difference in units of one clock of the reference clock. 4. The video signal phase adjusting circuit according to claim 2, wherein the control circuit sets the time difference by controlling an output time of a read address reset pulse signal of the second line memory. 4. The control circuit sets the time difference by controlling an output time of a read address reset pulse signal of the first line memory and a write address reset pulse signal of the second line memory. The phase adjustment circuit of the described video signal. A read address for the field or frame memory is generated based on a reference synchronization signal, the reference clock, and a read address reset pulse signal of the second line memory,
A write address for the field or frame memory is generated based on the read address, the reference clock, a read address reset pulse signal of the second line memory, and a control signal from the control circuit. The video signal phase adjusting circuit according to claim 3. A read address for the field or frame memory is generated based on a reference synchronization signal, the reference clock, and a read address reset pulse signal of the second line memory,
The write address for the field or frame memory is generated based on the read address, the reference clock, the read address reset pulse signal of the second line memory, and the line number ID of the write data for the field or frame memory. 6. The video signal phase adjusting circuit according to claim 3, wherein the video signal phase adjusting circuit is a video signal phase adjusting circuit. 8. The video signal phase adjustment circuit according to claim 1, wherein the field or frame memory is a two-field or two-frame memory. 8. The video signal phase adjusting circuit according to claim 7, wherein the field or frame memory is one field or one frame memory. 10. The video signal phase adjusting circuit according to claim 7, wherein the second line memory is deleted. 10. The video signal phase adjusting circuit according to claim 1, wherein the connection order of the first line memory, the second line memory, the field or the frame memory is changed. A first fixed delay circuit is inserted between the first line memory and the second line memory, and a second fixed delay circuit is inserted between the second line memory and the field or frame memory. 12. The video signal phase adjusting circuit according to claim 10, wherein the phase adjusting circuit is inserted.

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