JP2012016232A - Dead time compensation system of pwm power conversion apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a delay error TDLY by reducing an error (phase difference) between a PWM gate command before dead time compensation and a phase voltage output after dead time compensation.SOLUTION: A dead time compensation unit 30 increases or reduces the voltage value of a PWM voltage command Vcmd_U by an amount equal to a dead time compensation Vcmp_U which is determined depending on a phase difference between PWM gate command Gate_U and PWM output Vce_U. A compensated PWM voltage command, Vcmd_U', is then converted into a PWM gate command by a PWM waveform generation unit 20, whereby an error (phase difference) between the PWM gate command before dead time compensation and a phase voltage output after dead time compensation is reduced.

Description

  The present invention relates to a dead time (short-circuit prevention period) compensation device that is inserted into a drive signal of a main circuit switching element of a PWM power converter, and more particularly to compensation of an output voltage error caused by a switching delay due to insertion of a dead time.

  In power converters such as inverters and converters using power switching elements such as transistors and IGBTs, the main circuit has two switching elements for the DC power supply (main circuit power supply) (the P side arm and the N side of the DC link voltage). Arms) are connected in series, and control is performed to alternately turn on (close) these two switching elements. At this time, there is a time delay in the actual switching operation with respect to the switching command, and if the N-side arm is still in the ON state when the P-side arm is turned on, the power supply P of the main circuit DC link unit is passed through both switching elements. The side and the N side are short-circuited, and the switching element may be damaged.

  In order to avoid the occurrence of this short circuit, a dead time generation circuit is provided that inserts a dead time (short circuit prevention period) into the ON / OFF control signal (drive signal) of the switching element. During this dead time period, both of the two switching elements connected in series are turned off. Thereby, even if there is a time delay in the switching operation of the two switching elements, a power supply short circuit can be prevented.

  Here, a switching delay occurs due to the dead time inserted in the drive signals of the two switching elements, and a voltage error is generated between the output voltage command and the output voltage due to the switching delay. A dead time compensation circuit is also added.

  FIG. 6 shows a configuration example of a PWM inverter to which a dead time compensation circuit is added. The PWM inverter 10 having the DC voltage source PN as an input is configured as a three-phase bridge circuit in which two switching elements such as IGBTs are connected in series with each phase, and the switching elements U to Z are gate signals GU, GX, GV. , GY, GW, and GZ are controlled to be turned on and off to obtain a three-phase output in which the voltage and frequency are controlled and supplied to the load.

  Here, the inverter 10 is controlled by the PWM method. The three-phase voltage commands Vcmd_U, Vcmd_V, and Vcmd_W are compared with the carrier wave carrier by the PWM waveform generator 20 and converted into three-phase gate commands Gate_U, Gate_V, and Gate_W of the PWM waveform. Further, the dead time generation unit 40 adds gate signals GU, GX, GV with dead time so that a certain short-circuit prevention period can be inserted between the on and off of the upper and lower arms of the inverter (for example, in the case of U and X phases). , GY, GW, and GZ are generated and output.

  In an inverter to which such a dead time is added, the presence of the dead time causes the output current waveform to be distorted as shown in FIG. In order to prevent this influence, a dead time compensation unit 30 is added to improve the output current waveform. The dead time compensation unit 30 obtains a dead time compensation output signal that compensates for a voltage error between the PWM output command and the PWM output voltage detection signal.

  In Patent Document 1 or Patent Document 2, the phase of each phase voltage Vce_U, Vce_V, Vce_W of the inverter is detected by the Vce (output voltage) detection unit 50, and the on-time and off-time with the three-phase gate commands Gate_U, Gate_V, Gate_W. Error Vce_DLY is detected, and gate signals Gate_U ′, Gate_V ′, and Gate_W ′ (gate signals after dead time compensation) are obtained by adding the counter value only in a section where there is an error.

  These block diagrams are shown in FIG. 7, and the time chart is shown in FIG. 7 and 8 show the case of only the U phase as an example. Since the other phase is the same as the U phase, it is omitted here.

  In FIG. 7, a counter that measures an on-time error is ON_COUNT, and a counter that measures an off-time error is OFF_COUNT. ON_COUNT and OFF_COUNT indicate a 1-bit counter (configured by one full adder circuit FA and one flip-flop for temporary storage) in the figure, but in actuality, an N-bit counter configuration in which 1-bit counters are connected in N stages cascaded. To do. The operation of each counter at this time is expressed by the following equation.

  A flag when ON_COUNT exceeds a certain value is Max_ON, and a flag when OFF_COUNT exceeds a certain value is Max_OFF. The gate command Gate_U ′ after the dead time compensation is generated by using the SR flip-flop F / F with the set and reset signals set to Max_ON and Max_OFF, respectively.

JP 7-95773 A JP-A-8-14362

  As shown in FIG. 8, in Patent Documents 1 and 2, the gate command Gate_U and the on-time and off-time phase delay Vce_DLY are reduced by the dead time compensation circuit, but in phase with the gate command Gate_U ′ after the dead time compensation. A delay error TDLY remains between the output voltage Vce_U and the output voltage Vce_U. This is always in principle because the error of the phase output voltage Vce_U is measured with reference to the gate command Gate_U.

  The occurrence of the delay error TDLY becomes a factor that increases the limit time of the minimum on-time of the PWM pulse, so that a thin PWM pulse cannot be output, and as a result, the upper limit of the output voltage is lowered.

  Further, since the delay error TDLY is a dead time in the current control of the inverter, it is desirable that the delay error TDLY is not present when the inverter is used for a high-response application.

  An object of the present invention is to provide a dead time compensation device for a power converter that shortens a delay error TDLY by reducing an error (phase difference) between a PWM gate command before dead time compensation and a phase voltage output after dead time compensation. It is to provide.

  In order to solve the above-described problem, the present invention increases or decreases the voltage value of the PWM voltage command by a dead time compensation amount obtained according to the phase difference between the PWM gate command and each phase PWM output, and the PWM voltage command after this compensation Is converted into a PWM gate command to reduce the error (phase difference) between the PWM gate command before dead time compensation and the phase voltage output after dead time compensation. .

(1) A dead time of a predetermined time is inserted into the three-phase drive signal of the main circuit switching element of the PWM power converter, and the PWM output voltage corresponding to the PWM gate command generated by the switching delay of the main circuit switching element due to the dead time insertion A PWM power conversion device dead time compensation device that compensates for errors by a dead time compensation circuit,
The dead time compensation circuit increases or decreases the voltage value of the PWM voltage command by the amount of dead time compensation determined according to the phase difference between the PWM gate command and each phase PWM output, and the compensated PWM voltage command is used as the PWM gate command. It is characterized by comprising means for reducing an error (phase difference) between the PWM gate command before dead time compensation and the phase voltage output after dead time compensation by conversion.

(2) The dead time compensation circuit is:
A circuit for measuring a phase difference between a PWM gate command generated based on a PWM voltage command and a PWM phase output as an on-time error time and an off-time error time,
A circuit for converting the measured values of the on-time error time and the off-time error time into the same units as the PWM voltage command;
A circuit for adding / subtracting the measured values of the converted on-time error time and off-time error time to / from the PWM voltage command according to the next on / off polarity of the PWM waveform;
It is provided with.

  As described above, according to the present invention, the voltage value of the PWM voltage command is increased / decreased by the dead time compensation amount determined according to the phase difference between the PWM gate command and each phase PWM output. By converting to the gate command, the error (phase difference) between the PWM gate command before the dead time compensation and the phase voltage output after the dead time compensation is reduced, so that the delay error TDLY can be shortened. By shortening the delay error TDLY, it is possible to output a thin PWM pulse, and there is an effect that the control dead time of the PWM inverter is reduced.

The block diagram of PWM inverter which added the dead time compensation circuit (embodiment). The circuit block diagram of the dead time compensation part 30 (embodiment). Each part time chart by dead time compensation (embodiment). The waveform diagram of each part before and after compensation for dead time (embodiment). Current waveform diagram before and after dead time compensation. The block diagram of the PWM inverter which added the dead time compensation circuit (conventional). The circuit block diagram of the dead time compensation part 30 (conventional). Time chart of each part by dead time compensation (conventional).

(1) Configuration FIG. 1 is a configuration diagram of a PWM inverter to which a dead time compensation circuit is added. 6 differs from FIG. 6 in that the voltage values of the PWM voltage commands Vcmd_U, Vcmd_V, and Vcmd_W are increased or decreased by a dead time compensation amount determined according to the phase difference between the PWM gate command and each phase PWM output. By converting the PWM voltage command into PWM gate commands Gate_U, Gate_V, and Gate_W, an error (phase difference) between the PWM gate command before dead time compensation and the phase voltage output after dead time compensation is reduced.

  In FIG. 1, the carrier generation unit 60 outputs a triangular carrier wave Carrier having a frequency Fc [Hz] and a single amplitude Ac, and simultaneously outputs Carrier maximum and minimum flags Carrier_top and Carrier_btm (see FIG. 3). ). The PWM waveform generation unit 20 compares the triangular carrier wave carrier and the voltage commands V_cmd_U ′, V_cmd_V ′, and Vcmd_W ′ after the dead time compensation, and generates gate commands Gate_U, Gate_V, and Gate_W. The dead time compensation by the dead time compensation unit 30 will be described later.

  The dead time generation unit 40 adds a predetermined dead time to the gate commands Gate_U, Gate_V, and Gate_W to prevent a short circuit between the upper and lower arms of the inverter 10 and generates final gate commands GU, GX, and the like. Compensation of the voltage command by the dead time compensation unit 30 is expressed by the following equation.

  Here, Vcmd_U, Vcmd_V, and Vcmd_W are three-phase voltage commands before dead time compensation, and Vcmp_U, Vcmp_V, and Vcmp_W are dead time compensation voltage commands.

(2) Action / Operation In the conventional technique, the dead time compensation is performed using the gate command after the PWM comparison result. However, as described above, this method always causes a delay error. In the present embodiment, the delay error is eliminated by compensating the PWM voltage command before generating the PWM waveform so that the PWM gate command is not delayed compared to before the compensation. In the following description, only the U phase will be described, but the other phases are also the same as the U phase, and thus the description thereof is omitted.

  FIG. 2 shows a circuit configuration of the dead time compensator 30, and FIG. 3 shows a time chart of each part. First, the dead time compensator 30 compares the phase of the PWM gate command Gate_U generated by the PWM waveform generator 20 with the phase of the U-phase output voltage Vce_U detected by the Vce detector 50. By this comparison, the phase difference between the PWM gate command Gate_U and the U-phase output voltage Vce_U is measured as an on-time error time Vce_DLY1 and an off-time error time Vce_DLY2. A counter that operates only for the on-time error time at this time is ON_COUNT, and a counter that operates only for the off-time error time is OFF_COUNT. As in FIG. 6, these counters are composed of an N-bit full adder circuit FA and a flip-flop.

  These measured values of the on-time error time and off-time error time need to be converted to the same unit as the voltage command Vcmd_U in order to be used for dead time compensation. If the value to be added at the time of error generation is the conversion gain clk_pwm, these counters are added per time Tclk [s], and therefore can be converted into PWM units while measuring the error time. The following formula shows the definition of clk_pwm as one input of the full adder circuit FA.

  ON_COUNT is reset after Carrier_top, and OFF_COUNT is reset after Carrier_btm. ON_COUNT and OFF_COUNT are N-bit counters, and the adder in the counter is composed of an N-bit full adder circuit FA and operates as shown in the following equation.

  The operation when measuring the on-time and off-time delay errors is as shown in the time chart of FIG.

  The dead time compensation circuit 30 superimposes the measured counter value on the voltage command to compensate for the dead time. Since there is a difference between the on-time error and the off-time error depending on the characteristics of the IGBT and the flow path depending on the current polarity, compensation is performed individually. Vce detection is detected with a delay relative to the PWM command. In order to compensate for the on-time, the rise of the gate command Gate_U may be advanced. In order to advance the rise of the gate command, the voltage command may be increased while the carrier carrier is descending. Further, in order to compensate for the off time, the fall of the gate command Gate_U may be advanced. In order to advance the fall of the gate command, the voltage command may be decreased while the carrier carrier is rising.

  Therefore, the measured values of the converted on-time error time and off-time error time are added to or subtracted from the PWM voltage command in accordance with the next on / off polarity of the PWM waveform. For example, the ON_COUNT value is added to Vcmd_U at Carrier_top to compensate for on-time, and OFF_COUNT is subtracted from Vcmd_U at Carrier_btm to compensate for off-time. This compensation relationship is shown in FIG. Accordingly, the voltage compensation value V_cmp_U is expressed by the following equation.

  The gate command before and after the compensation shown in FIG. 4 will be described. The waveform of Gate_U is an ideal output voltage waveform. If there is no change in the on-time and off-time errors for each carrier cycle, the gate command Gate_U before compensation and the detected phase voltage Vce_U after compensation completely coincide with each other. Time compensation is possible. Even if there is a change, the delay error is much smaller than in the conventional technique.

  FIG. 5 shows current waveforms when an inductive load is actually connected to the inverter of the embodiment and compensation is applied. By the dead time compensation shown in the embodiment, it can be confirmed that the current distortion (6f component) is reduced in the present embodiment as shown in FIG. 5B, compared to the conventional FIG. It was.

(3) Effects According to the dead time compensation by the present mobile phone, there are the following effects.

  The error between the PWM command Gate_U before compensation and the detected phase voltage Vce_U after compensation can be made substantially zero.

  Since the dead time TDLY due to dead time compensation is eliminated, the limit of the minimum on-pulse time is reduced. By reducing the limitation on the minimum on-pulse time, a narrower PWM pulse can be output. If this narrower PWM pulse can be output, the maximum output voltage of the power converter increases.

  -Since the dead time TDLY due to dead time compensation is eliminated, the control dead time of the PWM inverter is reduced. By reducing the dead time of the PWM inverter, the current control and frequency control responses are improved.

  -The dead time compensation reduces the 6f component (current distortion) of the output current.

DESCRIPTION OF SYMBOLS 10 PWM inverter 20 PWM waveform generation part 30 Dead time compensation part 40 Dead time generation part 50 Vce (output voltage) detection part 60 Carrier generation part

Claims (2)

A dead time of a predetermined time is inserted into the three-phase drive signal of the main circuit switching element of the PWM power converter, and the error of the PWM output voltage with respect to the PWM gate command generated by the switching delay of the main circuit switching element due to this dead time insertion A dead time compensator for a PWM power converter that compensates with a time compensator,
The dead time compensation circuit increases or decreases the voltage value of the PWM voltage command by the amount of dead time compensation determined according to the phase difference between the PWM gate command and each phase PWM output, and the compensated PWM voltage command is used as the PWM gate command. A dead time compensation device for a PWM power converter characterized by comprising means for reducing an error (phase difference) between a PWM gate command before dead time compensation and a phase voltage output after dead time compensation by conversion . The dead time compensation circuit is:
A circuit for measuring a phase difference between a PWM gate command generated based on a PWM voltage command and a PWM phase output as an on-time error time and an off-time error time,
A circuit for converting the measured values of the on-time error time and the off-time error time into the same units as the PWM voltage command;
A circuit for adding / subtracting the measured values of the converted on-time error time and off-time error time to / from the PWM voltage command according to the next on / off polarity of the PWM waveform;
The dead time compensator for a PWM power converter according to claim 1, comprising:

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