JP2016208559A - Parallel operation method and parallel operation device for pwm power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a cross flow caused by a difference in switching properties in rise and fall of a switching element.SOLUTION: In an up cross flow control part 9a, an up cross flow compensation value Vccc_up is calculated based on a detection value of a cross current Ic during a period in which a triangular carrier Carrier increases from a lower limit value to an upper limit value. In a down cross current control part 9b, a down cross current compensation value Vccc_down is calculated based on a detection value of the cross current Ic during a period in which the triangular carrier Carrier decreases from the upper limit value to the lower limit value. During the period in which the triangular carrier Carrier decreases from the upper limit value to the lower limit value, the up cross current compensation value Vccc_up is superposed on a voltage command Vcmd' of each of PWM power converters. During the period in which the triangular carrier Carrier increases from the lower limit value to the upper limit value, the down cross current compensation value Vccc_down is superposed on the voltage command Vcmd' of each of PWM converters.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a parallel operation method and a parallel operation apparatus for PWM power converters, and more particularly to control for suppressing cross current.

  FIG. 7 shows a parallel operation device in which PWM power converters (three-phase inverters in FIG. 7) of Patent Document 1 are arranged in parallel. FIG. 7 shows a configuration in which a cross current compensation and a dead time compensation are added to the inverter, and is represented by a single line diagram for the sake of explanation.

  The inputs of the inverters INV1 and INV2 are DC voltage sources PN, which are connected in parallel. The outputs of the inverters INV1 and INV2 are connected by an interphase reactor L_mut, and are connected to a load from an intermediate tap of the interphase reactor L_mut.

  If the output currents of the inverters INV1 and INV2 are I1 and I2, the output current supplied to the load is Io. Here, the detection current used for current control is Idet. The cross current Ic is represented by the deviation between the output current I1 and the output current I2. The following equations (1) and (2) show the relationship among the output currents I1, I2, Io, the detection current Idet, and the cross current Ic.

  In a current controller ACR (Automatic Current Regulator), current control is performed so that the detected current Idet follows the current command Icmd, and a voltage command Vcmd is generated.

  The adder 5 adds a voltage command Vcmd and a dead time compensation amount Vdtc described later to generate a voltage command Vcmd 'after dead time compensation. The adder 6a adds a voltage command Vcmd 'after dead time compensation and a voltage command Vccc for cross current compensation (hereinafter referred to as a cross current compensation value) Vccc, which will be described later, and outputs a voltage command Vcmd1' for the inverter INV1. Further, the subtractor 6b subtracts the cross current compensation value Vccc from the voltage command Vcmd 'after the dead time compensation, and outputs the voltage command Vcmd2' of the inverter INV2.

  The PWM controllers PWM1 (Pulse Width Modulation) and PWM2 respectively compare the voltage command Vcmd1 'of the inverter INV1 and the voltage command Vcmd2' of the inverter INV2 with the triangular carrier wave carrier to generate gate commands Gate1 and Gate2. The gate commands Gate1 and Gate2 are compensated by a dead time compensation unit DTC (Dead Time Compensation).

  The Vce detection unit 1 detects the phase voltages V1 and V2 of the inverter INV1 and the inverter INV2, and outputs insulated detection phase voltages Vce1 and Vce2. The dead time compensation unit DTC detects an on-time and off-time error between the gate commands Gate1 and Gate2 and the detection phase voltages Vce1 and Vce2, performs compensation, and outputs a dead time compensation amount Vdtc. Since there are two inverters, there are two types of errors to detect. The dead time compensation amount Vdtc used for dead time compensation is the average of detection errors of the two inverters INV1 and INV2.

  Further, the cross current control time Tccc is calculated by the PI control of the cross current control unit (Balance ACR) 4, and the cross current compensation value Vccc in the same unit as the voltage command Vcmd is output based on the cross current control time Tccc.

  The dead time generation units DT1 and DT2 receive the gate commands Gate1 and Gate2, and output switching commands G1_U, G1_L, G2_U, and G2_L having a predetermined dead time Td. The switching commands G1_U, G1_L, G2_U, and G2_L are switching commands for the inverter INV1 and the inverter INV2, and the inverters INV1 and INV2 are operated by turning on and off the switching elements in the inverters INV1 and INV2 according to the commands.

JP 2012-244673 A JP 2012-016232 A

  In Patent Document 1, in the cross current control unit 4, based on the cross current Ic between the PWM power converters INV 1 and INV 2, the cross current compensation value Vccc in the same unit as the voltage command Vcmd common to the PWM power converters INV 1 and INV 2 is obtained. This cross current compensation value Vccc is added to one voltage command Vcmd1 ′ according to the value of the cross current Ic, and subtracted from the other voltage command Vcmd2 ′.

  However, a switching element such as an IGBT has different switching characteristics at the time of rising and at the time of falling. The switching characteristics are various characteristics related to turn-on and turn-off of the switching element with respect to the gate commands Gate1 and Gate2 (delay time required for turn-on and turn-off, voltage gradient, etc.).

  The rise of the gate commands Gate1 and Gate2 indicates that the gate commands Gate1 and Gate2 are switched from OFF to ON, and the fall of the gate commands Gate1 and Gate2 indicates that the gate commands Gate1 and Gate2 are switched from ON to OFF. The values of the gate commands Gate1 and Gate2 are defined as 1 when the gate commands Gate1 and Gate2 are ON, and the value is defined as 0 when the gate commands Gate1 and Gate2 are OFF.

  Therefore, since the cross current compensation control according to the polarity of on / off of the PWM control is not performed, the difference between the switching characteristics at the turn-on time of the switching element and the switching characteristics at the turn-off time with respect to the gate commands Gate1 and Gate2 is caused. There is a problem that the cross current compensation value Vccc cannot be controlled to an optimum value.

  FIG. 8 shows a time chart of the gate commands Gate1 and Gate2 and the cross current Ic during the cross current control in the conventional method. Although dead time is originally added, the present invention relates to cross current control, and therefore the dead time will be omitted and described in a simplified manner. In the cross current, the direction from the inverter INV1 to the inverter INV2 is positive.

  As shown in FIG. 8, the cross current can be compensated for most of the time, but since the switching characteristics are different when the switching element is turned on and off, the cross current compensation value Vccc cannot be controlled to the optimum value. As a result, the voltage command Vcmd1 ′ of the inverter INV1 and the voltage command Vcmd2 ′ of the inverter INV2 are not optimum values, and as a result, the rise timing and fall timing of the gate command Gate1 of the inverter INV1 and the gate command Gate2 of the inverter INV2, respectively. There is a problem that a difference occurs in that the effect of suppressing cross current is reduced.

  As described above, in the parallel operation method and parallel operation apparatus of the PWM power converter, the cross current generated due to the difference in switching characteristics at the time of rising (turn-on) and falling (at turn-off) of the switching element. It becomes a problem to suppress this.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is PWM power in which two PWM power converters are connected in parallel and the outputs of the two PWM power converters are connected by an interphase reactor. A parallel operation device for a converter, which outputs a triangular carrier wave for generating a gate command, and a period during which the triangular carrier wave is decreasing from an upper limit value to a lower limit value, or from a lower limit value to an upper limit value. Triangular carrier determination unit that determines whether the period is rising, and the detected value of the cross current is input to the falling current control unit while the triangular carrier is decreasing from the upper limit value to the lower limit value, and the triangular carrier wave is the lower limit value. Based on the first selection unit that rises the detected value of the cross current during the period rising from the upper limit to the upper limit value and inputs it to the cross current control unit, and the detected value of the cross current during the period when the triangular carrier wave increases from the lower limit value to the upper limit value , Rising cross current compensation A rising cross current control unit that calculates a falling cross current compensation value based on a detected value of the cross current during a period when the triangular carrier wave is decreasing from the upper limit value to the lower limit value, and a triangular carrier wave The rising cross current compensation value calculated by the rising cross current control unit is output during the period when the upper limit value is decreasing to the lower limit value, and the falling cross current control unit is calculated when the triangular carrier wave is increasing from the lower limit value to the upper limit value. The second selection unit that outputs the falling cross current compensation value, the adder that adds the value output by the second selection unit to the voltage command of one PWM power converter, and the voltage command of the other PWM power converter And a subtractor for subtracting a value output from the two selection unit.

  According to the present invention, in a parallel operation method and a parallel operation device of a PWM power converter, a cross current generated due to a difference in switching characteristics at the time of rising (turn-on) and falling (at turn-off) of a switching element is suppressed. It becomes possible to do.

The block diagram which shows the parallel operation apparatus of the PWM power converter in Embodiment 1. FIG. FIG. 3 is a block diagram illustrating a cross current control unit according to the first embodiment. The time chart which shows a triangular carrier wave, a gate rising signal, and a gate falling signal. Time chart showing gate command and cross current. FIG. 5 is a block diagram illustrating a cross current control unit according to a second embodiment. FIG. 9 is a block diagram illustrating a cross current control unit according to a third embodiment. The block diagram which shows the parallel operation apparatus of the conventional PWM power converter. The time chart which shows the conventional gate command and cross current.

  Embodiments 1 to 3 of the PWM power converter parallel operation method and parallel operation device according to the present invention will be described below in detail with reference to FIGS.

[Embodiment 1]
In the conventional method, since the rising time and falling time of the gate commands Gate1 and Gate2 are not distinguished, the cross current compensation value Vccc cannot be controlled to the optimum value. Therefore, in the first embodiment, the compensation control is performed by distinguishing between the rising time and the falling time of the gate commands Gate1 and Gate2.

  FIG. 1 shows a parallel operation apparatus for PWM power converters according to the first embodiment. The parallel operation apparatus of the PWM power converter in the first embodiment is the same as that of FIG. 7 except for the triangular carrier wave determination unit 3 and the cross current control unit 4a. A triangular carrier Carrier for generating gate commands Gate 1 and Gate 2 output from the carrier generation unit 2 is input to the triangular carrier determination unit 3. The triangular carrier wave determination unit 3 determines whether the triangular carrier wave carrier is decreasing from the upper limit value to the lower limit value or rising from the lower limit value to the upper limit value, and the gate rising signal Gate_up_signal and the gate falling signal Gate_down_signal. Is generated and input to the cross current control unit 4a. The cross current control unit 4a according to the first embodiment performs the cross current control by using the gate rising signal Gate_up_signal and the gate falling signal Gate_down_signal to distinguish the rising time and the falling time of the gate.

  FIG. 2 shows a block diagram of the cross current control unit 4a in the first embodiment. As shown in FIG. 2, the cross current control unit 4a includes a cross current control unit for gate rising (hereinafter referred to as a rising cross current control unit) 9a and a cross current compensation control unit for gate falling (hereinafter referred to as falling cross current control). 9b) are provided for exclusive use.

  Based on the gate rising signal Gate_up_signal or the gate falling signal Gate_down_signal, it is determined whether the detected value of the cross current Ic is input to the rising cross current control unit 9a or the falling cross current control unit 9b.

  FIG. 3 is a time chart showing the gate rising signal Gate_up signal and the gate falling signal Gate down signal. The gate commands Gate1 and Gate2 output the ON signal 1 when the voltage command (the voltage command Vcmd1 ′ of the inverter INV1 in FIG. 1 or the voltage command Vcmd2 ′ of the inverter INV2 in FIG. 1) is larger than the triangular carrier wave carrier, and is smaller than the triangular carrier carrier. In this case, an OFF signal 0 is output.

  The gate commands Gate1 and Gate2 change from 1 to 0 during the period in which the triangular carrier wave carrier rises from the lower limit value to the upper limit value. Conversely, the gate commands Gate1 and Gate2 change from 0 to 1 during the period in which the triangular carrier wave carrier decreases from the upper limit value to the lower limit value.

  The triangular carrier wave determination unit 3 outputs a gate rising signal Gate_up_signal during a period from when the triangular carrier wave carrier reaches the upper limit value until it reaches the lower limit value. In this period, the switch (first selection unit) SW1 and the switch (second selection unit) SW2 in FIG. 2 are each connected to the “1” side. The cross current Ic detected during the period when the gate rising signal Gate_up_signal is output is the detected value of the cross current Ic generated due to the previous gate update timing (the timing at which the gate commands Gate1 and Gate2 change from 1 to 0). It is. Therefore, during this period, the switch SW1 is connected to the “1” side, and the falling cross current control unit 9b calculates the falling cross current compensation value Vccc_down based on the detected value of the cross current Ic.

  On the other hand, when the switch SW2 is connected to the “1” side, the rising cross current compensation value Vccc_up calculated by the rising cross current control unit 9a when the gate falling signal Gate_down_signal is output is shown in FIG. The cross current compensation value Vccc is the final output of the cross flow control unit 4a. This cross current compensation value Vccc is superimposed on the voltage command Vcmd 'after dead time compensation.

  During the period in which the gate falling signal Gate_down_signal is output (that is, the period in which the gate rising signal Gate_up_signal is not output), the switches SW1 and SW2 are connected to the “0” side, and the rising lateral current control unit 9a Based on the detected value, the rising cross current compensation value Vccc_up is calculated. On the other hand, since the switch SW2 is connected to the “0” side, the falling cross current compensation value Vccc_down calculated by the falling cross current control unit 9b when the gate falling signal Gate_up_signal is output is used as the cross current compensation value. Output as Vccc.

  Thus, according to the state of the triangular carrier wave carrier, two types of rising cross current compensation value Vccc_up and falling cross current compensation value Vccc_down are calculated, and either the rising cross current compensation value Vccc_up or the falling cross current compensation value Vccc_down is selected. And superimposed on the voltage command Vcmd ′ after the dead time compensation.

  By performing the processing as described above, since the cross current Ic can be compensated in consideration of the rise and fall of the gate commands Gate1 and Gate2, there is no deviation in the compensation amount.

  FIG. 4 is a time chart showing the gate commands Gate1 and Gate2 and the cross current Ic in the first embodiment.

  In the period in which the triangular carrier wave carrier is decreasing (period in which the gate rising signal Gate_up_signal is output) and in the period in which the triangular carrier wave carrier is increasing (while the gate rising signal Gate_up_signal is not output), the cross current compensation value Vccc Therefore, the values of the voltage commands Vcmd1 ′ and Vcmd2 ′ of the inverters INV1 and INV2 in both periods are different.

  By this operation, as shown in FIG. 4, control is performed so that the rising and falling timings of the gate commands Gate1 and Gate2 coincide with each other, and the cross current is suppressed.

  As described above, according to the first embodiment, it is possible to suppress the cross current generated due to the difference in switching characteristics between the rising time (turn-on time) and the falling time (turn-off time) of the switching element. .

[Embodiment 2]
FIG. 5 is a block diagram showing the cross current control unit 4b in the second embodiment. In the second embodiment, the switches SW1 and SW2 are switched using a gate falling signal Gate_down_signal. In a period in which the gate falling signal Gate_down_signal is output, the switch SW1 and the switch SW2 in FIG. 5 are each connected to the “1” side. Others are the same as in the first embodiment.

  The cross current Ic detected during this period is a detected value of the cross current Ic generated due to the timing of the previous gate update. Therefore, the detection value of the cross current Ic is input to the rising cross current control section 9a by connecting the switch SW1 to the “1” side during the period when the gate falling signal Gate_down_signal is output. The rising cross current control unit 9a calculates the rising cross current compensation value Vccc_up based on the detected value of the cross current Ic.

  On the other hand, by connecting the switch SW2 to the “1” side, when the gate rising signal Gate_up_signal is output, the falling cross current compensation value Vccc_down calculated by the falling cross current control unit 9b becomes the cross current compensation value Vccc. It becomes. This cross current compensation value Vccc is superimposed on the voltage command Vcmd 'after dead time compensation.

  The operation during the period when the gate rising signal Gate_up_signal is output (that is, the period when the gate falling signal Gate_down_signal is not output) is the same.

  As described above, according to the second embodiment, the same operational effects as those of the first embodiment can be obtained.

[Embodiment 3]
FIG. 6 is a block diagram showing the cross current control unit 4c in the third embodiment. In the third embodiment, the gate falling signal Gate_down_signal is used as the determination signal for the switch SW1, and the gate rising signal Gate_up_signal is used as the determination signal for the switch SW2. Others are the same as those in the first and second embodiments.

  Even if the determination signals of the switch SW1 and the switch SW2 are reversed, the same can be implemented. Thereby, there exists an effect similar to Embodiment 1,2.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

3 ... Triangular carrier wave determination unit 4a, 4b, 4c ... Cross current control unit 9a ... Rising cross current control unit 9b ... Falling cross current control unit INV1, INV2 ... PWM power converter (inverter)
Ic: Cross current Vcmd: Voltage command Vcmd ': Voltage command after dead time compensation Vcmd1': Voltage command for inverter INV1 Vcmd2 ': Voltage command for inverter INV2 Vccc: Cross current compensation value (voltage command for cross current compensation)
Vccc_up: rising cross current compensation value Vccc_down: rising cross current compensation value Carrier: triangular carrier wave

Claims (2)

A PWM power converter parallel operation device in which two PWM power converters are connected in parallel and the outputs of the two PWM power converters are connected by an interphase reactor,
A carrier generation unit that outputs a triangular carrier wave for generating a gate command;
A triangular carrier wave determination unit that determines whether the triangular carrier wave is decreasing from the upper limit value to the lower limit value or is rising from the lower limit value to the upper limit value;
When the triangular carrier wave decreases from the upper limit value to the lower limit value, the cross current detection value falls and is input to the cross current control unit, and when the triangular carrier wave rises from the lower limit value to the upper limit value, the cross current detection value rises. A first selection unit that inputs to the cross current control unit;
A rising cross current control unit that calculates a rising cross current compensation value based on the detected value of the cross current during the period when the triangular carrier wave is rising from the lower limit value to the upper limit value;
A falling cross current control unit that calculates a falling cross current compensation value based on a detected value of the cross current during a period in which the triangular carrier wave decreases from the upper limit value to the lower limit value;
Outputs the rising cross current compensation value calculated by the rising cross current control unit during the period when the triangular carrier wave decreases from the upper limit value to the lower limit value, and falls during the period when the triangular carrier wave increases from the lower limit value to the upper limit value. A second selection unit for outputting the falling cross current compensation value calculated by:
An adder for adding the value output by the second selection unit to the voltage command of one PWM power converter;
A subtractor for subtracting the value output from the second selection unit from the voltage command of the other PWM power converter;
A parallel operation apparatus for PWM power converters. A parallel operation method of a parallel operation device for PWM power converters in which two PWM power converters are connected in parallel and the outputs of the two PWM power converters are connected by an interphase reactor,
In the carrier generation unit, a triangular carrier wave output process for outputting a triangular carrier wave for generating a gate command,
In the triangular carrier wave determination unit, a triangular carrier wave determination process for determining whether the triangular carrier wave is decreasing from the upper limit value to the lower limit value or a period rising from the lower limit value to the upper limit value;
The first selection unit inputs the detected value of the cross current into the cross current control unit while the triangular carrier wave is decreasing from the upper limit value to the lower limit value, and during the period when the triangular carrier wave rises from the lower limit value to the upper limit value. A first selection process in which the detected value of the cross current is risen and input to the cross current control unit;
The rising cross current control unit calculates the rising cross current compensation value based on the detected value of the cross current during the period in which the triangular carrier wave increases from the lower limit value to the upper limit value, and
A falling cross current compensation unit that calculates a falling cross current compensation value based on a detected value of the cross current during a period in which the triangular carrier wave decreases from an upper limit value to a lower limit value;
The second selection unit outputs the rising cross current compensation value calculated by the rising cross current control unit while the triangular carrier wave is decreasing from the upper limit value to the lower limit value, and the triangular carrier wave is increasing from the lower limit value to the upper limit value. A second selection process for outputting a falling cross-current compensation value calculated by the falling cross-flow control unit;
An addition process in which the adder adds the value output by the second selection unit to the voltage command of one of the PWM power converters;
A subtraction process in which the subtracter subtracts the value output from the second selection unit from the voltage command of the other PWM power converter;
A method for parallel operation of PWM power converters.

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