JP5733015B2 - Parallel operation apparatus and parallel operation method for PWM power converter - Google Patents

Description

  The present invention relates to a parallel operation device and a parallel operation method for PWM power converters, and more particularly to cross current compensation between PWM power converters and dead time compensation of each PWM power converter.

  The power converter is configured as an inverter or a converter using a semiconductor element as a main circuit switching element. As a means for increasing the capacity of this power converter, there is a method in which the outputs of a plurality of power converters are connected in parallel and the power converters are operated synchronously (see, for example, Patent Document 1 and Patent Document 2).

  In general, two factors that cause a decrease in output current are considered in parallel operation of power converters. The first factor is the existence of cross current. In parallel operation of power converters, if the outputs are simply connected in parallel, the output current of each device is unbalanced due to the characteristics of the elements inside the power converter, and a circulating current called a cross current is generated between the devices. As a cause of the occurrence of the cross current, a difference in wiring impedance and a difference in storage time of the switching element are considered.

  The second factor is the existence of dead time. There is a dead time generation circuit to prevent a short circuit between the upper and lower arms of the power converter. The dead time generation circuit creates a gate signal by adding dead time so that the upper and lower arms are not short-circuited.

  In a power converter to which such a dead time is added, the presence of the dead time causes the output current waveform to be distorted. In the conventional technique, in order to compensate for these two factors, two compensation circuits are added to operate the power converters in parallel.

  FIG. 5 shows a parallel operation apparatus for power converters described in Patent Document 1. This figure shows a case where cross current compensation and dead time compensation are added to two three-phase PWM inverters, and is represented by a single line diagram. In FIG. 5, the meaning of three diagonal lines in the signal line means that there are three phases. The DC input of the inverter 1 and inverter 2 is a DC voltage source PN, which is connected in parallel. The outputs of the inverters 1 and 2 are connected by an interphase reactor L_mut, and are connected to a load from an intermediate tap of L_mut. The output currents of the inverters 1 and 2 are I1 and I2, respectively, and the output current supplied to the load is Io. Here, the detection current used for current control is Idet. Moreover, the cross current Ic is represented by the deviation of I1 and I2. The relationship between I1, I2, Io, Idet, and Ic is shown in the following formula.

Io = I1 + I2 = Idet
Ic = I2-I1
The current control unit (ACR: Automatic Current Regulator) 3 calculates a deviation between a current command value Icmd common to both inverters and a detection current Idet obtained by averaging the output currents of both inverters by performing a proportional integral (PI) operation, and a voltage common to both inverters. A command value Vcmd is generated. A PWM (Pulse Width Modulation) control unit 4 compares the voltage command value Vcmd common to both inverters with a triangular carrier wave (carrier) from the carrier generation unit 5, and generates a gate command (PWM command) Gate.

  A dead time compensation unit (DTC: Dead Time Compensation) 6 detects and compensates for errors in the on-time and off-time between the gate command Gate and the detected phase voltages Vce1 and Vce2, and outputs the gate command Gate ′ after the dead time compensation. Generate.

  In this dead time compensation calculation, the detected phase voltages Vce1 and Vce2 are output from the detected phase voltages V1 and V2 of the inverters 1 and 2 as the phase voltage detector (Vce) 7 is insulated. Since two inverters are connected in parallel, there are two errors to be detected (an error between the gate command Gate and the phase voltage Vce1 and an error between the gate command Gate and the phase voltage Vce2), and the value used for dead time compensation is, for example, 2 Take the average of the detection error of one inverter. The details of the dead time compensation method are proposed in Patent Document 3, for example.

  A cross current compensation (CCC) 8 performs a cross current compensation operation on the gate command Gate ', and generates a gate command Gate1' for the inverter 1 and a gate command Gate2 'for the inverter 2. The cross current control unit (Balance ACR) 9 calculates a deviation of the currents I1 and I2 (cross current value Ic) as a proportional integral (PI) and obtains it as a cross current, and calculates it as a cross current compensation time Tccc for compensating this cross current. This is fed back to the cross current compensator 8.

  The dead time generators (DT1, DT2) 10, 11 receive the gate commands Gate1 'and Gate2', and output switching commands G1_U, G1_L, G2_U, G2_L with the dead time period Td added thereto. These signals are switching commands for each phase of the inverters 1 and 2 and the upper and lower arms, and are turned on / off with a dead time between the switching elements which are the upper and lower arms of each phase of the inverter 1.2.

Japanese Patent No. 3185257 JP 2004-15923 A Japanese Patent No. 3496943

  FIG. 6 shows a time chart of conventional dead time compensation and cross current compensation. In FIG. 6, in the conventional dead time compensation, an error Vce_DLY between the gate command Gate and the detection phase voltage Vce is measured, and the dead time compensation is performed so as to reduce this measurement error. The compensated gate command Gate 'is a command approaching the gate command Gate by compensation. However, the delay time DTC_DLY still exists in the gate command Gate and the compensated gate command Gate ′.

  In the conventional cross current compensation, a cross current compensation delay CCC_DLY exists so as not to interfere with the dead time compensation. Cross current compensation is realized by increasing or decreasing the width of the pulse by the cross current compensation time Tccc around the cross current compensation delay CCC_DLY.

  The above error Vce_DLY differs depending on the error at the leading edge and the trailing edge of the gate Gate, but in FIG. 6 and the embodiment, it will be described as the same for the sake of simplicity. Similarly, the delay time DTC_DLY will be described as the same delay time at the leading edge and the trailing edge, assuming that the phase voltages Vce1 and Vce2 are equal. Further, the cross current compensation time Tccc will be described as the same compensation time for the leading edge and the trailing edge.

  As a result of performing the above-described dead time compensation and cross current compensation, the width of Gate may change greatly. If the Gate itself is a narrow pulse output, there is a high possibility of missing pulses during dead time generation. As a result, in the compensation of the conventional technique, the limitation of the minimum on-pulse time becomes a factor, and it becomes impossible to output a thin pulse, and as a result, the upper limit of the maximum output of the inverter is lowered.

  Further, by performing the two compensations of the dead time compensation and the cross current compensation, a delay time in which the delay time is the sum of DTC_DLY and CCC_DLY is generated. In particular, when the inverter is used with high response, these delay times become dead time, and the upper limit of response speed is limited.

  An object of the present invention is to provide a parallel operation device and a parallel operation method for PWM power converters that can eliminate the delay time DTC_DLY after dead time compensation and the delay time CCC_DLY due to cross current compensation.

  In order to solve the above-mentioned problem, the present invention adds an average value of dead time compensation values of each PWM power converter to a common voltage command value of parallel PWM power converters, and adds the average value of each PWM power converter to each PWM power converter. Each of the cross current compensation values is added to generate a voltage command value for each PWM power converter, and is characterized by the following apparatus and method.

PWM power conversion in which outputs of a plurality of PWM power converters are connected in parallel, and each power converter is operated synchronously by having a cross current compensation means between the PWM power converters and a dead time compensation means of each PWM power converter. A parallel operation device for a vessel,
The dead time compensation means includes a phase voltage detector that detects a phase voltage (Vce) of each PWM power converter, a PWM command (Gate) from a PWM controller for each PWM power converter, and the phase voltage (Vce). ) And the PWM command (Gate) and the off time of the phase voltage (Vce) are detected, and the detected error time is used as a common voltage command value for each PWM power converter ( Vmd) is converted as a dead time compensation voltage (Vdtc) in the same unit, and these dead time compensation voltages are converted into the PWM power converters according to the polarity of the next PWM control on / off of each PWM power converter. A dead time compensator for adding and subtracting to a common voltage command value (Vcmd);
The cross current compensation means detects the cross current (Ic) between the PWM power converters, obtains the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter, A cross current control unit is provided that adds a compensation value (Vccc) to one PWM voltage command value according to the value of the cross current (Ic) and subtracts it from the other PWM voltage command value.

Parallel output of PWM power converters that connect the outputs of multiple PWM power converters in parallel, perform cross current compensation between each PWM power converter and dead time compensation of each PWM power converter, and operate each power converter synchronously Driving method,
In the dead time compensation, the phase voltage detection unit detects the phase voltage (Vce) of each PWM power converter, and the dead time compensation unit receives the PWM command (Gate) from the PWM control unit for each PWM power converter. The error time of the ON time of the phase voltage (Vce) is detected, and the error time of the PWM command (Gate) and the OFF time of the phase voltage (Vce) is detected, and these detected error times are common to each PWM power converter. Is converted as a dead time compensation voltage (Vdtc) in the same unit as the voltage command value (Vcmd), and the dead time compensation voltage is changed according to the on / off polarity of the next PWM control of each PWM power converter. Addition / subtraction to the common voltage command value (Vcmd) of the PWM power converter,
In the cross current compensation, the cross current control unit detects the cross current (Ic) between the PWM power converters, and uses the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter. This cross current compensation value (Vccc) is added to one PWM voltage command value according to the value of the cross current (Ic), and subtracted from the other PWM voltage command value.

  As described above, according to the present invention, the average value of the dead time compensation value of each PWM power converter is added to the common voltage command value of the parallel PWM power converter, and the cross current compensation for each PWM power converter is added to this. Since each value is added to generate a voltage command value for each PWM power converter, the delay time DTC_DLY after the dead time compensation and the delay time CCC_DLY due to the cross current compensation can each be eliminated.

  By eliminating the delay time DTC_DLY and the delay time CCC_DLY individually and simultaneously, it is possible to solve the conventional individual problems and both problems.

The block diagram of the parallel operation apparatus of the PWM power converter which becomes embodiment of this invention. The time chart of the dead time compensation which becomes embodiment of this invention. The time chart of the cross current compensation which becomes embodiment of this invention. The dead time compensation waveform and cross current compensation waveform figure by the past and embodiment. The figure which shows the structural example of the parallel operation apparatus of the conventional power converter. Time chart of conventional dead time compensation and cross current compensation.

(1) Configuration of Device FIG. 1 shows a configuration of a parallel operation device for PWM power converters according to an embodiment of the present invention. This figure shows a case where cross current compensation and dead time compensation are used in combination with two three-phase PWM inverters, and is represented by a single line diagram. The same configuration can be applied to a parallel operation device of three or more PWM inverters, and further to a parallel operation device of three or more PWM power converters.

  The DC input of the inverter 1 and inverter 2 is a DC voltage source PN, which is connected in parallel. The outputs of the inverters 1 and 2 are connected by an interphase reactor L_mut, and are connected to a load from an intermediate tap of L_mut. The output currents of the inverters 1 and 2 are I1 and I2, respectively, and the output current supplied to the load is Io. Here, the detection current used for current control is Idet. Moreover, the cross current Ic is represented by the deviation of I1 and I2. Idet performs current control so as to follow the current command Icmd. The current control unit 3 generates a voltage command value Vcmd.

  The dead time compensation and the cross current compensation of this embodiment prevent the occurrence of missing pulses due to the dead time generation, minimize the delay due to the compensation, and prevent the dead time compensation and the cross current compensation from interfering with each other. Instead of adding the dead time compensation value for the gate command (PWM command) from the unit, and further the cross current compensation value, the average value of the dead time compensation value of each inverter is added to the common voltage command value of the parallel inverter, The cross current compensation value for each inverter is added to this to generate a voltage command value for each inverter. Therefore, the PWM control unit is provided for the number of inverters in parallel. In this embodiment, since there are two inverters, the PWM control units 4A and 4B are referred to as PWM1 and PWM2, respectively.

  In PWM1, the voltage command value Vcmd1 'and the triangular carrier wave Carrier are compared to generate the gate command Gate1, and similarly, in PWM2, the voltage command value Vcmd2' and Carrier are compared to generate the gate command Gate2. Dead time generators (DT1, DT2) 10, 11 receive Gate1 'and Gate2' as inputs, and output switching commands G1_U, G1_L, G2_U, G2_L having a dead time period Td. These signals are switching commands for each phase of the inverters 1 and 2 and the upper and lower arms, and are turned on / off with a dead time between the switching elements which are the upper and lower arms of each phase of the inverter 1.2.

(2) Dead time compensation Dead time compensation will be described. FIG. 2 shows a time chart for dead time compensation. However, FIG. 2 shows only the time chart of one inverter 1. First, an error Vce_DLY1 between the on-time and off-time of the gate command Gate1 and the detection phase voltage Vce1 is measured. The dead time compensator (DTC) 6 uses the error time measurement value for the dead time compensation, and therefore uses the error time measurement value as the voltage command value Vcmd [p. u. ] Dead time compensation voltage Vdtc1 [p. u. ] Is obtained. This dead time compensation voltage Vdtc1 is obtained by setting the amplitude of one half of the carrier signal generated by the carrier generator 5 of PWM control to 1 [p. u. ], The carrier frequency Fc [Hz] is obtained by the following equation.

Vdtc1 [p. u. ] = 2 × Vce_DLY1 [s] × 2 Fc [Hz]
Similarly, the dead time compensation unit (DTC) 6 detects the gate command Gate2 of the other inverter 2 and the error Vce2 between the on time and the off time, and obtains the dead time compensation voltage Vdtc2. Furthermore, since there is Vce_DLY for two inverters, the dead time compensation unit (DTC) 6 takes the average of the respective dead time compensation voltages Vdtc1 and Vdtc2 and outputs it as the dead time compensation voltage Vdtc.

  The dead time compensation voltage Vdtc from the dead time compensation unit (DTC) 6 is superimposed on the voltage command value Vcmd so that the Gate 1 before dead time compensation and the detected phase voltage Vce 1 after compensation coincide. This superposition is performed by adding / subtracting to / from the common voltage command value (Vcmd) of each PWM power converter according to the polarity of the next PWM control ON / OFF. The dead time compensation voltage Vdtc is added, and the off time dead time compensation voltage Vdtc is subtracted while the PWM carrier is rising. As a result, it is possible to perform dead time compensation in which Gate 1 before dead time compensation and Vce 1 after compensation are made to coincide with each other so that the error is substantially zero.

  As described above, by the dead time compensation according to the present embodiment, the error between the gate command Gate before the dead time compensation and the phase voltage detection value Vce after the dead time compensation can be almost zero, and the delay after the dead time compensation. Time DTC_DLY can be eliminated. Accordingly, the limit on the minimum on-pulse time can be reduced, and a narrower PWM pulse can be output. If a narrower PWM pulse can be output, the maximum output voltage of a power converter such as an inverter can be increased. Moreover, the dead time of a PWM inverter becomes small, and the response of current control and frequency control improves. Further, since the dead time compensation value is superimposed on the voltage command, no missing pulse occurs when the dead time is generated.

  Further, since the phase voltage detection unit 7 does not change from the conventional mechanism, only the dead time compensation unit 6 needs to be changed.

  Furthermore, the dead time compensation can reduce the 6f component of the output current. FIG. 4A shows a current waveform in a conventional apparatus in a test in which an inductive load is connected to an inverter, and FIG. 4B shows a current waveform when the dead time compensation according to the present embodiment is applied. From these waveform diagrams, it was confirmed that the current distortion was reduced as shown in FIG. 4B compared to the waveform of FIG. 4A by the dead time compensation according to the present embodiment.

(3) Cross current compensation Cross current compensation will be described. FIG. 3 shows a time chart for cross current compensation. Here, FIG. 3 shows a case where the dead time compensation voltage Vdtc = 0 for simplification of explanation.

  The cross current control unit (Balance ACR) 9 performs a proportional integral (PI) operation on the deviation (cross current value Ic) of the output currents I1 and I2 of the inverters 1 and 2, and is the same as the common voltage command value (Vcmd) of each PWM inverter. It is obtained as a cross current compensation value Vccc in units. The cross current compensation value Vccc is added to the voltage command value Vcmd ′ after the dead time compensation so that the cross current value Ic becomes zero to obtain the voltage command value Vcmd1 ′ of the inverter 1, and the voltage command value Vcmd after the dead time compensation. By subtracting from ', the voltage command value Vcmd2' of the inverter 2 is obtained. As a result, the voltages of the two inverters 1 and 2 are deviated in a direction in which no cross current is generated, so that the cross current becomes small.

  The dead time compensation voltage Vdtc and the cross current compensation voltage Vccc described above have the following relationship with the dead time compensated voltage command value Vcmd 'and the cross current compensated voltage command values Vcmd1' and Vcmd2 '.

Vcmd '= Vcmd + Vdtc
Vcmd1 ′ = Vcmd ′ + Vccc
Vcmd2 ′ = Vcmd ′ + Vccc
As described above, by the cross current compensation according to the present embodiment, the delay time CCC_DLY of the gate command Gate ′ before the cross current compensation and the gate commands Gate1 ′ and Gate2 ′ after the cross current compensation can be made substantially zero, and the delay time CCC_DLY by this cross current compensation Can be eliminated. Along with this, the limit of the minimum on-pulse time can be reduced, and a narrower PWM pulse can be output. If a narrower PWM pulse can be output, the maximum output voltage of a power converter such as an inverter can be increased. Moreover, the dead time of a PWM inverter becomes small, and the response of current control and frequency control improves. In addition, since the cross current compensation value is superimposed on the voltage command, no pulse missing occurs due to the cross current compensation. Further, since the cross flow control unit 9 is not different from the conventional mechanism, only the cross flow compensation unit 8 needs to be changed.

  Further, the distortion of the output current can be reduced by the cross current compensation. FIG. 4C shows a current waveform when the cross current compensation according to the present embodiment is applied, and the distortion of the current is reduced as shown in FIG. 4C compared to the waveform of FIG. Was confirmed.

(4) Combined use of dead time compensation and cross current compensation Up to this point, the effects of applying dead time compensation and cross current compensation individually have been described, but a synergistic effect is obtained by applying dead time compensation and cross current compensation simultaneously. be able to.

  For example, when dead time compensation and cross current compensation are simultaneously superimposed on the voltage command, each compensation can be made non-interfering. FIG. 4D shows a current waveform when dead time compensation and cross current compensation according to the configuration of FIG. 1 are applied simultaneously, and the dead time compensation and cross current compensation do not interfere with each other, and FIGS. It was confirmed that it has a compensation effect.

DESCRIPTION OF SYMBOLS 1, 2 Inverter 3 Current control part 4, 4A, 4B PWM control part 5 Carrier generation part 6 Dead time compensation part 7 Phase voltage detection part 8 Cross current compensation part 9 Cross current control part 10, 11 Dead time generation part

Claims (2)

PWM power conversion in which outputs of a plurality of PWM power converters are connected in parallel, and each power converter is operated synchronously by having a cross current compensation means between the PWM power converters and a dead time compensation means of each PWM power converter. A parallel operation device for a vessel,
The dead time compensation means includes a phase voltage detector that detects a phase voltage (Vce) of each PWM power converter, a PWM command (Gate) from a PWM controller for each PWM power converter, and the phase voltage (Vce). ) And the PWM command (Gate) and the off time of the phase voltage (Vce) are detected, and the detected error time is used as a common voltage command value for each PWM power converter ( Vmd) is converted as a dead time compensation voltage (Vdtc) in the same unit, and these dead time compensation voltages are converted into the PWM power converters according to the polarity of the next PWM control on / off of each PWM power converter. A dead time compensator for adding and subtracting to a common voltage command value (Vcmd);
The cross current compensation means detects the cross current (Ic) between the PWM power converters, obtains the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter, A PWM power converter comprising a cross current control unit that adds a compensation value (Vccc) to one PWM voltage command value in accordance with the value of the cross current (Ic) and subtracts it from the other PWM voltage command value Parallel operation device. Parallel output of PWM power converters that connect the outputs of multiple PWM power converters in parallel, perform cross current compensation between each PWM power converter and dead time compensation of each PWM power converter, and operate each power converter synchronously Driving method,
In the dead time compensation, the phase voltage detection unit detects the phase voltage (Vce) of each PWM power converter, and the dead time compensation unit receives the PWM command (Gate) from the PWM control unit for each PWM power converter. The error time of the ON time of the phase voltage (Vce) is detected, and the error time of the PWM command (Gate) and the OFF time of the phase voltage (Vce) is detected, and these detected error times are common to each PWM power converter. Is converted as a dead time compensation voltage (Vdtc) in the same unit as the voltage command value (Vcmd), and the dead time compensation voltage is changed according to the on / off polarity of the next PWM control of each PWM power converter. Addition / subtraction to the common voltage command value (Vcmd) of the PWM power converter,
In the cross current compensation, the cross current control unit detects the cross current (Ic) between the PWM power converters, and uses the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter. This parallel current compensation value (Vccc) is added to one PWM voltage command value in accordance with the value of the cross current (Ic) and subtracted from the other PWM voltage command value. how to drive.

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