JP5733015B2 - Parallel operation apparatus and parallel operation method for PWM power converter - Google Patents

Parallel operation apparatus and parallel operation method for PWM power converter Download PDF

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JP5733015B2
JP5733015B2 JP2011110114A JP2011110114A JP5733015B2 JP 5733015 B2 JP5733015 B2 JP 5733015B2 JP 2011110114 A JP2011110114 A JP 2011110114A JP 2011110114 A JP2011110114 A JP 2011110114A JP 5733015 B2 JP5733015 B2 JP 5733015B2
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鎮教 濱田
鎮教 濱田
利道 高橋
利道 高橋
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Meidensha Corp
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本発明は、PWM電力変換器の並列運転装置および並列運転方法に係り、特に、PWM電力変換器間の横流補償と各PWM電力変換器のデッドタイム補償に関する。   The present invention relates to a parallel operation device and a parallel operation method for PWM power converters, and more particularly to cross current compensation between PWM power converters and dead time compensation of each PWM power converter.

電力変換器は半導体素子を主回路スイッチング素子としてインバータまたはコンバータに構成される。この電力変換器の大容量化手段として、複数台の電力変換器の出力を並列接続して各電力変換器を同期運転する方法がある(例えば特許文献1、特許文献2参照)。   The power converter is configured as an inverter or a converter using a semiconductor element as a main circuit switching element. As a means for increasing the capacity of this power converter, there is a method in which the outputs of a plurality of power converters are connected in parallel and the power converters are operated synchronously (see, for example, Patent Document 1 and Patent Document 2).

一般に、電力変換器の並列運転には出力電流を低下させる2つの要因が考えられる。一つ目の要因は横流の存在である。電力変換器の並列運転では出力を単に並列接続するだけでは電力変換器内部の素子の特性により、各装置の出力電流に不平衡が生じ、装置間に横流と呼ばれる循環電流が発生する。横流発生の原因として、配線インピーダンスの差、スイッチング素子のストレージタイムの差が考えられる。   In general, two factors that cause a decrease in output current are considered in parallel operation of power converters. The first factor is the existence of cross current. In parallel operation of power converters, if the outputs are simply connected in parallel, the output current of each device is unbalanced due to the characteristics of the elements inside the power converter, and a circulating current called a cross current is generated between the devices. As a cause of the occurrence of the cross current, a difference in wiring impedance and a difference in storage time of the switching element are considered.

二つ目の要因はデッドタイムの存在である。電力変換器の上下アーム短絡を防ぐためにデッドタイム生成回路がある。デッドタイム生成回路は上下アームが短絡しないようにデッドタイムを付加してゲート信号を作成する。   The second factor is the existence of dead time. There is a dead time generation circuit to prevent a short circuit between the upper and lower arms of the power converter. The dead time generation circuit creates a gate signal by adding dead time so that the upper and lower arms are not short-circuited.

このようなデッドタイムを付加した電力変換器において、デッドタイムの存在が出力電流波形を歪ませる原因になる。従来の技術ではこの2つの要因を補償するために2つの補償回路を付加して電力変換器を並列運転している。   In a power converter to which such a dead time is added, the presence of the dead time causes the output current waveform to be distorted. In the conventional technique, in order to compensate for these two factors, two compensation circuits are added to operate the power converters in parallel.

図5は特許文献1に記載される電力変換器の並列運転装置を示す。同図は2台の3相PWMインバータに横流補償とデッドタイム補償を付加した場合であり、単線図で表記する。図5の中で信号線に3本の斜線がある意味は3相あることを意味している。インバータ1、インバータ2の直流入力は直流電圧源PNであり、これを並列に接続する。インバータ1、2の出力は相間リアクトルL_mutで接続し、L_mutの中間タップから負荷に接続する。インバータ1、インバータ2それぞれの出力電流をI1、I2とし、負荷に供給される出力電流はIoである。ここで、電流制御に使用する検出電流をIdetとする。また、横流IcはI1、I2の偏差で表される。下式にI1、I2、Io、Idet、Icの関係を示す。   FIG. 5 shows a parallel operation apparatus for power converters described in Patent Document 1. This figure shows a case where cross current compensation and dead time compensation are added to two three-phase PWM inverters, and is represented by a single line diagram. In FIG. 5, the meaning of three diagonal lines in the signal line means that there are three phases. The DC input of the inverter 1 and inverter 2 is a DC voltage source PN, which is connected in parallel. The outputs of the inverters 1 and 2 are connected by an interphase reactor L_mut, and are connected to a load from an intermediate tap of L_mut. The output currents of the inverters 1 and 2 are I1 and I2, respectively, and the output current supplied to the load is Io. Here, the detection current used for current control is Idet. Moreover, the cross current Ic is represented by the deviation of I1 and I2. The relationship between I1, I2, Io, Idet, and Ic is shown in the following formula.

Io=I1+I2=Idet
Ic=I2−I1
電流制御部(ACR:Automatic Current Regulator)3は、両インバータに共通の電流指令値Icmdと両インバータの出力電流を平均した検出電流Idetの偏差を比例積分(PI)演算して両インバータ共通の電圧指令値Vcmdを生成する。PWM(Pulse Width Modulation)制御部4は、両インバータ共通の電圧指令値Vcmdとキャリア生成部5からの三角搬送波(キャリア:Carrier)を比較し、ゲート指令(PWM指令)Gateを生成する。
Io = I1 + I2 = Idet
Ic = I2-I1
The current control unit (ACR: Automatic Current Regulator) 3 calculates a deviation between a current command value Icmd common to both inverters and a detection current Idet obtained by averaging the output currents of both inverters by performing a proportional integral (PI) operation, and a voltage common to both inverters. A command value Vcmd is generated. A PWM (Pulse Width Modulation) control unit 4 compares the voltage command value Vcmd common to both inverters with a triangular carrier wave (carrier) from the carrier generation unit 5, and generates a gate command (PWM command) Gate.

デッドタイム補償部(DTC:Dead Time Compensation)6は、ゲート指令Gateと検出相電圧Vce1、Vce2とのオンタイムおよびオフタイムの誤差を検出し補償を行い、デッドタイム補償後のゲート指令Gate’を生成する。   A dead time compensation unit (DTC: Dead Time Compensation) 6 detects and compensates for errors in the on-time and off-time between the gate command Gate and the detected phase voltages Vce1 and Vce2, and outputs the gate command Gate ′ after the dead time compensation. Generate.

このデッドタイム補償演算には、インバータ1、インバータ2の検出相電圧V1、V2から、相電圧検出部(Vce)7が絶縁された検出相電圧Vce1、Vce2として出力する。インバータを2台並列接続するため、検出する誤差も2つの誤差(ゲート指令Gateと相電圧Vce1の誤差とゲート指令Gateと相電圧Vce2の誤差)があり、デッドタイム補償に使用する値は例えば2台のインバータの検出誤差の平均を取る。デッドタイム補償法の詳細は例えば特許文献3で提案されている。   In this dead time compensation calculation, the detected phase voltages Vce1 and Vce2 are output from the detected phase voltages V1 and V2 of the inverters 1 and 2 as the phase voltage detector (Vce) 7 is insulated. Since two inverters are connected in parallel, there are two errors to be detected (an error between the gate command Gate and the phase voltage Vce1 and an error between the gate command Gate and the phase voltage Vce2), and the value used for dead time compensation is, for example, 2 Take the average of the detection error of one inverter. The details of the dead time compensation method are proposed in Patent Document 3, for example.

横流補償部(CCC:Cross Current Compensation)8は、ゲート指令Gate’に対する横流補償演算を行い、インバータ1のゲート指令Gate1’およびインバータ2のゲート指令Gate2’を生成する。横流制御部(Balance ACR)9は、電流I1、I2の偏差(横流値Ic)を比例積分(PI)演算して横流分として求め、この横流分を補償するための横流補償時間Tcccとして算出し、これを横流補償部8にフィードバックする。   A cross current compensation (CCC) 8 performs a cross current compensation operation on the gate command Gate ', and generates a gate command Gate1' for the inverter 1 and a gate command Gate2 'for the inverter 2. The cross current control unit (Balance ACR) 9 calculates a deviation of the currents I1 and I2 (cross current value Ic) as a proportional integral (PI) and obtains it as a cross current, and calculates it as a cross current compensation time Tccc for compensating this cross current. This is fed back to the cross current compensator 8.

デッドタイム生成部(DT1、DT2)10、11は、ゲート指令Gate1’およびGate2’を入力とし、これらにデッドタイム期間Tdを付加したスイッチング指令G1_U、G1_L、G2_U、G2_Lを出力する。これら信号はインバータ1、2の各相および上下アーム別のスイッチング指令であり、インバータ1.2の各相の上下アームになるスイッチング素子間にデッドタイムを持たせてオン・オフ動作させる。   The dead time generators (DT1, DT2) 10, 11 receive the gate commands Gate1 'and Gate2', and output switching commands G1_U, G1_L, G2_U, G2_L with the dead time period Td added thereto. These signals are switching commands for each phase of the inverters 1 and 2 and the upper and lower arms, and are turned on / off with a dead time between the switching elements which are the upper and lower arms of each phase of the inverter 1.2.

特許第3185257号公報Japanese Patent No. 3185257 特開2004−15923号公報JP 2004-15923 A 特許第3496943号公報Japanese Patent No. 3496943

図6に従来のデッドタイム補償と横流補償のタイムチャートを示す。図6において、従来のデッドタイム補償では、ゲート指令Gateと検出相電圧Vceとの誤差Vce_DLYを計測し、この計測誤差が小さくなるようにデッドタイム補償を行っている。補償後のゲート指令Gate’は補償によりゲート指令Gateに近づいた指令になっている。しかし、まだ、ゲート指令Gateと補償後のゲート指令Gate’とには遅延時間DTC_DLYが存在する。   FIG. 6 shows a time chart of conventional dead time compensation and cross current compensation. In FIG. 6, in the conventional dead time compensation, an error Vce_DLY between the gate command Gate and the detection phase voltage Vce is measured, and the dead time compensation is performed so as to reduce this measurement error. The compensated gate command Gate 'is a command approaching the gate command Gate by compensation. However, the delay time DTC_DLY still exists in the gate command Gate and the compensated gate command Gate ′.

従来の横流補償では、デッドタイム補償と干渉させないようにするために横流補償遅延CCC_DLYが存在する。横流補償は横流補償遅延CCC_DLYを中心にパルスの幅を横流補償時間Tccc分増やしたり、減らしたりすることで実現する。   In the conventional cross current compensation, a cross current compensation delay CCC_DLY exists so as not to interfere with the dead time compensation. Cross current compensation is realized by increasing or decreasing the width of the pulse by the cross current compensation time Tccc around the cross current compensation delay CCC_DLY.

なお、上記の誤差Vce_DLYは、ゲートGateの前縁での誤差と後縁での誤差で異なるが、図6および実施形態では説明簡略化のために同じものとして説明する。同様に、上記の遅延時間DTC_DLYは、相電圧Vce1とVce2が等しいものとして、以下では前縁と後縁で同じ遅延時間として説明する。さらに、横流補償時間Tcccも前縁と後縁で同じ補償時間として説明する。   The above error Vce_DLY differs depending on the error at the leading edge and the trailing edge of the gate Gate, but in FIG. 6 and the embodiment, it will be described as the same for the sake of simplicity. Similarly, the delay time DTC_DLY will be described as the same delay time at the leading edge and the trailing edge, assuming that the phase voltages Vce1 and Vce2 are equal. Further, the cross current compensation time Tccc will be described as the same compensation time for the leading edge and the trailing edge.

上記のデッドタイム補償および横流補償を行った結果、Gateの幅は大きく変化する場合がある。もし、Gate自体が細いパルス出力であった場合、デッドタイム生成時にパルス欠けが発生する可能性が高い。これより、従来の技術の補償では最小オンパルス時間の制限を長くする要因となり、細いパルスが出力できなくなり、結果的にインバータの最大出力の上限が低下する。   As a result of performing the above-described dead time compensation and cross current compensation, the width of Gate may change greatly. If the Gate itself is a narrow pulse output, there is a high possibility of missing pulses during dead time generation. As a result, in the compensation of the conventional technique, the limitation of the minimum on-pulse time becomes a factor, and it becomes impossible to output a thin pulse, and as a result, the upper limit of the maximum output of the inverter is lowered.

また、デッドタイム補償および横流補償の二つの補償を行うことで、遅延時間がDTC_DLYとCCC_DLYを合計した遅延時間が発生する。特に、インバータを高応答で使用する場合、これらの遅延時間が無駄時間にとなり、応答速度の上限が制限される。   Further, by performing the two compensations of the dead time compensation and the cross current compensation, a delay time in which the delay time is the sum of DTC_DLY and CCC_DLY is generated. In particular, when the inverter is used with high response, these delay times become dead time, and the upper limit of response speed is limited.

本発明の目的は、デッドタイム補償後の遅延時間DTC_DLYおよび横流補償による遅延時間CCC_DLYをそれぞれ無くすこともできるPWM電力変換器の並列運転装置および並列運転方法を提供することにある。   An object of the present invention is to provide a parallel operation device and a parallel operation method for PWM power converters that can eliminate the delay time DTC_DLY after dead time compensation and the delay time CCC_DLY due to cross current compensation.

本発明は、前記の課題を解決するため、並列PWM電力変換器の共通の電圧指令値に各PWM電力変換器のデッドタイム補償値の平均値を加算し、これに各PWM電力変換器別の横流補償値をそれぞれ加算してPWM電力変換器別の電圧指令値を生成するようにしたもので、以下の装置および方法を特徴とする。   In order to solve the above-mentioned problem, the present invention adds an average value of dead time compensation values of each PWM power converter to a common voltage command value of parallel PWM power converters, and adds the average value of each PWM power converter to each PWM power converter. Each of the cross current compensation values is added to generate a voltage command value for each PWM power converter, and is characterized by the following apparatus and method.

複数台のPWM電力変換器の出力を並列接続し、各PWM電力変換器間の横流補償手段と各PWM電力変換器のデッドタイム補償手段を有して各電力変換器を同期運転するPWM電力変換器の並列運転装置であって、
前記デッドタイム補償手段は、各PWM電力変換器の相電圧(Vce)を検出する相電圧検出部と、各PWM電力変換器別のPWM制御部からのPWM指令(Gate)と前記相電圧(Vce)のオン時間の誤差時間を検出、およびPWM指令(Gate)と相電圧(Vce)のオフ時間の誤差時間を検出し、これら検出した誤差時間を各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位のデッドタイム補償電圧(Vdtc)としてそれぞれ変換し、これらデッドタイム補償電圧を各PWM電力変換器の次回のPWM制御のオン/オフの極性に応じて、各PWM電力変換器の共通の電圧指令値(Vcmd)に加減算するデッドタイム補償部を備え、
前記横流補償手段は、各PWM電力変換器間の横流(Ic)を検出し、各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位の横流補償値(Vccc)として求め、この横流補償値(Vccc)を前記横流(Ic)の値に応じて一方のPWM電圧指令値に加算し、他方のPWM電圧指令値から減算する横流制御部を備えたことを特徴とする
PWM power conversion in which outputs of a plurality of PWM power converters are connected in parallel, and each power converter is operated synchronously by having a cross current compensation means between the PWM power converters and a dead time compensation means of each PWM power converter. A parallel operation device for a vessel,
The dead time compensation means includes a phase voltage detector that detects a phase voltage (Vce) of each PWM power converter, a PWM command (Gate) from a PWM controller for each PWM power converter, and the phase voltage (Vce). ) And the PWM command (Gate) and the off time of the phase voltage (Vce) are detected, and the detected error time is used as a common voltage command value for each PWM power converter ( Vmd) is converted as a dead time compensation voltage (Vdtc) in the same unit, and these dead time compensation voltages are converted into the PWM power converters according to the polarity of the next PWM control on / off of each PWM power converter. A dead time compensator for adding and subtracting to a common voltage command value (Vcmd);
The cross current compensation means detects the cross current (Ic) between the PWM power converters, obtains the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter, A cross current control unit is provided that adds a compensation value (Vccc) to one PWM voltage command value according to the value of the cross current (Ic) and subtracts it from the other PWM voltage command value.

複数台のPWM電力変換器の出力を並列接続し、各PWM電力変換器間の横流補償と各PWM電力変換器のデッドタイム補償をして各電力変換器を同期運転するPWM電力変換器の並列運転方法であって、
前記デッドタイム補償は、相電圧検出部が各PWM電力変換器の相電圧(Vce)を検出し、デッドタイム補償部が、各PWM電力変換器別のPWM制御部からのPWM指令(Gate)と前記相電圧(Vce)のオン時間の誤差時間を検出、およびPWM指令(Gate)と相電圧(Vce)のオフ時間の誤差時間を検出し、これら検出した誤差時間を各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位のデッドタイム補償電圧(Vdtc)としてそれぞれ変換し、これらデッドタイム補償電圧を各PWM電力変換器の次回のPWM制御のオン/オフの極性に応じて、各PWM電力変換器の共通の電圧指令値(Vcmd)に加減算し、
前記横流補償は、横流制御部が、各PWM電力変換器間の横流(Ic)を検出し、各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位の横流補償値(Vccc)として求め、この横流補償値(Vccc)を前記横流(Ic)の値に応じて一方のPWM電圧指令値に加算し、他方のPWM電圧指令値から減算することを特徴とする。

Parallel output of PWM power converters that connect the outputs of multiple PWM power converters in parallel, perform cross current compensation between each PWM power converter and dead time compensation of each PWM power converter, and operate each power converter synchronously Driving method,
In the dead time compensation, the phase voltage detection unit detects the phase voltage (Vce) of each PWM power converter, and the dead time compensation unit receives the PWM command (Gate) from the PWM control unit for each PWM power converter. The error time of the ON time of the phase voltage (Vce) is detected, and the error time of the PWM command (Gate) and the OFF time of the phase voltage (Vce) is detected, and these detected error times are common to each PWM power converter. Is converted as a dead time compensation voltage (Vdtc) in the same unit as the voltage command value (Vcmd), and the dead time compensation voltage is changed according to the on / off polarity of the next PWM control of each PWM power converter. Addition / subtraction to the common voltage command value (Vcmd) of the PWM power converter,
In the cross current compensation, the cross current control unit detects the cross current (Ic) between the PWM power converters, and uses the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter. This cross current compensation value (Vccc) is added to one PWM voltage command value according to the value of the cross current (Ic), and subtracted from the other PWM voltage command value.

以上のとおり、本発明によれば、並列PWM電力変換器の共通の電圧指令値に各PWM電力変換器のデッドタイム補償値の平均値を加算し、これに各PWM電力変換器別の横流補償値をそれぞれ加算してPWM電力変換器別の電圧指令値を生成するようにしたため、デッドタイム補償後の遅延時間DTC_DLYおよび横流補償による遅延時間CCC_DLYをそれぞれ無くすことができる。   As described above, according to the present invention, the average value of the dead time compensation value of each PWM power converter is added to the common voltage command value of the parallel PWM power converter, and the cross current compensation for each PWM power converter is added to this. Since each value is added to generate a voltage command value for each PWM power converter, the delay time DTC_DLY after the dead time compensation and the delay time CCC_DLY due to the cross current compensation can each be eliminated.

これら遅延時間DTC_DLYと遅延時間CCC_DLYを個々に無くすこと、および同時に無くすことにより、従来の個々の課題および両方の課題を解決することができる。   By eliminating the delay time DTC_DLY and the delay time CCC_DLY individually and simultaneously, it is possible to solve the conventional individual problems and both problems.

本発明の実施形態になるPWM電力変換器の並列運転装置の構成図。The block diagram of the parallel operation apparatus of the PWM power converter which becomes embodiment of this invention. 本発明の実施形態になるデッドタイム補償のタイムチャート。The time chart of the dead time compensation which becomes embodiment of this invention. 本発明の実施形態になる横流補償のタイムチャート。The time chart of the cross current compensation which becomes embodiment of this invention. 従来と実施形態によるデッドタイム補償波形と横流補償波形図。The dead time compensation waveform and cross current compensation waveform figure by the past and embodiment. 従来の電力変換器の並列運転装置の構成例を示す図。The figure which shows the structural example of the parallel operation apparatus of the conventional power converter. 従来のデッドタイム補償と横流補償のタイムチャート。Time chart of conventional dead time compensation and cross current compensation.

(1)装置の構成
図1は、本発明の実施形態になるPWM電力変換器の並列運転装置の構成を示す。同図は2台の3相PWMインバータに横流補償とデッドタイム補償を併用した場合であり、単線図で表記する。なお、同様の構成を3台以上のPWMインバータの並列運転装置に適用、さらには3台以上のPWM電力変換器の並列運転装置に適用することもできる。
(1) Configuration of Device FIG. 1 shows a configuration of a parallel operation device for PWM power converters according to an embodiment of the present invention. This figure shows a case where cross current compensation and dead time compensation are used in combination with two three-phase PWM inverters, and is represented by a single line diagram. The same configuration can be applied to a parallel operation device of three or more PWM inverters, and further to a parallel operation device of three or more PWM power converters.

インバータ1、インバータ2の直流入力は直流電圧源PNであり、これを並列に接続する。インバータ1、2の出力は相間リアクトルL_mutで接続し、L_mutの中間タップから負荷に接続する。インバータ1、インバータ2それぞれの出力電流をI1、I2とし、負荷に供給される出力電流はIoである。ここで、電流制御に使用する検出電流をIdetとする。また、横流IcはI1、I2の偏差で表される。Idetは電流指令Icmdに追従するように電流制御を行う。電流制御部3は電圧指令値Vcmdを生成する。   The DC input of the inverter 1 and inverter 2 is a DC voltage source PN, which is connected in parallel. The outputs of the inverters 1 and 2 are connected by an interphase reactor L_mut, and are connected to a load from an intermediate tap of L_mut. The output currents of the inverters 1 and 2 are I1 and I2, respectively, and the output current supplied to the load is Io. Here, the detection current used for current control is Idet. Moreover, the cross current Ic is represented by the deviation of I1 and I2. Idet performs current control so as to follow the current command Icmd. The current control unit 3 generates a voltage command value Vcmd.

本実施形態のデッドタイム補償および横流補償は、デッドタイム生成によってパルス欠けを発生することを防止し、補償による遅延を最小にすることや、デッドタイム補償と横流補償を干渉させないために、PWM制御部からのゲート指令(PWM指令)に対するデッドタイム補償値、さらには横流補償値を加算するのではなく、並列インバータの共通の電圧指令値に各インバータのデッドタイム補償値の平均値を加算し、これに各インバータ別の横流補償値をそれぞれ加算してインバータ別の電圧指令値を生成する。よって、PWM制御部はインバータの並列台数分だけ設ける。本実施形態の場合、インバータは2台あるのでそれぞれのPWM制御部4A,4BをPWM1、PWM2とする。   The dead time compensation and the cross current compensation of this embodiment prevent the occurrence of missing pulses due to the dead time generation, minimize the delay due to the compensation, and prevent the dead time compensation and the cross current compensation from interfering with each other. Instead of adding the dead time compensation value for the gate command (PWM command) from the unit, and further the cross current compensation value, the average value of the dead time compensation value of each inverter is added to the common voltage command value of the parallel inverter, The cross current compensation value for each inverter is added to this to generate a voltage command value for each inverter. Therefore, the PWM control unit is provided for the number of inverters in parallel. In this embodiment, since there are two inverters, the PWM control units 4A and 4B are referred to as PWM1 and PWM2, respectively.

PWM1では電圧指令値Vcmd1’と三角搬送波Carrierを比較し、ゲート指令Gate1を生成し、同様にPWM2では電圧指令値Vcmd2’とCarrierを比較し、ゲート指令Gate2を生成する。デッドタイム生成部(DT1、DT2)10,11は、Gate1’およびGate2’を入力とし、デッドタイム期間Tdを有したスイッチング指令G1_U、G1_L、G2_U、G2_Lを出力する。これら信号はインバータ1、2の各相および上下アーム別のスイッチング指令であり、インバータ1.2の各相の上下アームになるスイッチング素子間にデッドタイムを持たせてオン・オフ動作させる。   In PWM1, the voltage command value Vcmd1 'and the triangular carrier wave Carrier are compared to generate the gate command Gate1, and similarly, in PWM2, the voltage command value Vcmd2' and Carrier are compared to generate the gate command Gate2. Dead time generators (DT1, DT2) 10, 11 receive Gate1 'and Gate2' as inputs, and output switching commands G1_U, G1_L, G2_U, G2_L having a dead time period Td. These signals are switching commands for each phase of the inverters 1 and 2 and the upper and lower arms, and are turned on / off with a dead time between the switching elements which are the upper and lower arms of each phase of the inverter 1.2.

(2)デッドタイム補償
デッドタイム補償について説明する。図2にデッドタイム補償のタイムチャートを示す。ただし、図2は片方のインバータ1のタイムチャートのみを示す。まず、ゲート指令Gate1と検出相電圧Vce1のオンタイムとオフタイムの誤差Vce_DLY1を計測する。デッドタイム補償部(DTC)6は、誤差時間計測値をデッドタイム補償に使用するため、誤差時間計測値を電圧指令値Vcmd[p.u.]と同じ単位(電圧)に変換したデッドタイム補償電圧Vdtc1[p.u.]を得る。このデッドタイム補償電圧Vdtc1は、PWM制御のキャリア生成部5が生成するキャリア信号の片振幅を1[p.u.]、キャリア周波数Fc[Hz]とすると下式の演算で求められる。
(2) Dead time compensation Dead time compensation will be described. FIG. 2 shows a time chart for dead time compensation. However, FIG. 2 shows only the time chart of one inverter 1. First, an error Vce_DLY1 between the on-time and off-time of the gate command Gate1 and the detection phase voltage Vce1 is measured. The dead time compensator (DTC) 6 uses the error time measurement value for the dead time compensation, and therefore uses the error time measurement value as the voltage command value Vcmd [p. u. ] Dead time compensation voltage Vdtc1 [p. u. ] Is obtained. This dead time compensation voltage Vdtc1 is obtained by setting the amplitude of one half of the carrier signal generated by the carrier generator 5 of PWM control to 1 [p. u. ], The carrier frequency Fc [Hz] is obtained by the following equation.

Vdtc1[p.u.]=2×Vce_DLY1[s]×2Fc[Hz]
同様に、デッドタイム補償部(DTC)6は、他方のインバータ2のゲート指令Gate2とオンタイムとオフタイムの誤差Vce2を検出し、デッドタイム補償電圧Vdtc2を求める。さらに、デッドタイム補償部(DTC)6は、インバータ2台分のVce_DLYが存在するので、それぞれのデッドタイム補償電圧Vdtc1,Vdtc2の平均をとり、それをデッドタイム補償電圧Vdtcとして出力する。
Vdtc1 [p. u. ] = 2 × Vce_DLY1 [s] × 2 Fc [Hz]
Similarly, the dead time compensation unit (DTC) 6 detects the gate command Gate2 of the other inverter 2 and the error Vce2 between the on time and the off time, and obtains the dead time compensation voltage Vdtc2. Furthermore, since there is Vce_DLY for two inverters, the dead time compensation unit (DTC) 6 takes the average of the respective dead time compensation voltages Vdtc1 and Vdtc2 and outputs it as the dead time compensation voltage Vdtc.

デッドタイム補償部(DTC)6からのデッドタイム補償電圧Vdtcは、デッドタイム補償前のGate1と補償後の検出相電圧Vce1が一致するように、電圧指令値Vcmdに重畳させる。この重畳は、次回のPWM制御のオン/オフの極性に応じて、各PWM電力変換器の共通の電圧指令値(Vcmd)に加減算するものであり、例えば、PWMキャリアが下降中はオンタイムのデッドタイム補償電圧Vdtcを加算し、PWMキャリアが上昇中はオフタイムのデッドタイム補償電圧Vdtcを減算する。これにより、デッドタイム補償前のGate1と補償後のVce1を一致させ、その誤差をほぼ零にしたデッドタイム補償が可能となる。   The dead time compensation voltage Vdtc from the dead time compensation unit (DTC) 6 is superimposed on the voltage command value Vcmd so that the Gate 1 before dead time compensation and the detected phase voltage Vce 1 after compensation coincide. This superposition is performed by adding / subtracting to / from the common voltage command value (Vcmd) of each PWM power converter according to the polarity of the next PWM control ON / OFF. The dead time compensation voltage Vdtc is added, and the off time dead time compensation voltage Vdtc is subtracted while the PWM carrier is rising. As a result, it is possible to perform dead time compensation in which Gate 1 before dead time compensation and Vce 1 after compensation are made to coincide with each other so that the error is substantially zero.

以上のように、本実施形態によるデッドタイム補償により、デッドタイム補償前のゲート指令Gateとデッドタイム補償後の相電圧検出値Vceの誤差をほぼ零にすることができ、デッドタイム補償後の遅延時間DTC_DLYを無くすことができる。これに伴い、最小オンパルス時間の制限を小さくすることができ、より細いPWMパルスが出力可能になる。また、より細いPWMパルスが出力可能であれば、インバータなどの電力変換器の最大出力電圧を大きくすることができる。また、PWMインバータの無駄時間が小さくなることで、電流制御および周波数制御の応答が向上する。また、電圧指令にデッドタイム補償値を重畳しているため、デッドタイム生成時にパルス欠けが発生することはない。   As described above, by the dead time compensation according to the present embodiment, the error between the gate command Gate before the dead time compensation and the phase voltage detection value Vce after the dead time compensation can be almost zero, and the delay after the dead time compensation. Time DTC_DLY can be eliminated. Accordingly, the limit on the minimum on-pulse time can be reduced, and a narrower PWM pulse can be output. If a narrower PWM pulse can be output, the maximum output voltage of a power converter such as an inverter can be increased. Moreover, the dead time of a PWM inverter becomes small, and the response of current control and frequency control improves. Further, since the dead time compensation value is superimposed on the voltage command, no missing pulse occurs when the dead time is generated.

また、相電圧検出部7は、従来の機構と変化ないため、デッドタイム補償部6のみを変更することで済む。   Further, since the phase voltage detection unit 7 does not change from the conventional mechanism, only the dead time compensation unit 6 needs to be changed.

さらに、デッドタイム補償により、出力電流の6f成分を小さくすることができる。図4(a)は、インバータに誘導性負荷を接続した試験での従来装置における電流波形を示し、図4(b)は本実施形態によるデッドタイム補償を適用した場合の電流波形を示す。これら波形図から、本実施形態によるデッドタイム補償によって、図4(a)の波形と比較して図4(b)のように電流のひずみが低減していることが確認できた。   Furthermore, the dead time compensation can reduce the 6f component of the output current. FIG. 4A shows a current waveform in a conventional apparatus in a test in which an inductive load is connected to an inverter, and FIG. 4B shows a current waveform when the dead time compensation according to the present embodiment is applied. From these waveform diagrams, it was confirmed that the current distortion was reduced as shown in FIG. 4B compared to the waveform of FIG. 4A by the dead time compensation according to the present embodiment.

(3)横流補償
横流補償について説明する。図3に横流補償のタイムチャート示す。ここで、図3は説明簡略化のためにデッドタイム補償電圧Vdtc=0の場合を示す。
(3) Cross current compensation Cross current compensation will be described. FIG. 3 shows a time chart for cross current compensation. Here, FIG. 3 shows a case where the dead time compensation voltage Vdtc = 0 for simplification of explanation.

横流制御部(Balance ACR)9は、インバータ1、2の出力電流I1、I2の偏差(横流値Ic)を比例積分(PI)演算し、各PWMインバータの共通の電圧指令値(Vcmd)と同じ単位の横流補償値Vcccとして求める。この横流補償値Vcccは、横流値Icが零になるように、デッドタイム補償後の電圧指令値Vcmd’に加算してインバータ1の電圧指令値Vcmd1’とし、デッドタイム補償後の電圧指令値Vcmd’から減算してインバータ2の電圧指令値Vcmd2’とする。これにより、2つのインバータ1,2の電圧は横流が発生しない方向に偏差が生まれるので、横流は小さくなる。   The cross current control unit (Balance ACR) 9 performs a proportional integral (PI) operation on the deviation (cross current value Ic) of the output currents I1 and I2 of the inverters 1 and 2, and is the same as the common voltage command value (Vcmd) of each PWM inverter. It is obtained as a cross current compensation value Vccc in units. The cross current compensation value Vccc is added to the voltage command value Vcmd ′ after the dead time compensation so that the cross current value Ic becomes zero to obtain the voltage command value Vcmd1 ′ of the inverter 1, and the voltage command value Vcmd after the dead time compensation. By subtracting from ', the voltage command value Vcmd2' of the inverter 2 is obtained. As a result, the voltages of the two inverters 1 and 2 are deviated in a direction in which no cross current is generated, so that the cross current becomes small.

以上までに説明したデッドタイム補償電圧Vdtcと横流補償電圧Vcccは、デッドタイム補償後電圧指令値Vcmd’、横流補償後電圧指令値Vcmd1’、Vcmd2’とは下式の関係になる。   The dead time compensation voltage Vdtc and the cross current compensation voltage Vccc described above have the following relationship with the dead time compensated voltage command value Vcmd 'and the cross current compensated voltage command values Vcmd1' and Vcmd2 '.

Vcmd’=Vcmd+Vdtc
Vcmd1’=Vcmd’+Vccc
Vcmd2’=Vcmd’+Vccc
以上のように、本実施形態による横流補償により、横流補償前のゲート指令Gate’と横流補償後のゲート指令Gate1’、Gate2’の遅延時間CCC_DLYをほぼ零にでき、この横流補償による遅延時間CCC_DLYを無くすことができる。これに伴い、最小オンパルス時間の制限を小さくなることができ、より細いPWMパルスが出力可能になる。また、より細いPWMパルスが出力可能であれば、インバータなどの電力変換器の最大出力電圧を大きくすることができる。また、PWMインバータの無駄時間が小さくなることで、電流制御および周波数制御の応答が向上する。また、電圧指令に横流補償値を重畳しているため、横流補償によりパルス欠けが発生することはない。また、横流制御部9は従来の機構と変化ないため、横流補償部8のみを変更することで済む。
Vcmd '= Vcmd + Vdtc
Vcmd1 ′ = Vcmd ′ + Vccc
Vcmd2 ′ = Vcmd ′ + Vccc
As described above, by the cross current compensation according to the present embodiment, the delay time CCC_DLY of the gate command Gate ′ before the cross current compensation and the gate commands Gate1 ′ and Gate2 ′ after the cross current compensation can be made substantially zero, and the delay time CCC_DLY by this cross current compensation Can be eliminated. Along with this, the limit of the minimum on-pulse time can be reduced, and a narrower PWM pulse can be output. If a narrower PWM pulse can be output, the maximum output voltage of a power converter such as an inverter can be increased. Moreover, the dead time of a PWM inverter becomes small, and the response of current control and frequency control improves. In addition, since the cross current compensation value is superimposed on the voltage command, no pulse missing occurs due to the cross current compensation. Further, since the cross flow control unit 9 is not different from the conventional mechanism, only the cross flow compensation unit 8 needs to be changed.

さらに、横流補償により、出力電流のひずみを小さくすることができる。図4(c)は本実施形態による横流補償を適用した場合の電流波形を示し、図4(a)の波形と比較して図4(c)のように電流のひずみが低減していることが確認できた。   Further, the distortion of the output current can be reduced by the cross current compensation. FIG. 4C shows a current waveform when the cross current compensation according to the present embodiment is applied, and the distortion of the current is reduced as shown in FIG. 4C compared to the waveform of FIG. Was confirmed.

(4)デッドタイム補償と横流補償の併用
前記まではデッドタイム補償と横流補償を個別に適用した場合の作用効果を説明したが、デッドタイム補償と横流補償を同時に適用することで相乗効果を得ることができる。
(4) Combined use of dead time compensation and cross current compensation Up to this point, the effects of applying dead time compensation and cross current compensation individually have been described, but a synergistic effect is obtained by applying dead time compensation and cross current compensation simultaneously. be able to.

例えば、デッドタイム補償および横流補償を電圧指令に同時に重畳する場合は、各々の補償の非干渉化が可能になる。図4(d)は、図1の構成によるデッドタイム補償および横流補償を同時に適用した場合の電流波形を示し、デッドタイム補償および横流補償は互いに干渉せず、図4(b)、(c)の補償効果を有していることが確認できた。   For example, when dead time compensation and cross current compensation are simultaneously superimposed on the voltage command, each compensation can be made non-interfering. FIG. 4D shows a current waveform when dead time compensation and cross current compensation according to the configuration of FIG. 1 are applied simultaneously, and the dead time compensation and cross current compensation do not interfere with each other, and FIGS. It was confirmed that it has a compensation effect.

1、2 インバータ
3 電流制御部
4,4A,4B PWM制御部
5 キャリア生成部
6 デッドタイム補償部
7 相電圧検出部
8 横流補償部
9 横流制御部
10、11 デッドタイム生成部
DESCRIPTION OF SYMBOLS 1, 2 Inverter 3 Current control part 4, 4A, 4B PWM control part 5 Carrier generation part 6 Dead time compensation part 7 Phase voltage detection part 8 Cross current compensation part 9 Cross current control part 10, 11 Dead time generation part

Claims (2)

複数台のPWM電力変換器の出力を並列接続し、各PWM電力変換器間の横流補償手段と各PWM電力変換器のデッドタイム補償手段を有して各電力変換器を同期運転するPWM電力変換器の並列運転装置であって、
前記デッドタイム補償手段は、各PWM電力変換器の相電圧(Vce)を検出する相電圧検出部と、各PWM電力変換器別のPWM制御部からのPWM指令(Gate)と前記相電圧(Vce)のオン時間の誤差時間を検出、およびPWM指令(Gate)と相電圧(Vce)のオフ時間の誤差時間を検出し、これら検出した誤差時間を各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位のデッドタイム補償電圧(Vdtc)としてそれぞれ変換し、これらデッドタイム補償電圧を各PWM電力変換器の次回のPWM制御のオン/オフの極性に応じて、各PWM電力変換器の共通の電圧指令値(Vcmd)に加減算するデッドタイム補償部を備え、
前記横流補償手段は、各PWM電力変換器間の横流(Ic)を検出し、各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位の横流補償値(Vccc)として求め、この横流補償値(Vccc)を前記横流(Ic)の値に応じて一方のPWM電圧指令値に加算し、他方のPWM電圧指令値から減算する横流制御部を備えたことを特徴とするPWM電力変換器の並列運転装置。
PWM power conversion in which outputs of a plurality of PWM power converters are connected in parallel, and each power converter is operated synchronously by having a cross current compensation means between the PWM power converters and a dead time compensation means of each PWM power converter. A parallel operation device for a vessel,
The dead time compensation means includes a phase voltage detector that detects a phase voltage (Vce) of each PWM power converter, a PWM command (Gate) from a PWM controller for each PWM power converter, and the phase voltage (Vce). ) And the PWM command (Gate) and the off time of the phase voltage (Vce) are detected, and the detected error time is used as a common voltage command value for each PWM power converter ( Vmd) is converted as a dead time compensation voltage (Vdtc) in the same unit, and these dead time compensation voltages are converted into the PWM power converters according to the polarity of the next PWM control on / off of each PWM power converter. A dead time compensator for adding and subtracting to a common voltage command value (Vcmd);
The cross current compensation means detects the cross current (Ic) between the PWM power converters, obtains the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter, A PWM power converter comprising a cross current control unit that adds a compensation value (Vccc) to one PWM voltage command value in accordance with the value of the cross current (Ic) and subtracts it from the other PWM voltage command value Parallel operation device.
複数台のPWM電力変換器の出力を並列接続し、各PWM電力変換器間の横流補償と各PWM電力変換器のデッドタイム補償をして各電力変換器を同期運転するPWM電力変換器の並列運転方法であって、
前記デッドタイム補償は、相電圧検出部が各PWM電力変換器の相電圧(Vce)を検出し、デッドタイム補償部が、各PWM電力変換器別のPWM制御部からのPWM指令(Gate)と前記相電圧(Vce)のオン時間の誤差時間を検出、およびPWM指令(Gate)と相電圧(Vce)のオフ時間の誤差時間を検出し、これら検出した誤差時間を各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位のデッドタイム補償電圧(Vdtc)としてそれぞれ変換し、これらデッドタイム補償電圧を各PWM電力変換器の次回のPWM制御のオン/オフの極性に応じて、各PWM電力変換器の共通の電圧指令値(Vcmd)に加減算し、
前記横流補償は、横流制御部が、各PWM電力変換器間の横流(Ic)を検出し、各PWM電力変換器の共通の電圧指令値(Vcmd)と同じ単位の横流補償値(Vccc)として求め、この横流補償値(Vccc)を前記横流(Ic)の値に応じて一方のPWM電圧指令値に加算し、他方のPWM電圧指令値から減算することを特徴とするPWM電力変換器の並列運転方法。
Parallel output of PWM power converters that connect the outputs of multiple PWM power converters in parallel, perform cross current compensation between each PWM power converter and dead time compensation of each PWM power converter, and operate each power converter synchronously Driving method,
In the dead time compensation, the phase voltage detection unit detects the phase voltage (Vce) of each PWM power converter, and the dead time compensation unit receives the PWM command (Gate) from the PWM control unit for each PWM power converter. The error time of the ON time of the phase voltage (Vce) is detected, and the error time of the PWM command (Gate) and the OFF time of the phase voltage (Vce) is detected, and these detected error times are common to each PWM power converter. Is converted as a dead time compensation voltage (Vdtc) in the same unit as the voltage command value (Vcmd), and the dead time compensation voltage is changed according to the on / off polarity of the next PWM control of each PWM power converter. Addition / subtraction to the common voltage command value (Vcmd) of the PWM power converter,
In the cross current compensation, the cross current control unit detects the cross current (Ic) between the PWM power converters, and uses the cross current compensation value (Vccc) in the same unit as the common voltage command value (Vcmd) of each PWM power converter. This parallel current compensation value (Vccc) is added to one PWM voltage command value in accordance with the value of the cross current (Ic) and subtracted from the other PWM voltage command value. how to drive.
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