JPH0795773A - Dead time compensating circuit - Google Patents

Abstract

PURPOSE:To raise a carrier frequency so that the distortion of a current waveform can be reduced even when a dead time compensating circuit is operated in a low-frequency domain. CONSTITUTION:At the time of adjusting the pulse width of PWM waveform signals of each phase generated from a PWM waveform generating section 11 by means of a dead time compensating section 12, a voltage detecting section 16 detects the turning on/off timing of the phase output voltage VCE of an inverter main body 15 and, by switching the detecting reference value for the signal detection in accordance with turning on/off polarity of the gate reference signal of PWM waveforms, the zero clamp of the output current of the inverter 15 is eliminated by adding dead time to the output current.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dead time compensation circuit in a PWM power conversion device such as a PWM inverter device.

[0002]

2. Description of the Related Art Inverters, converters, and power converters such as choppers obtain waveform improvement and power factor improvement by PWM control.

FIG. 5 shows a PWM inverter configuration example.
Inverter body 2 which uses the DC output of the rectifier 1 as a DC power supply
Is a three-phase bridge configuration of transistors, each transistor is on / off controlled by a gate signal according to a PWM waveform from the PWM circuit 3, an AC output whose voltage and frequency are controlled is obtained, and the induction motor 4 serving as a load Supply. The speed control unit 5 obtains voltage and frequency control outputs by comparing the speed setting value and the speed detection value of the electric motor 4.

Here, the PWM circuit 3 is subjected to a dead time waveform processing to form a PWM waveform with dead time added so that the upper arm and the lower arm of the inverter body 2 do not turn on (short circuit) at the same time.

FIG. 6 shows ON / OFF waveforms of the upper and lower arms in which a dead time Td is added to an ideal PWM waveform.

In the inverter with such dead time added, the presence of the dead time Td causes the output current waveform to be distorted in low frequency operation of the inverter.

In order to prevent this effect, a dead time compensation function is added and the current waveform is improved. This compensation method detects each phase voltage V _CE of the inverter main body 2 and performs dead time compensation, but a current zero clamp phenomenon occurs at the zero cross point of the current due to the influence of the residual voltage of the electric motor 4.

As a countermeasure against this, by detecting the timing when the phase voltage (ON / OFF) output of the inverter body 2 becomes 1/2 of the DC voltage, the PWM waveform is corrected,
A method has been proposed in which the influence of the residual voltage is set to an intermediate potential to eliminate the distortion of the current waveform. For example, JP-A-4-
69066 publication.

[0009]

When switching the main circuit element of the inverter body from the transistor to the IGBT,
The IGBT has a short switching time, and the carrier wave frequency for generating the PWM waveform is also increased to make the output waveform closer to a sine wave.

However, as the carrier frequency increases,
The effect of dead time cannot be ignored. That is, PWM
The shorter the cycle, the larger the ratio of the dead time to the PWM cycle, and the larger the waveform distortion at the zero cross point.

FIG. 7 shows the operating frequency of the inverter = 5.
The output current waveform of H _Z and carrier frequency = 5 KH _Z is shown. As described above, when the carrier frequency is increased, the current causes the zero clamp phenomenon at the zero cross point, and the current waveform is distorted.

It is an object of the present invention to provide a dead time compensating circuit which reduces the distortion of the current waveform even when operating in a low frequency region with a high carrier frequency.

[0013]

In order to solve the above-mentioned problems, the present invention detects the on / off timing of the phase voltage output of the main circuit and detects the error between this detection signal and the on / off control waveform of the main circuit. In a PWM power conversion device including a voltage detection unit that obtains a minute as a pulse width and a dead time compensation unit that compensates the on / off control waveform with the error component, the voltage detection unit is configured to provide a phase voltage of the main circuit. It is characterized in that the detection reference when the output changes from the low level to the high level and the detection reference when the output changes from the high level to the low level are detected with different values.

[0014]

According to the experiments, it has been clarified that when the detection reference for detecting the on / off timing of the main circuit is individually changed, the output current waveform has a certain regularity and waveform distortion occurs.

FIG. 8 shows current waveforms when the detection reference Vref of the phase voltage output of the inverter device is larger than 1/2 of the DC voltage Edc (a), when it is the same (b) and when it is smaller (c). .

As is clear from the figure, in the case of the conventional method (b), the current is symmetrical and the harmonics are reduced, but the waveform has distortion. On the other hand, in the case of (a) in which the detection reference is increased, waveform distortion occurs at the zero crossing point of the current fall, and the rise is a smooth change. On the contrary, the detection standard was lowered (c)
In the case of, the waveform distortion occurs at the zero crossing point of the rising edge of the current, and the falling edge becomes a smooth change.

In view of the above phenomenon, the present invention detects the current at the zero-cross point side where no waveform distortion occurs by performing detection and dead time compensation by changing the detection reference according to the polarity of the change in the phase voltage. obtain.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of essential parts showing an embodiment of the present invention. P of each phase generated by the PWM waveform generator 11
The dead time compensating unit 12 adjusts the pulse width of the WM waveform signal, the dead time adding unit 13 adds a dead time of a fixed width, and the base drive unit 14 outputs the gate signal for each arm. A main circuit of the inverter body 15 is formed by using the IGBT as a switching element.

The dead time compensation by the dead time compensator 12 is performed by the voltage detector 16 detecting the on / off timing of the output voltage V _CE of the inverter body 15. This detection is performed as a pulse width for dead time compensation, and the gate reference signal of the PWM waveform is used as a reference voltage switching signal. For detection, the detection reference voltage is obtained from the DC voltage of the inverter main circuit.

FIG. 2 shows a circuit diagram of the voltage detector 16 for only one phase. The voltage V _CE supplied from the inverter body 15 to the induction motor 4 is taken out as a signal by the resistance voltage dividing circuit 21 and given as a comparison input to the pair of comparators 22 and 23.

Comparison reference V of both comparators 22 and 23
_{The ref1} and _Vref2 are set as voltages that are proportional to and different from the DC voltage Edc of the inverter body 15 by the resistance voltage dividing circuit 24. Here, the comparison reference V _ref1 is the voltage Edc.
Is set to ⅓ lower than 1/2 and the comparison reference V _ref2 is set to ⅔ higher than ½ of the voltage Edc.

Such setting conditions and the comparator 2
By setting the input polarities of 2 and 23, a high level is obtained at the output of the comparator 22 when the voltage V _CE is equal to or lower than the comparison reference V _ref1 , and an output inverted to a low level is obtained when the voltage V _CE is exceeded.

On the contrary, when the voltage V _CE is equal to or higher than the comparison reference V _ref2 , the output of the comparator 23 obtains a high level, and when it becomes a low level exceeding it, an output inverted to a low level is obtained.

Both outputs of the comparators 22 and 23 are taken out as signals insulated by the photocouplers 25 and 26, respectively, and input to one of the AND gates 27 and 28.

The AND gate 27 takes the logical product of the gate reference signal of the PWM waveform and the output of the comparator 25.
The AND gate 28 takes the logical product of the output of the logic inverter 29 which is the inverted gate reference signal and the output of the comparator 26. The switching of the detection reference is obtained by the logical product of the AND gate and the PWM waveform.

The outputs of the AND gates 27 and 28 are ORed by the OR gate 30 and used as the detection signal of the voltage V _CE .

The voltage detecting section 16 having the above-mentioned configuration is
The operation waveform shown in FIG. 3 is obtained, and the output pulse of the OR gate 30 is given to the dead time compensator 12. The dead time compensator 12 suppresses waveform distortion by increasing or decreasing the leading edge and the trailing edge of the PWM reference gate signal according to the V _CE detection signal.

[0028] Figure 4 shows the current waveform of an experiment based on the present embodiment, the operating frequency 5H _Z, Te placed PWM inverter at the carrier frequency 15KH _Z, with a reduced both waveform distortion rising and falling of the current A waveform close to a sine wave was obtained.

FIG. 9 is a circuit diagram of a voltage detecting section showing another embodiment of the present invention. . The difference between FIG. 2 and FIG. 2 will be described. The resistance dividing circuit 24A has a one-level comparison reference V
_ref1 is obtained, for example, 1 lower than 1/2 of the DC voltage Edc
/ 3.

The comparator 31 has a positive feedback resistor 31A and is configured as a hysteresis comparator. The comparison reference V _ref1 and the detection signal from the resistance voltage dividing circuit 21 have a hysteresis characteristic and are switched to a low level and a high level. .

The photocoupler 32 takes out the output of the comparator 31 as an insulated signal and outputs it to the AND gate 27.
A gate signal is provided to the AND gate 28 in the opposite phase by the logic inverter 33.

In the voltage detection circuit of the present embodiment, the comparator 31 has a hysteresis comparator configuration, so that detection of the voltage V _CE equivalent to the configuration of FIG. 2 having a two-level comparison reference can be obtained.

That is, the comparator 31 inverts the output when the voltage V _CE shown in FIG. 3 exceeds the comparison reference V _ref1 , and then inverts the output when the voltage V _CE becomes lower than the comparison reference V _ref2. You can get a signal. At this time, the hysteresis width is set to the difference between the comparison reference V _ref1 and V _ref2 .

The output of the comparator 31 is inverted by the logic inverter 33 to obtain a logical product with the gate reference signal, thereby obtaining a voltage detection signal when the voltage V _CE exceeds the comparison reference V _ref1 and V _ref2. Become.

This embodiment has the effect of simplifying the circuit configuration, such that one comparator and photocoupler are sufficient as compared with the one shown in FIG. 2 which requires two comparators and photocouplers per phase. .

In the above-mentioned embodiments, the case where the detection reference is switched by the PWM gate reference signal has been described, but this can be switched depending on the polarity of the output current to achieve the same effect.

Further, in the embodiment, the case of the PWM inverter device is shown, but it is needless to say that the present invention can be applied to a power conversion device such as a converter or a chopper for PWM control.

[0038]

As described above, according to the present invention, the voltage detection of the main circuit is performed by the detection reference when the phase voltage output changes from the low level to the high level and when the phase voltage output changes from the high level to the low level. Since the dead time compensation is performed by detecting a value different from the detection reference of No. 1, there is an effect that the distortion of the output current waveform is reduced even at a low operating frequency in the PWM power conversion device in which the carrier frequency is increased.

Further, the present invention has the effect of simplifying the voltage detection circuit because the voltage detection with different detection reference is obtained by the comparator having the hysteresis characteristic.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a voltage detector in the embodiment.

FIG. 3 is a waveform diagram of a voltage detector.

FIG. 4 is a current waveform diagram in the example.

FIG. 5 is a configuration example of an inverter device.

FIG. 6 is a dead time compensation waveform diagram.

FIG. 7 is a conventional current waveform diagram.

FIG. 8 is a current waveform diagram when the detection reference is changed.

FIG. 9 is another circuit diagram of the voltage detection unit in the embodiment.

[Explanation of symbols]

 11 ... PWM waveform generating section 12 ... Dead time compensating section 13 ... Dead time adding section 15 ... Inverter main body 16 ... Voltage detecting section 22, 23 ... Comparator 31 ... Hysteresis characteristic comparator

Claims (4)

[Claims] 1. A voltage detecting section for detecting an on / off timing of a phase voltage output of a main circuit and obtaining an error component between the detection signal and an on / off control waveform of the main circuit as a pulse width, and the on / off control. In the PWM power conversion device including a dead time compensating unit that compensates a waveform with the error component, the voltage detecting unit includes a detection reference when the phase voltage output of the main circuit changes from a low level to a high level. A dead time compensation circuit, which detects a detection reference at the time of changing from a high level to a low level with a different value. 2. The dead time compensation circuit according to claim 1, wherein the detection reference is set according to the DC voltage of the main circuit. 3. The dead time compensation circuit according to claim 1, wherein the detection reference is switched according to a PWM reference signal or an output current polarity of the main circuit. 4. The voltage detecting unit according to claim 1, wherein the phase voltage output and the on / off control waveform are compared by a comparator having a hysteresis characteristic to obtain detection by different detection standards. Dead time compensation circuit.