KR940002232Y1 - Pulse width modulation type inverter having temperature compensation - Google Patents

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Description

Pulse Width Modulated Inverter with Temperature Compensation

1 is a block diagram of an inverter device according to an embodiment of the present invention.

2 is a block diagram of an inverter device according to another embodiment of the present invention.

3 is a diagram showing the relationship between the temperature and the carrier frequency of the control element of FIG.

4 shows the relationship between the output frequency and carrier frequency of FIG.

5 is a block diagram of a circuit used in the present invention for varying the carrier frequency by the output frequency or the temperature of the control element.

6 and 7 are waveform charts showing reference voltages and carrier frequencies in the inverter device of the present invention.

8 is an explanatory diagram of a clock switching circuit used in the present invention.

9 is a chart showing the relationship between the temperature, the output voltage and the carrier frequency of the control element of the present invention.

10 is a block diagram of a conventional inverter device.

11A to 11A are waveform configuration diagrams showing a relationship between a reference voltage, a carrier, and a PWM signal of a conventional inverter device.

12 is a simplified operation diagram of a conventional inverter device.

13 is a block diagram of an inverter device according to another embodiment of the present invention.

FIG. 14 illustrates the relationship between the output frequency and the carrier frequency of FIG. 13; FIG.

FIG. 15 is a chart illustrating an algorithm used to change carrier frequency at the base of temperature.

16 is a diagram for explaining changes in frequency and temperature in time.

FIG. 17 is a flowchart illustrating an algorithm used to change the carrier frequency at the base of the output current.

* Explanation of symbols for main parts of the drawings

100: DC power supply 200: reverse converter

300: motor 400: reference voltage generator

500: carrier generator 900: output frequency setter

The present invention relates to a pulse width modulated inverter that obtains an alternating current of variable voltage and variable frequency, and in particular, an inverter using a high carrier frequency (hereinafter referred to as a "PWM" signal). ) Control.

10 shows a configuration example of a conventional PWM inverter.

Referring to the drawings, the known PWM inverter includes an inversion converter in which the DC power supply 100 is configured with a controllable element and a pair of inverse parallel-connected diodes. ).

The reversing converter can convert a direct current into an alternating current of variable voltage and variable frequency and can be used to drive the motor 300, or such a device.

The reference voltage generator 400 outputs a reference voltage waveform used as a reference of the output frequency and the output voltage.

In practice, the waveform of the reference voltage has an optimal shape for operating the motor, but the waveform of such shape cannot be obtained with a suitable power source where commercial power is not available.

Therefore, the carrier waveform with the appropriate power source is mixed with the reference wave, resulting in a pulsed waveform with the same area as the reference voltage wave suitable for driving the electric motor or the like.

This reference waveform is transformed (modified) in response to the input provided by the user-settable output frequency setter 900.

A suitable carrier generator 500 forms, for example, a triangular waveform carrier waveform at a certain frequency fc.

The PWM circuit 600 is operated in response to the signals provided by the reference voltage generator 400 and the carrier generator 500 to generate control signals of the control element of the inverting converter 200.

The driving circuit 700 drives the provisional control element of the inverting converter 200 in response to the signals provided from the PWM circuit 600 and the output frequency setter 900.

Some waveforms generated during the typical PWM operation of the operation of the known inverter will be described with reference to FIG.

In generating a three-phase AC power supply for operating a device such as an electric motor or the like, it is worth noting the example of one of the three phases (U, V, W) suitable for actual inverter operation, in particular, the "U phase".

Referring to FIG. 11A, the triangular waveform output of the carrier generator 500 and the sinusoidal waveform output of the reference voltage generator 400 are superimposed in the same frame.

The superimposed waveform describes a comparison between a reference voltage used as a reference of the output voltage and the output frequency of the inverter and a signal for modulating the reference voltage, for example, a triangular carrier waveform.

The waveform of FIG. 11B is generated at the point where the reference voltage waveform and the carrier cross in the waveform of FIG. 11A.

One of the waveforms in FIG. 11B is the PWM signal U _PO .

This signal is generated on the upper side of the U phase, and the signal is turned on in a period in which the reference voltage is higher than the carrier voltage, and turned off in a period in which the reference voltage is lower than the carrier voltage.

Another waveform in FIG. 11B is the PWM signal U _NO . This signal is generated for the lower side of U and is obtained as the inversion of the signal U _PO .

The control element is actually driven by the PWM signals U _PO , U _NO as shown in FIG. 11C and the signals are subjected to a short circuit prevention process which causes the timing of the ON pulse to be delayed by the time duration period Td. It is formed from the dependent waveforms U _PO , U _NO .

The pulse width modulated output voltage obtained as the U phase output as a result of this delay is shown in FIG. By the same method, the V and W phases are obtained in the same way.

Again, referring to FIG. 10, the reference voltage waveform shown in FIG. 11A, which provides a reference of the output frequency and the output voltage, is delivered by the reference voltage waveform generator 400. In FIG. The triangular carrier wave shown in FIG. 11A is generated by the carrier generator 500.

The PWM circuit 600 responds to the waveform of FIG. 11A and generates the PWM signal shown in FIG. 11C. The driving circuit 700 amplifies the output of the PWM circuit 600 and drives the provisional control element of the inverting converter 200.

Since the drive signal changes with a change in the reference voltage waveform, an AC current is obtained at the inverter by the variable voltage and the variable frequency.

When the motor is driven with this PWM waveform, harmonics at the audible level are generated due to the carrier frequency. These audible signals increase the level of noise in the working environment.

One means to circumvent this problem is to increase the carrier frequency above or above the upper limit of the human audible frequency range (15 KHz). The level of noise gradually decreases as the carrier frequency is increased.

In fact, when the carrier frequency is in the range of 10KHz to 15KHz, the noise frequency approaches the upper limit of the audible frequency range and the noise level is lowered.

When the carrier frequency is increased beyond 20KHz, the audible range is exceeded so that harmonics are undetectable to human hearing. As a result, the noise level is reduced approximately equal to the level generated when driven by commercial power.

In order to obtain a high carrier frequency accompanied by low noise, high speed switching elements such as power MOSFETs, 1GBT, etc., operable at frequencies between 10 and 20 KHz are used.

The drawback in such a design is that switching is inevitably accompanied by a negligible amount of power loss. Further, the loss P generated by the control element carried by the antiparallel diode is given by the following equation.

P = P _ON + P _SW

= Normal Loss + Switching Loss

= P _ON (1) + P _SW (fc, I). (One)

The "normal loss" is the product of the current and the voltage drop quotient (minutes) at normal ON, and the "switching loss" is the product of the voltage and current at the ON and OFF of the control element.

As a simplified function type, as shown in Equation (1), the total normal loss (P _ON ) is a function of the current level (I) and the total switching loss (P _SW ) is the current level (I) that controls the switching of the device. ) And carrier frequency (fc). The switching loss P _SW is increased when the carrier frequency fc is increased. Again, the ratio of losses P _ON : P _SW is large when the current is near the level of the inverter's rated current.

When the inverter operation results in relatively high switching losses, ie high fc and high current, adequate cooling is required because the proper thermal design of the switching elements requires the junction temperature of the elements to be kept below acceptable values.

The operation of the inverter at high carrier frequencies thus reduces audible noise but increases the coolable output and the size of the inverter. The noise generated when the inverter drive motor runs at low speeds poses a serious problem.

At low speed of the motor, the noise generated by the load driven by the motor is relatively low and the noise of the motor tends to prevail. At high speeds of the motor, the noise generated by the load driven by the motor increases so that harmonics generated by the motor do not prevail and their effects are not a problem.

Nevertheless, in the conventional inverter, when the speed of the motor is increased, fc is maintained to increase the loss due to the high switching loss.

In order to meet the thermal demands of the switching elements, conventional inverters must be designed to maintain the temperature of the switching elements under the highest permissible temperature. Clearly, when the ambient temperature is low, the inverter can safely operate (run) even when fc remains high due to increased load.

However, when the ambient temperature starts to rise, the most effective parameter that can include the temperature under the highest permissible temperature of the switching element is the carrier frequency (fc). It is difficult to effectively suppress the generation of audible noise if the carrier frequency fc is reduced to reduce the temperature rise due to switching power loss.

The present invention has been proposed to solve the above problem of the prior art.

Thus, it is an object of the present invention to provide an inverter device which can operate at a low level of audible noise and which can compensate for an increase in loss without increasing the size of the inverter or installing special cooling.

Another object of the present invention is to control the carrier frequency according to the inverter output frequency or the temperature or output current of the control element so that the generation of noise is suppressed and the power loss is reduced.

In the inverter device of the present invention, the carrier frequency ranges between the upper limit carrier frequency (fcmax) determined by the response time and the generation loss of the inverter, and the lower limit carrier frequency (fcmin) determined by the distortion of the output noise characteristic and the output current. Is variable within.

The carrier frequency is controlled in accordance with the temperature of the control element of the inverter device in such a way that when the detected temperature of the control element increases and decreases respectively the carrier frequency is reduced and increased.

Preferably the carrier frequency is controlled in accordance with the output frequency of the inverter device in such a way that the carrier frequency is reduced and increased respectively when the inverter frequency is increased and decreased.

The carrier frequency is also controlled in accordance with the output current of the inverter device in such a way that the carrier frequency is increased and decreased, respectively, when the inverter output current is increased and decreased.

The carrier generator in the inverter device of the present invention determines the carrier frequency according to the output current or output frequency of the inverter or the temperature of the control element of the inverter.

In particular, the carrier frequency is increased when the detected temperature or the speed of the motor is low or the inverter output current is small to suppress voice generation, while the carrier frequency is increased when the detected temperature or the motor speed is increased or the inverter output current is large. It is reduced to reduce the loss generated in the control element.

EXAMPLE

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.

Referring to FIG. 1, reference numerals 100, 200, 300, 400, 600, 700 and 900 denote elements which are the same as or similar to those indicated by the reference numerals of FIG. 10 with reference to known inverter devices.

Reference numeral 800 denotes a temperature detector for detecting the temperature of the control element and reference numeral 500 denotes a carrier generator for generating a signal of variable frequency fc in response to the output of the temperature detector 800.

The carrier frequency fc is a linear method as shown in FIG. 3 within a range between the predetermined frequency limit fcmax and fcmin in response to a change in temperature To as indicated by the output at the temperature detector 800. Is controlled.

As a result, the carrier, ie the triangular waveform, is provided to the PWM circuit at a controlled carrier frequency fc.

2 shows another embodiment of the present invention.

The elements of this embodiment are substantially the same as that shown in FIG. 1 except that the temperature detector is removed and the carrier generator 500 receives the input provided by the inverter output frequency setter 900 instead.

The carrier frequency fc is controlled by the linear method shown in FIG. 4 within a range between the predetermined frequency limit fcmax and fcmin in accordance with the change of the output frequency fo.

The output frequency is set by the operator between the upper limit (f _OH ) and the lower limit (f _OC ) (30 Hz, 40 Hz, 60 Hz, etc.) and the carrier frequency (fc) is typically between the lower eye fcmin and the upper limit fcmax from 15 KHz to 20 KHz. Determined based on inverse relationship.

12 shows a third embodiment in which the carrier frequency is controlled in accordance with the output at the current detector 1000 which can detect the load current of the inverter within the range of low current I _OC high current I _OH . .

The carrier frequency is shown in FIG. 13 (typically from 15 KHz to 20 KHz) and has a reverse linear relationship with the current within a range between the predetermined frequencies fcmax and fcmin.

The current detector 1000 may use a DCCT current detector using a Hall element. Although the current detector 1000 is installed at the output side of the inverter in FIG. 13, this is only an example, and the current detector 1000 may be provided at any place capable of detecting a current corresponding to the output current of the inverter.

Details of changes in carrier frequencies fcmin to fcmax for changes in detection temperature To, output frequency fo, and load current Io as shown in FIGS. 3, 4 and 13 will be described.

As mentioned above, it is recalled that the motor which is the load of the inverter device generates harmonic noise due to the carrier frequency fc.

The effect of this noise can be avoided by increasing the carrier frequency fc at a level higher than the range of the audible frequency.

However, such countermeasures create a risk that the temperature To of the control element exceeds the allowable upper limit and greatly increases the loss of the control element.

The temperature To of the control element is

To = Ta + T... … (2)

Is indicated by.

Where Ta denotes the ambient temperature of the inverter device, and T denotes the temperature rise of the control element itself.

The temperature rise (T)

T = P × Rth... … (3)

Where P is the generation loss of the control element, and Rth is the thermal resistance comprising the control element and its cooling body.

As described above, the generation loss P in the control element can be expressed by the normal loss P _ON and the switching loss P _SW , and the normal loss P _ON is a function of the output current Io. On the other hand, switching loss P _SW is expressed as a function of the output current Io and the carrier frequency fc.

The loss P is converted in correspondence with the current power PL supplied to the load by the inverter, i.e., when the power PL is small, the generated loss P is also small.

In general, the reduction of the energy consumption by reducing the power PL supplied to the load by reducing the output frequency fo of the inverter exists as one purpose of using the inverter device of the type described above.

Therefore, it is also possible to reduce the generation loss P by lowering the output frequency fo and the generation loss P can be expressed as a function of the output frequency fo.

In summary, the temperature To of the control element is expressed as follows.

To = Ta + {P _ON (Io, fo) + P _SW (Io, fc)} x Rth. … (4)

As can be understood in the implantation, the temperature To of the control element is determined when the ambient temperature Ta, the output current Io, the output frequency fo and the carrier frequency fc of the inverter device are provided.

The parameters (items) except the carrier frequency fc are determined by the condition and environment of the side where the inverter device is used, and thus cannot be controlled by the inverter device itself. The temperature To of the control element rises as a result of one or both of a loss occurring in the control element due to a change in conditions or environment on the side where the inverter device is used and an increase in the ambient temperature of the inverter device.

According to the present invention, when the temperature To approaches the maximum allowable temperature TR of the control element, the carrier frequency fc is lowered to maintain the temperature To of the control element under the maximum allowable temperature TR.

3 shows the relationship between frequency and temperature normally and the frequency should be reduced to lower the temperature.

The control method shown in FIGS. 4 and 13, which rely on the output frequency fo and the output current Io, respectively, uses control of the carrier frequency in accordance with the temperature To of the provisional control element.

In this method, the temperature is indirectly detected through the detection of the output frequency fo and the output current Io.

However, since there is no information about the ambient temperature Ta, the control is not accurate compared to the direct detection method of the temperature To of the control element.

Such a system can be constructed at low cost since no temperature sensor is required.

5, a detailed circuit diagram of the carrier generator 501 is shown.

In the reference voltage generator 3, its output is brought closer to the sine wave by quantization of the input analog signal, for example by n-bit digital processing.

Reference numeral 4 denotes a triangular wave capping device generating an upper limit of the triangular wave carrier signal having a controllable upper limit and 5 denotes a triangular wave capping device generating a lower limit of the triangular carrier signal.

The apparatus 3-5 can be realized by the arithmetic function of the microcomputer 6 and outputs each voltage value in a digital shape.

The microcomputer 6 becomes a 16-bit microcomputer, such as the INTEL8096 CPU, which has a 16-bit data bus and integrates an A / D converter.

The voltage data obtained by the microcomputer 6 is latched by the flip flop 7-9.

It is assumed that the inverter of this embodiment outputs a three-phase alternating current so that the flip-flop 7-9 latches a voltage applicable to each of U, V, and W.

The flip-flops 10 and 11 are connected to the microcomputer 6 which latches the upper and lower limit data output in the triangle wave upper limit generator and the triangle wave lower limit generators 4 and 5, respectively, which are the limiting generating elements.

In FIG. 5, CS1, CS2, CS3, CS4 and CS5 control the signal provided to the flip-flop 7-11 from the microcomputer 6.

The n bit up-down counter 12 is used to quantify the triangular waveform generated by the carrier signal generator and output the quantized value.

The triangular waveform is generated by the counter 13 and repeats the counter CK _U and a different count CK _D in response to the clock input signal CK.

14 through 18 represent n-bit digital signal comparators.

In particular, the comparator 14 compares the n-bit U-phase voltage data provided by the flip-flop 7 with the n-bit triangular wave data output by the counter 12 and outputs the signal UP _O according to the result of the comparison. Will occur).

Similarly, the comparators 15 and 16 also output the outputs V _O according to the result of the comparison between the V and W phase voltage data in the flip-flops 8 and 9 and the triangular wave data output by the counter 12. , WP _O ).

The comparator 17 operates to compare the triangular wave data generated by the up-down counter 12 with the triangular wave upper limit data obtained from the flip-flop 10 and outputs the output signal EQ to the clock switching circuit 13. _U ) serve.

A comparator 18 similar to the comparator 17 compares the triangular wave data at the counter 12 with the triangular wave lower limit data at the flip-flop 11.

The output signal from the digital comparators 14 and 15, which is used as a signal for driving the switching elements on U, V, and W phases, is converted into an inverting circuit and a short circuit prevention circuit (not shown in the drawing) using one of the phase signals of FIG. Is supplied).

In FIG. 5, the output frequency setter 1 and the temperature detector 2 are shown connected to the microcomputer 6.

The output frequency setter 1 outputs a signal in the form of voltage or current based on the operator setting of the variable control contact of the apparatus. In the figure, the output frequency setter 1 outputs a signal in the form of a voltage or a current. In the figure, the output frequency setter 1 operates with a voltage signal.

The temperature detector 2 for detecting the temperature of the switching element, for example the MOSFET or the IGBT, outputs an analog signal, for example a voltage signal.

In a simplified phenomenon, the temperature detector switches on and off when the temperature changes beyond the reference temperature.

In operation, the output signal from the output frequency setter 1 or the temperature detector 2 is supplied to the input port of the microcomputer 6. When the voltage signal is input from the output frequency setter 1, the reference voltage corresponding to the output frequency is output from the microcomputer 6.

At the same time, the triangular wave upper and lower limits providing the return point of the triangular wave are output from the microcomputer 6.

The output signal from the output frequency setter 1 or the temperature detector 2 is thus supplied to the input port of the microcomputer which converts the input analog signal into a digital signal and calculates the upper and lower limits of the reference voltage triangular wave.

It is estimated here that the level of the output at the output frequency setter 1 or the temperature detector 2 is constant.

The microcomputer 6 can output a sinusoidal reference signal that is quantized and approximated by an n-bit digital amount as shown in FIG.

As shown in FIG. 6, the duration of each quantization step having the size Tc is established by the computation time of the microcomputer.

Needless to say, the degree of myopia of the sine wave is increased when the time Tc is short and the number of bits n is increased in the quantization process.

If n is 10 (n = 10), the hexadecimal representation shows a wave approximating a sine wave with an upper limit of 3FFH and a lower limit of 0OOH.

The imaginary center of the amplitude of this sinusoidal wave is in hexadecimal representation between 20OH and 1FFH and the output sinusoid changes its amplitude at this center of amplitude.

Thus, the output frequency setter 1 increases the sinusoidal waveform amplitude when setting the output frequency of the inverter device at the high level.

On top of that, the amplitude is reduced when the output frequency is set to a low level.

The voltage signals calculated and output by the microcomputer 6 are latched by the flip-flops 7, 8, 9 corresponding to the voltages of the three phases U, V, and W, respectively.

This voltage data is set and latched at an interval of 120 ° by the electrical angle.

In the preferred embodiment, the voltage data is set via the 16-bit bus of the microcomputer 6 so that when the size of the voltage data on each U, V, W exceeds 5 bits, the voltage data cannot be set and latched in one operation. And settings and latches must be made in multiple operations.

In such a case, the comparison of this voltage data with the triangular wave implemented by the comparator is hindered by the time difference in which three phases exist between the voltage data of the phases.

Therefore, it is necessary to provide an additional step of flip-flop to simultaneously format the voltage data for the U, V, and W phases.

Referring to FIGS. 7 and 5, the triangular wave upper and lower limit data output from the microcomputer 6 as a result of the functions 4 and 5, respectively, are returned to the triangular wave generated by the triangular wave generator 12. FIG. To provide.

The triangular wave upper limit is latched by the flip-flop 10 and supplied to the comparator 17. It is likewise latched by the triangular wave lower limit flip-flop 11 and supplied to the comparator 18.

As mentioned above, the triangular wave generator 12 is an up-down counter controlled by the up counting clock Cku and the down counting clock Cko, and its current count is simultaneously output to the comparator 14-18.

When the up-down counter 12 is in the up counting mode, counting continues in response to the input clock signal CKU as indicated by the ascending depth waveform of FIG.

However, the comparator 17 generates a coincidence signal EQ _U when the triangular wave data constituted by n bits is coincident with the n-bit triangular wave upper limit during the counting by the counter 12.

In response to this signal EQ _{U the} clock switching circuit 13 operates to set the up count clock CK _{U in the} inactive state and to set the down count clock CK _U in the active state and so the counter 12 is switched from the up counting mode to the down counting mode.

When in the down count mode, the counter 12 counts down at its value in that it returns in response to the clock input CK _D as also shown in FIG.

The comparator circuit 18 supplies the coincidence signal EQ _D when the triangular wave data matches the n-bit triangular wave lower limit data during the down counting operation.

In response to this signal, clock switching circuit 13 switches clock CKD and clock CK _U into inactive and active states, respectively.

The operation is continuously repeated so that a triangular wave signal having a peak at the level of the triangular wave upper limit and a trough at the level of the triangular wave lower limit is formed.

8 shows an example of the configuration of the clock switching circuit used for the counter 12. As shown in FIG.

The upper coincidence signal EQ _U and the lower coincidence signal EQ _D are amplified by the inverter amplifiers 131 and 132, respectively, and input to the set and reset flip-flop 133.

Flip-flop The output is divided into two signals, one of which is inverted by the inverter amplifier 134. The pair of logic gates 135 and 136 receive a clock signal CK and each gate is Signal that is the reverse of Receive one of the signals.

At the base of this input, the gate generates clocks CK _U and CK _D.

In operation, when the EQ _U signal is input, the flip-flop is set and the state Q = "L" is obtained. Therefore, clock CK _U becomes inactive and clock CK _D becomes active.

The frequency of the triangular wave is determined by the set value of the upper and lower limits and the frequency fck of the clock CK whose frequency of the up-down counter 12 performs its arithmetic function.

The following equation determines the frequency:

… (5)

Assuming that the upper and lower limit values of the triangular wave data are 10 bits, 3FFH and 0OOH in hexadecimal, the frequency fck is 20 MHz, and the frequency of the triangular wave, i.

… (6)

Once the size and frequency of the triangular wave is set, its value output from the counter 13 is compared with the reference voltage data on U, V, and W so that the PWM signal is in accordance with the principles previously described with reference to FIGS. 11A and 11B. Get along.

The carrier frequency is changed in accordance with the information in the output frequency setter 1. As described above, the carrier frequency fc, that is, the frequency of the triangular wave, is determined by adjusting the clock frequency fck of the upper and lower set values.

Thus, the carrier frequency fc can be controlled by changing the upper and lower limits when the clock frequency is constant.

For example, if the upper and lower limits are set to 100H of 2FFH, respectively, the carrier frequency fc is calculated in Equation (1) as follows.

… … (7)

Obviously it is possible to obtain a carrier frequency fc which is twice the carrier frequency fc determined by equation (6).

If K denotes the difference between the upper and lower limits of a triangular wave, the carrier frequency fc is determined by the following equation.

fc = fck / 2k... … (8)

It is clearly possible to increase the carrier frequency by reducing the difference K between the upper and lower limits in the equation.

Thus, by setting the output at the microcomputer 6 in such a way that the value of the difference K is decreased and increased in response to the increase and decrease of the inverter output frequency, the carrier frequency ( It is possible to control the carrier frequency fc with respect to the output frequency of the inverter in such a way that fc decreases and increases.

Control of the carrier frequency fc in response to the detected temperature can be carried out in the same way. That is, the temperature value (value) input from the temperature detector 1 can be used by the microcomputer 6 to form the value K by adjusting one or both of the upper and lower limits of the triangular waveform.

When the carrier frequency fc does not change, the amplitude of the triangular wave is kept constant so that the amplitude of the reference voltage is converted in proportion to the frequency of the reference voltage and is output as the output of the inverter device.

Needless to say, the relationship between the voltage and the frequency of AC power is determined by the amplitude of the triangular wave, the amplitude of the reference voltage, and the frequency of the reference voltage.

In this embodiment, the amplitude of the triangular wave is changed in accordance with the change of the carrier frequency fc so that the amplitude of the reference voltage is also changed to maintain a constant relationship between the voltage and the frequency of the output AC power of the inverter device.

This can be achieved by changing the reference voltage generated by the reference voltage generator in accordance with the upper and lower limits of the triangular wave by the microcomputer 6. Such control can be executed without difficulty by the arithmetic function of the microcomputer 6.

9 shows qualitative changes in the reference voltage waveform and the triangular waveform of one phase observed when the carrier frequency fc decreases as a result of the detected element temperature rise when the output AC power of the inverter device is kept constant.

Obviously it is possible to easily control the carrier frequency fc by the circuit arrangement.

For the actual configuration of the circuit represented by the block diagram, each flip-flop 7-11 can be realized by the D-type flip-flop 74HC74 and each comparator 14-18 is realized by the magnitude comparator 74HC85. And the down counter 12 may be realized by the down binary counter 74HC193.

The change in the frequency of the triangular wave, which is not accompanied by the change in amplitude, can be realized simply by changing the clock frequency fck.

It is more substantial to detect the surface temperature of the cooling body of the control element or a component thereof and the ambient temperature of the inverter when the temperature of the control element is directly detected in the above embodiment. Automatic control of the carrier frequency in response to the detected temperature can be achieved immediately by the microcomputer 6.

FIG. 15 briefly shows a pro of the process of changing the carrier frequency fc in the detection of the element temperature To when executed by the microcomputer 6. Step START indicates that the operation of the inverter is started.

Considering that the device temperature To is low, fcmax is set as the carrier frequency fc in step S1. The calculation of the carrier frequency fcmax, the setting of the reference voltage, the setting of the upper limit value and the lower limit value of the triangular wave are performed in steps S2-S4.

In step S5, time processing is executed by a timer for which time t1 is set. The time t1 is determined based on the thermal time constant of the control element which contains the cooling body of the control element.

After elapse of time t1, the element temperature to is read in step S6. In step S7, the element temperature To is compared with the target temperature T. The target temperature T is a value obtained in the thermal design of the control element. In general, the target temperature T is set at a level obtained by reducing the allowable maximum temperature Tk to some extent.

When the detected element temperature to is lower than the target temperature T, the carrier frequency fc is set in step S8 by fc at a level higher than the constant carrier frequency fc.

The screw steps S2 to S4 are again executed based on the carrier frequency fc set in step S8 or S9. If the carrier frequency fc has already been set to fcmax, step S8 permits the operation of the inverter continuously by setting the frequency increase to zero (0), that is, keeping the carrier frequency fc constant at the level of fcmax. When the carrier frequency fc already set is fcmin in step S9, it is determined that there is an abnormal temperature rise of the element, and the process moves to the protection process.

FIG. 16 quantitatively shows how the carrier frequency fc and the device temperature To change with respect to time t as a result of the execution of the process. The described embodiment may be modified such that a tolerance T is provided at the target temperature T so as to have hysteresis characteristics in the control of the carrier frequency fc.

It is also possible to calculate the degree of variability of the detected device temperature To and to vary the carrier frequency increase fc in accordance with the degree of variability of the device temperature.

FIG. 17 schematically shows a pro of a process executed by the microcomputer 6 which changes the carrier frequency fc based on the output current Io and the output frequency fo. The process is substantially the same as shown in FIG. 15 except that To is computed at the detected values Io and fo of the output current and output frequency instead of being directly detected.

The present invention is not intended to be limited thereto when it is disclosed with respect to some embodiments, and the full scope of protection provided by the present invention is defined in the appended claims.

Claims (8)

An inverting converter 200 including a control element for converting a direct current into a variable output voltage and an alternating current of an output frequency, and a reference voltage operable to output a reference voltage waveform used as a reference of the output frequency and the output voltage. Generating means 400, carrier generating means 500 for forming and outputting a carrier waveform at a carrier frequency, comparing the reference voltage with the carrier and controlling the controllable element of the inverting converter 500 In response to a pulse width modulation circuit 600 for generating a signal, a driving means 700 for driving the provisional control element in response to a signal provided from the pulse width modulation circuit 600, and in response to a parameter of a detected operation And a control means for controlling the carrier frequency. 2. A pulse according to claim 1, wherein said arithmetic parameter comprises said output frequency and said control means increases said carrier frequency with decreasing said output frequency and decreases said carrier frequency with increasing said output frequency. Width modulated inverter device. The method according to claim 1, wherein said operation parameter comprises a load current of said inverter and said control means increases said carrier frequency with decreasing said load current and decreases said carrier frequency with increasing said load current. Pulse width modulation type inverter device. 4. The pulse width modulation inverter device according to claim 3, further comprising a current detecting means (800) for detecting a load current of the inverter after controlling the carrier frequency. An inverting converter 200 including a control element for converting a direct current into a variable voltage and frequency of an alternating current, and a reference voltage generating means operable to output a reference voltage waveform used as a reference for the output frequency and the output voltage. 400, carrier generating means 500 for forming and outputting a carrier waveform at a carrier frequency, comparing and modulating the reference voltage and the carrier, and controlling the controllable element of the inverting converter 200. A pulse width modulation circuit 600 for generating a signal, a driving means 700 for driving the control element in response to a signal provided from the pulse width modulation circuit 600, and a decrease in temperature of the control element. Within a predetermined range of carrier frequency to increase the carrier frequency accordingly and to decrease the carrier frequency with increasing temperature of the control element. And a control means for executing a control function. 6. The pulse width modulation inverter device according to claim 5, wherein a temperature detecting means (800) for detecting the temperature of the inverting converter (200) is added. 7. The pulse width modulated inverter device of claim 6, wherein the reference voltage waveform comprises a sine wave and the carrier waveform approximates a triangular wave. 7. The pulse width modulated inverter device of claim 6, wherein said control means operates to increase said carrier frequency as said output frequency decreases and to decrease said carrier frequency as said output frequency increases.