JP3994243B2 - Power converter and its PWM pulse generation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power conversion device such as an inverter / servo drive that performs variable speed driving of a motor.
[0002]
[Prior art]
Conventionally, as a PWM pulse generation method of an inverter, a method of generating a PWM pulse by comparing a command voltage with a triangular wave carrier, or a method of generating a PWM by vector calculation of a space vector is generally used. That is, in the PWM inverter that converts the DC power of the DC power source into AC power whose frequency and voltage (current) are controlled by controlling the switching elements of the inverter main circuit and supplies it to the load, each phase switching element of the inverter main circuit is PWMed Control according to the waveform. Among such conventional PWM inverters, a typical example of a waveform generation circuit of a neutral point clamp type PWM inverter is disclosed in, for example, JP-A-8-98540.
FIG. 12 shows a circuit diagram of the PWM inverter. The circuit shown in FIG. 12 is a waveform generation circuit of a neutral point clamp type PWM inverter. The carrier generated from the two carrier generators 104A and 104B and the sine wave generator 105 are shown. Are compared with each other by the comparators 106A and 106B, the outputs of both comparators are added by the adder 106C, and the phase is returned by the sign inversion circuit 106D, whereby the high level H, the low level L, and A PWM waveform with zero level 0 is generated. By this signal, a switching arm (not shown) constituted by a switching element such as IGBT is selectively turned on / off to obtain a desired output voltage.
[0003]
[Problems to be solved by the invention]
However, in the above-described conventional example, in the case of an operation of a two-level or three-level inverter in which the inverter command voltage is low modulation rate and a large current flows through the switch element, such as during regenerative braking, There is a problem that current concentrates on a specific switch element and the switch element itself is thermally destroyed by heat due to loss of the switch element.
Therefore, the present invention adjusts the generation time of the zero voltage vector so as not to affect the line voltage, thereby controlling the loss due to the current flowing through the switching element to prevent the thermal destruction of the switching element. It is an object to provide a method and a generator.
[0004]
[Means for Solving the Problems]
The invention described in claim 1 is a three-phase three-level inverter main circuit that converts DC power having a plurality of switching elements into AC power, and a comparison that generates a PWM pulse by comparing the amplitudes of the phase command voltage and the carrier wave. And a power conversion device comprising:
The modulation rate is obtained by comparing the modulation rate with a modulation rate reference value by a modulation rate detection unit that inputs the PWM pulse and obtains a modulation rate from the on / off ratio of the PWM pulse using a conversion table. only if below a value, by shifting the directive voltage upward or downward direction by adding the same amount of DC offset values in all phases of the command voltage, the changing time of occurrence of the zero voltage vector, positive bus those having a generation time ratio means zero voltage vector to vary the loss-sharing the switching element of the switching element and the negative bus side of the side, a.
The invention according to claim 2 is a three-phase three-level inverter main circuit that converts DC power having a plurality of switching elements into AC power, and a comparison that generates a PWM pulse by comparing the amplitudes of the phase command voltage and the carrier wave. A PWM pulse generating method for a power conversion device comprising: a modulation rate detecting process for inputting the PWM pulse and obtaining a modulation rate from an on / off ratio of the PWM pulse using a conversion table; A comparison process is performed to compare the modulation factor by the detection process and a modulation factor reference value, and only when the modulation factor is lower than the modulation factor reference value by the comparison process, the same amount of direct current is applied to all phases of the command voltage. By shifting the command voltage upward or downward by adding an offset value, the generation time of the zero voltage vector is changed, and the switching element and negative bus on the positive bus side are changed. Changing the loss-sharing the switching element side, PWM pulse generating method of the power converter, characterized in that the generation time change processing of the zero voltage vector.
[0005]
According to the above configuration, when the command voltage of the inverter has a low modulation rate and the operation is such that a large current flows through the switch element, such as during regenerative braking, the current concentrated on the switch element of the inverter becomes zero. This can be prevented by changing the time ratio of the switch pattern, so that the thermal destruction due to the loss of the switch element can be prevented and the safety of the inverter can be improved.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIGS. 1-6 is a figure of an example based on the 1st Embodiment of this invention.
FIG. 1 is a diagram showing a PWM pulse when the command voltage of the three-phase two-level inverter according to the first embodiment of the present invention is shifted.
FIG. 2 is a diagram showing a PWM pulse when the command voltage shown in FIG. 1 is shifted in the reverse direction.
FIG. 3 is a basic circuit diagram for one phase of the PWM pulse generator shown in FIG.
FIG. 4 is a diagram showing an example of a PWM pulse generated in the circuit of FIG.
FIG. 5 is a main circuit diagram of the three-phase two-level inverter to which the PWM pulse shown in FIG. 4 is applied.
FIG. 6 is a state diagram at the time of zero voltage output of the three-phase two-level inverter shown in FIG.
In FIG. 3, 1 is a triangular wave carrier generator, 2 is a command voltage generator including information such as output voltage and output frequency, and the generated carrier and command voltage are compared by a comparator 3 to generate a PWM pulse. FIG. 3 shows a general circuit configuration.
The main circuit of the three-phase two-level inverter has a circuit configuration as shown in FIG. 5, 4 is a DC power supply, 5 is a smoothing capacitor, and 6 to 11 are upper and lower pairs for each phase U, V, W. Reference numerals 12 to 17 denote feedback diodes of the switch elements IGBTs 6 to 11.
As shown in FIG. 3, the triangular wave carrier and the command voltage are compared by the comparator 3 to generate a PWM pulse. For example, if the command voltage is high, the upper IGBT (6, 8, or 10) is turned ON, When it is low, a three-phase sinusoidal phase voltage can be obtained by turning on the lower IGBT (7, 9, or 11). The line voltage in this case is a difference voltage between the phase voltages U, V, and W.
In the case of regenerative braking of the motor, the brake is applied as a generator operation, and the regenerative energy is returned to the inverter and the smoothing capacitor 5 is charged to increase the DC voltage. Alternatively, it is processed by regeneration control or the like by the converter unit.
The manner of PWM pulse generation in the circuit of FIG. 3 will be described in more detail with reference to FIG. Here, one triangular wave carrier and three command voltages of three phases (U phase, V phase, W phase) are compared to generate PWM pulses for each phase.
In FIG. 4, 0n, 0p, a, and b are names of vectors output from the three-phase two-level inverter (for example, a rotation vector having a midpoint as a zero voltage vector), and 0n and 0p are U, This is a state in which a voltage vector with zero line voltage (zero voltage vector) is output when the V and W phases are short-circuited. 0n is a state diagram in which the three switches 7, 9, 11 on the negative bus side are turned on (b). 0p is a state diagram 6A in which the three switches 6, 8, 10 on the positive bus side are turned on.
[0007]
In the present embodiment, the loss of the switch element is reduced by utilizing the output state of this zero voltage vector. The state in which the zero voltage vectors of 0n and 0p are output is exactly the same when viewed from the line voltage. Therefore, even if the generation order of the 0n and 0p vectors is changed, the line output voltage is not affected. If the total output time of the zero voltage vector is the same, changing the ratio of the generation time of the 0n and 0p vectors does not affect the line output voltage. For example, when the three command voltages are shifted upward by the same amount from the state of FIG. 4 as shown in FIG. 1, the generation time of the 0n vector is shortened and the generation time of the 0p vector is lengthened. Here, since the generation times of a, b, and vectors are not changed, the average voltage output between the lines is not changed from that before the shift. However, when the generation time of the 0p vector becomes longer, the state of FIG. 6A becomes longer on a time average, and the ratio of current flowing through the switch element on the positive bus side becomes larger. That is, the loss of the switch element on the positive bus side increases, and the loss of the switch element on the negative bus side decreases.
Shifting the command voltage for the three phases by the same amount can be performed by adding the same offset value to the entire command voltage.
Conversely, when the three command voltages are shifted downward by the same amount from the state of FIG. 4 as shown in FIG. 2, the generation time of the 0n vector becomes longer and the generation time of the 0p vector becomes shorter. Furthermore, even in this case, the generation time of the a and b vectors does not change, and the average voltage output as the line-to-line output does not change from that before the shift, but the generation time of the 0n vector becomes longer. In FIG. 6B, the ratio of the current flowing through the switch element on the negative bus side becomes larger, the loss of the switch element on the negative bus side increases, and the loss of the switch element on the positive bus side increases. Decrease.
From the above, by shifting the three-phase command voltage, the loss sharing between the switch element on the positive bus side and the switch element on the negative bus side can be changed, and the current is concentrated on a specific switch element. In such a case, the switch element loss can be controlled to prevent thermal destruction of the switch element.
For example, when a large current flows through the inverter at a low modulation rate, such as during regenerative braking of an electric motor, the safety of the device can be ensured by distributing the loss sharing of the switch elements under the control of a control unit (not shown). .
[0008]
Next, a second embodiment of the present invention will be described with reference to the drawings.
FIG. 7 is a diagram showing an example of the PWM pulse of the three-phase three-level inverter according to the second embodiment of the present invention.
FIG. 8 is a main circuit diagram of the three-phase three-level inverter to which the PWM pulse shown in FIG. 7 is applied.
FIG. 9 is a state diagram at the time of zero voltage output of the three-phase three-level inverter shown in FIG.
FIG. 10 is a diagram showing a state in which the lower switching arm is turned off when the zero voltage is output as shown in FIG.
FIG. 11 is a diagram showing a state in which the upper switching arm is turned off at the time of zero voltage output shown in FIG.
The three-phase three-level inverter of the second embodiment has a circuit configuration as shown in FIG. Ep19 and En20 are voltage dividing capacitors that divide the DC power supply Ed18 into Ed / 2 to create three voltage levels, and 45 and 46 are rectifying elements (diodes) for deriving neutral point voltages of the capacitors 19 and 20. Reference numerals 21 to 24 denote IGBTs constituting switching arms for one U-phase each provided with rectifying elements (diodes) 33 to 36 for reflux.
Similarly, switching for IGBTs 25 to 28 and 29 to 32 for switching arms provided with neutral point diodes 47, 48 and 49, 50 and freewheeling diodes 37 to 40 and 41 to 44, respectively, for V phase and W phase switching. It constitutes the arm.
As an example of the PWM pulse generation method in this case, as shown in FIG. 7, a method of generating a PWM pulse of each phase by comparing a total of six command voltages with one triangular wave carrier and two command voltages per phase. is there. FIG. 7 shows a state at a low modulation rate.
In FIG. 7, 0n, an, bn, 0o, ap, bp, and 0p are names of voltage vectors output from the three-phase three-level inverter, and 0o, 0n, and 0p are U as shown in FIGS. This is a state in which a zero voltage vector in which the phase, the V phase, and the W phase are short-circuited is output.
[0009]
In the case of the second embodiment, similarly to the previous embodiment, the loss of the switch element is reduced using this zero voltage vector. Since the state in which zero voltage vectors of 0n, 0o, and 0p are output is the same as viewed from the phase voltage, the line output voltage is not affected even if the generation order of the 0n, 0o, and 0p vectors is changed. .
Similarly to the previous embodiment, when the command voltages P1 to P3 are shifted by the same amount, the generation time ratio of each zero voltage vector changes, but the average voltage output between the lines is the same as before the shift. It does not change. Therefore, even in the case of a three-phase three-level inverter, by adjusting the generation time ratio of the zero voltage vector, the loss of each switch can be adjusted at a low modulation rate such as during regenerative braking as in the case of the three-phase two-level inverter. Thermal destruction of the switch element can be prevented.
[0010]
FIG. 13 is an example of a flowchart of the zero voltage vector generation time ratio adjustment according to the present invention, and FIG. 14 is an example of a block diagram of the present invention.
In FIG. 13, when the flow starts, a modulation rate is detected in 131, and whether or not the detected value is lower than a predetermined modulation rate value is compared in 132.
In this case, the predetermined modulation rate may be about 0.5.
As a result, (1) if the detected value is not lower than the predetermined modulation factor value, normal PWM control is continued (133).
(2) If the detected value is lower than the predetermined modulation factor value, the zero voltage vector generation time ratio is adjusted (134).
[0011]
FIG. 14 is an example of a specific circuit block for realizing the above flow. In FIG. 14, the DC power of the DC power source 4 is converted into AC power whose frequency and voltage (current) are controlled by controlling the switching mode of the PWM inverter main circuit 90 (see FIGS. 5 and 8), and the motor M as a load is converted. To supply. In the PWM inverter, each phase switching element of the main circuit 90 is controlled according to the PWM waveform. The PWM waveform for this purpose is generated by comparing the level comparison between the carrier signal from the triangular wave carrier generator 1 shown in FIG. 3 and the signal of the command voltage generator 2 by the comparator 3. This PWM pulse is distributed by the gate circuit 93 as a gate signal necessary for turning on the switching element of the PWM inverter main circuit 90. Reference numeral 91 denotes a filter for removing harmonic components from the inverter output.
In such a circuit, according to the present invention, the modulation rate detection means A is provided, and the PWM waveform that is the output of the comparator 3 is input to the modulation rate detection means A. The modulation rate detecting means A can be realized by a memory and CPU having a conversion table of on / off ratio versus modulation rate, for example, and obtains the modulation rate from the on / off ratio of the input PWM waveform.
The obtained modulation rate is inputted to the minus terminal of the modulation rate comparison means B provided by the present invention, while the modulation rate reference value is inputted to the plus terminal of the modulation rate comparison means B. Thereby, when the modulation rate is higher than the reference value, no output is output from the modulation rate comparison unit B, and when the modulation rate is lower than the reference value, an output is output from the modulation rate comparison unit B.
C is a zero voltage vector generation time ratio adjusting means provided by the present invention. The time ratio adjusting means C functions to shift the command voltage of the command voltage generator 2. Accordingly, when an output is output from the previous modulation rate comparison means B, the time ratio adjustment means C is activated, and the command voltage of the command voltage generator 2 is shifted to shift the switch element on the positive bus side and the switch on the negative bus side. The loss sharing of the elements can be changed, and when current concentrates on a specific switch element, the switch element loss can be controlled to prevent thermal destruction of the switch element.
[0012]
【The invention's effect】
As described above, according to the present invention, in the three-phase two-level or three-phase three-level inverter, by changing the generation time ratio of the switch pattern in which the line-to-line output voltage at the low modulation rate becomes zero, It is possible to adjust the loss generated in the switch element when a large amount of current flows, and there is an effect of preventing the thermal destruction of the switch element and improving the safety of the inverter.
In addition, the above description is an example and this invention is not limited to this.
[Brief description of the drawings]
FIG. 1 is a diagram showing a PWM pulse when the command voltage of the three-phase two-level inverter according to the first embodiment of the present invention is shifted. FIG. 2 is a diagram in which the command voltage shown in FIG. It is a figure which shows the PWM pulse in the case of doing.
3 is a basic circuit diagram for one phase of the PWM pulse generating device shown in FIG. 1. FIG. 4 is a diagram showing an example of a PWM pulse generated in the circuit shown in FIG.
FIG. 5 is a main circuit diagram of a three-phase two-level inverter to which the PWM pulse shown in FIG. 4 is applied.
6 is a state diagram at the time of zero voltage output of the three-phase two-level inverter shown in FIG.
FIG. 7 is a diagram showing PWM pulses of a three-phase three-level inverter according to a second embodiment of the present invention.
FIG. 8 is a main circuit diagram of a three-phase three-level inverter to which the PWM pulse shown in FIG. 7 is applied.
FIG. 9 is a state diagram at the time of zero voltage output of the three-phase three-level inverter shown in FIG. 8;
10 is a diagram showing a state in which the lower switch arm is turned off at the time of zero voltage output shown in FIG. 9;
11 is a diagram showing an upper switch arm OFF state at the time of zero voltage output shown in FIG. 9;
FIG. 12 is a waveform generation circuit diagram of a conventional neutral point clamp type PWM inverter.
FIG. 13 is a flowchart of zero voltage vector generation time ratio adjustment according to the present invention.
FIG. 14 is an example of a block diagram of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Triangular wave carrier generator 2 Command voltage generator 3 Comparator 4, 18 DC power supply 5, 19, 20 Capacitors 6-11, 21-32 Semiconductor switch element 12-17, 33-50 Rectifier element 90 PWM inverter main circuit 91 Filter 92 Motor 93 Gate circuit A Modulation rate detection means B Modulation rate comparison means C Zero voltage vector generation time ratio adjustment means

Claims (2)

Power conversion comprising: a three-phase three-level inverter main circuit that converts DC power having a plurality of switch elements into AC power; and a comparator that compares the amplitudes of the phase command voltage and the carrier wave to generate a PWM pulse In the device
Modulation rate detection means for inputting the PWM pulse and obtaining a modulation rate from the on / off ratio of the PWM pulse using a conversion table;
By comparison with the modulation rate reference value and the modulation factor, the only case where the modulation rate is below the modulation rate reference value, the upward direction directive voltage by adding the same amount of DC offset values in all phases of the command voltage or A zero voltage vector generation time ratio adjusting means for changing the generation time ratio of the zero voltage vector and changing the loss sharing of the switch element on the positive bus side and the switch element on the negative bus side by shifting downward. the power conversion apparatus characterized by comprising a. Power conversion comprising: a three-phase three-level inverter main circuit for converting DC power having a plurality of switch elements into AC power; and a comparator for comparing the amplitudes of the phase command voltage and the carrier wave to generate a PWM pulse In the PWM pulse generation method of the device,
The PWM pulse is input, a modulation rate is detected from the on / off ratio of the PWM pulse using a conversion table, and a modulation rate detection process is performed.
Comparing the modulation rate by the modulation rate detection process with a modulation rate reference value,
Only when the modulation factor is lower than the modulation factor reference value by the comparison process, by adding the same amount of DC offset value to all phases of the command voltage and shifting the command voltage upward or downward, zero voltage is obtained. What is claimed is: 1. A power converter comprising: changing a vector generation time and changing a loss sharing between the switch element on the positive bus side and the switch element on the negative bus side. PWM pulse generation method.

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