KR100734050B1 - Feed-back control method - Google Patents

Abstract

A motor feedback control method using an H-bridge multi-level inverter is provided to solve a problem about a current controller when controlling an induction motor vector through the H-bridge multi-level inverter. A motor feedback control method using an H-bridge multi-level inverter removes an unstable factor of a current controller by detecting output voltage phase delays of the H-bridge multi-level inverter and a power cell, multiplying an output of the current controller by a function compensating an error due to the phase delay, and compensating the phase of the output voltage at stop DQ coordinates.

Description

Motor feedback control method using H-bridge multi-level inverter {Feed-back control method}

1 shows a Space Vector PWM.

2 shows a phase disposition carrier-based PWM.

3 shows a phase opposition carrier-based PWM.

4 shows an Alternative Phase Opposition Disposition Carrier-based PWM.

5 shows a phase-shifted carrier-based PWM.

Fig. 6 is a block diagram showing an H-bridge multilevel inverter which is a high voltage electric motor variable speed device.

7 is a diagram illustrating a phase delay state of an H-bridge multilevel inverter output voltage configured with 13 levels.

8 is an induction motor vector control diagram in which a phase delay compensation term is added.

9A and 9B are induction motor vector control diagrams in which a compensation term controlled by an H-bridge multilevel inverter is added.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor feedback control method using an H (H) -bridge multilevel inverter, and more particularly, to detect a phase delay between an inverter power cell and an inverter output voltage, and to multiply a current controller output by a function that compensates for the phase error The present invention relates to a motor feedback control method using an H-bridge multilevel inverter, which makes it possible to decentralize and modularize a controller of a multilevel inverter while eliminating the instability caused by the phase delay of the current controller.

The voltage of high voltage large induction motors is variously designed from 2,400V to 7,200V. On the other hand, the high-voltage inverter, which is a variable speed motor, does not vary in voltage, so it can be applied to various types of motors by using step-down and step-up transformers. Many problems, such as the need for installation space and reduced system efficiency, have emerged as an obstacle to the spread of industrial inverters.

In addition, the inverter is having difficulty in applying the inverter due to the harmonic effect of the bus, the deterioration of the motor due to the PWM voltage, the vibration, the insulation, and the devaluation of the energy savings. To overcome this problem, various kinds of multilevel inverters have been developed.

The circuit method for constructing a voltage-type high-voltage high-capacity inverter can be largely divided into a high-voltage method and a multilevel method of the switching device by series connection of the switching devices.

The device series method is to connect several low voltage switching elements in series to form an equivalent high voltage switching element. In this case, the circuit operation is the same as that of a low voltage two-level inverter.

The oldest three-level NPC (Nutral Point Clamping) multilevel inverter is a method of clamping a voltage applied to a switching device through a diode so that the voltage distribution of the device is constant.

In order to increase the inverter output voltage, it is necessary to extend the NPC method to configure multilevel, in which case the circuit configuration consists of several switches and clamping diodes per phase. The dc link should also be a voltage distribution circuit with multiple capacitors.

Comparison of key characteristics of high voltage large capacity inverter topology  SC2L  DCML  CCML  HBML  Voltage STEP  One  many  many  Very many  Output THD  Big  small  small  Very small  Control  simple  complication  complication  complication  Voltage balance of DC link  Good  DC link capacitor voltage balance  Clamp capacitors voltage balance  Unnecessary  Filtering requirement  High  Low  Low  Very low  Max motor voltage  3.3kV (Filter-less) 6.6kV (Filter)  3.3kV (Filter-less) 4.2kV (Filter)  3.3kV (Filter-less) 4.2kV (Filter)  3.3 kV (Filter-less) 6.6 kV (Filter-less)

Diode Clamping Expanding Three-Level NPC Method When a circuit is composed of a multi-level inverter, the voltage stress applied to the clamping diode is not constant and the voltage balance problem of the DC-stage capacitor is not easy.

One way to improve this is to use capacitor clamping multilevel inverters. This method compensates to some extent the problem of the diode clamped method by balancing the voltage of the device by a capacitor.

Another multilevel method is an H-bridge multilevel inverter, in which a power cell composed of a single-phase H-bridge inverter is connected in series instead of an element in series.

In this case, since each power cell has an independent DC link, a constant voltage is applied to the switch without a separate clamping circuit. However, the dc link of each power cell must be insulated.

Table 1 shows the main characteristics of high-voltage large-capacity inverter topologies for motor variable speed devices (SC2L: Series Connected 2-Level, DCML: Diode Clamping Multi-Level, CCML: Capacitor Clamping Multi-Level, HBML: H-Bridge Multi-Level).

Among the various multilevel inverters, the power topology exhibiting the best characteristics in terms of input / output quality is an H-bridge multilevel inverter capable of obtaining a high voltage by connecting a low voltage single phase inverter in series.

Each phase of the H-bridge multilevel inverter consists of several power cells connected in series. Each parcel has an independent single-phase inverter structure, and by connecting several power cells in series, a high voltage can be obtained using a low voltage power cell, that is, a low voltage power semiconductor, and according to the number of power cells, The number is increased to obtain a voltage waveform close to the sine wave. The input connected to the power system is connected to a transformer with multiple taps on the secondary side of the extended delta wiring method. The input transformer serves two purposes.

The first application is to supply independent power to each power cell of the H-bridge multilevel inverter. The second application is to construct a multi-pulse rectifier type converter with a phase difference between secondary taps. This is to achieve a very low total harmonic distortion (THD) compared to the -pulse rectification method. In general, the multi-level inverter is a fixed circuit method, it is difficult to cope with various voltages. However, cascaded H-bridge multilevel inverters are more flexible because they can easily change voltage levels by adjusting the number of power cells. In addition, since the system is a combination of the same power cells, it is possible to replace the unit of power cells in case of failure, so that only a spare power cell needs to be secured, so there is less burden on the spare parts.

Protection can be divided into power cell fault monitoring and system fault monitoring to provide more reliable and flexible fault monitoring and diagnostics. In the case of critical loads where the system should not be stopped, an auxiliary switch that can bypass the output of each cell is equipped so that the system can be operated by only lowering the voltage without stopping during the troubleshooting period. De-Rating Operation is possible. In this respect, a cascaded H-bridge multilevel inverter is an excellent power topology.

The structural characteristics and input / output characteristics of the H-bridge multilevel inverter are as follows.

Structural features

Series connection of single-phase inverters with independent and isolated DC Links;

-Complete module for power circuit

-Economical because it is composed of low pressure IGBT

-Easy to increase voltage rating because it is designed in module unit

(Easy to series by inverter voltage)

-Possible to operate even in case of individual power cell failure (De-Rating Operation)

I / O characteristics

-Output multileveling using PWM phase shift of individual power cells

Low output harmonics even at low switching frequencies

-Low input THD by using multiple pulse transformer.
(No input filter required)

-The output THD is low because the voltage step has several steps.
(No output filter required)

-Due to the small effect of voltage reflection, it can be installed even if the distance between inverter and motor is long

A PWM method of such a multilevel inverter includes a space vector PWM and a carrier-based PWM of FIG. 1, and a pulse disposition PD of FIG. 2 to a carrier-based PWM. , Pulse Opposition Disposition (POD) of FIG. 3, Alternate Phase Opposition Disposition (APOD) of FIG. 4, Pulse-Shifted (PS) of FIG. 5 There is a way.

Applying Phase-Shifted Carrier-based PWM (PSCPWM) to H-bridge multilevel inverter among PWM of various multilevel inverter enables modularization and distributed control of power circuit and controller of single-phase inverter and simple implementation There is an advantage to being terminated.

However, when the PSCPWM technique is applied to the motor vector control, there is a problem in that feedback control occurs because a phase difference occurs between the output voltage reference value of the controller and the actual output voltage of the inverter.

Accordingly, the present invention for solving the above problems is to detect the phase delay of the inverter power cell and the inverter output voltage, and multiply the current controller output by a function that compensates for the phase error so that the instability caused by the phase delay of the current controller is eliminated. Accordingly, an object of the present invention is to provide a motor feedback control method using an H-bridge multilevel inverter, which makes it possible to decentralize and modularize a controller of a multilevel inverter.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, FIGS. 6 to 9.

FIG. 6 illustrates an H-bridge inverter, in which a plurality of power cells consisting of a diode, a capacitor, and an IGBT are connected in series to each motor motor.

Phase-Shifted Carrier-based PWM (PSCPWM) method has many advantages, but when this PWM method is applied to vector control, phase difference occurs between output voltage reference value of controller and actual inverter output voltage. do. Equations 1 and 2 represent phase delays of the output voltages of the H-bridge multilevel inverter and the power cell when the PSCPWM is applied.

는 H-브릿지 멀티레벨 인버터 각 상의 파워셀 출력전압,

는 출력전압 기준값,

는 파워셀의 번호,

은 1상당 직렬로 연결된 파워셀의 총 갯수,

는 PWM 샘플링 시간을 의미한다.here,

Is the power cell output voltage of each phase of the H-bridge multilevel inverter,

Is the output voltage reference value,

Is the number of the power cell,

Is the total number of power cells connected in series per phase,

Means PWM sampling time.

에 비례하여 위상지연이 증가하는 현상이 발생한다.According to the above formula, the first power cell of each phase has no phase delay but the sampling time from the second power cell.

The phase delay increases in proportion to.

The phase delay of the power cell output voltage phase delay is represented by equation (3), and the phase delay of the H-bridge multilevel inverter output voltage is expressed by equation (4).

In PSCPWM, the output voltage reference value of the H-bridge multilevel inverter has no phase delay, but the output voltages of the individual power cells and the H-bridge multilevel inverter actually appear in phase delay form due to the phase shift of each power cell carrier.

Delay time at the output voltage of the actual H-bridge multi-level inverter than the output voltage reference value does not cause a big problem in open-loop control such as V / F operation, but it is closed-loop In the control, the control characteristic of the current controller of the synchronous coordinate system becomes worse.

In the case of the synchronous coordinate system current controller, the reference coordinate axis moves during this delay time. If this is not considered, an error occurs in the phase of the output voltage. This error can be ignored if the ratio of the sampling frequency to the output frequency is large enough, otherwise the control system becomes unstable due to the movement of the reference coordinate system during the delay time. FIG. 7 illustrates the phase delay of the output voltage when PSCPWM is applied to a 13-level H-bridge multilevel inverter (see FIG. 6).

전이 되어 있으므로 파워셀의 출력전압 위상이

씩 지연되는 형태로 나타난다. H-브릿지 멀티레벨 인버터 출력전압은 파워셀 출력전압의 합성이므로, 파워셀 출력전압의 위상지연은 결국 H-브릿지 멀티레벨 인버터 출력전압의 위상지연을 만들게 된다.The reference value of the H-bridge multilevel inverter output voltage applies equally to the power cells A1, A2, A3, A4, A5, and A6, but the carrier phase of the power cell is

Because of the transition, the output voltage phase of the power cell

It appears in the form of a delay. Since the H-bridge multilevel inverter output voltage is a composite of the power cell output voltages, the phase delay of the power cell output voltage eventually results in a phase delay of the H-bridge multilevel inverter output voltage.

가 1000㎲ 일 경우, 첫번째 파워셀

부터 여섯 번째 파워셀

까지의 출력전압의 위상지연 시간을 계산한 것이다.Equation (5) is that the number of power connected in series N on A is 6 and the sampling time is

Is 1000㎲, the first power cell

Sixth power cell

The phase delay time of the output voltage up to is calculated.

Equation 6 above calculates the phase delay of the H-bridge multilevel inverter output voltage due to the phase delay of the power cell output voltage.

The phase delay of the output voltage is not a problem in the open-loop control such as V / F, but the phase delay of the output voltage in the closed-loop control such as the vector control causes the current control to be difficult.

8 illustrates output voltage phase delay compensation in induction motor vector control using an H-bridge multilevel inverter.

The current is calculated by multiplying the output of the current controller (Equation 10) by a function (Equation 11) that compensates for the phase error caused by the output voltage phase delay (Equation (4)) of the H-bridge multilevel inverter (Equation 12). The instability of the controller (Current controller) was eliminated (Equation 13).

This delay of the output voltage can be ignored if the ratio of the sampling frequency to the output frequency is large enough.However, in the case of high-voltage, high-capacity H-bridge multilevel inverters, the sampling frequency is low due to the switching frequency limitation. The current controller becomes unstable as the motor speed increases due to the movement of the reference coordinate system.

The process of converting the H-bridge multilevel inverter output currents Ias, Ibs, and Ics into the synchronous DQ coordinate system Idse and Iqse during indirect vector control is represented by Equations 7, 8 and 9.

The output of the current controller is represented by the synchronous coordinate system Vdse, Vqse, and can be converted into the static coordinate system Vdss *, Vqss * by Equation 10 using the position information Equation 8 of the rotor flux.

However, when PSCPWM is applied to the H-bridge multilevel inverter, phase delay occurs in the output voltages of the individual power cells and the H-bridge multilevel inverter, and the delay angular velocity can be obtained as shown in Equation (11).

Where N is the power cell layer number, Ts is the sampling time of the current controller, and We is the synchronous angular velocity of the motor.

The phase delay of the output voltage increases in proportion to the current controller sampling time Ts and the motor speed.

Therefore, as the current controller sampling time increases and the motor speed increases, the phase delay of the output voltage increases so that the current controller operates unstablely.

Phase compensation of the output voltage is possible in the stationary DQ coordinate system from Equation 12, and the voltage reference value of the stationary abc coordinate system can be obtained as in Equation 13.

9A and 9B are diagrams showing the overall system configuration when the time delay compensation term of the current controller is applied to the induction motor vector control using the H-bridge multilevel inverter, which is a high-voltage motor variable speed device.

In the H-bridge multilevel inverter, six equivalent power cells are connected in series and are configured in three phases.

The control function of FIG. 8 is performed in the main controller of FIG. 9B, and the power cells A1-A6 of FIG. 9A through a voltage offset generation block, a controller area network, and an optical cable. B1-B6, C1-C6).

As described in detail above, the present invention has described a phase delay phenomenon and a compensation method of a current controller in an induction motor vector control using an H-bridge multilevel inverter. When applying the phase-shifted carrier-based PWM (PSCPWM) which has the advantage of decentralizing and modularizing the controller of the H-bridge multi-level inverter and simplicity of implementation, the output voltage reference value of the controller and the output of the actual H-bridge multi-level inverter The voltage is out of phase and the feedback control is unstable.

The causes and solutions of these are presented. The results of the present invention are 1) output voltage phase delay analysis of H-bridge multilevel inverter using PSCPWM 2) current controller instability problem in induction motor vector control using H-bridge multilevel inverter.

This method is effective for the H-bridge multilevel inverter system using PSCPWM under the condition that the switching frequency of the H-bridge multilevel inverter is low in time and the motor speed is high.

Claims (4)

In a motor feedback control method using an H-bridge multilevel inverter in which six equivalent power cells (A1 to A6, B1 to B6, and C1 to C6) are connected in series, The output voltage phase delays of the power cells and the H-bridge multilevel inverters are respectively detected, and the current controller output is multiplied by a function for compensating for the error caused by the phase delays to enable phase compensation of the output voltage in the stationary DQ coordinate system. A motor feedback control method using an H-bridge multilevel inverter characterized in that the instability factor of the controller is eliminated. The method of claim 1, wherein the phase delay of the power cell

Is calculated by the formula The phase delay of the H-bridge multilevel inverter output voltage

Is calculated by only,

Is the power cell output voltage of each phase of the H-bridge multilevel inverter,

Is the output voltage reference value,

Is the number of the power cell,

Is the total number of power cells connected in series per phase,

Motor feedback control method using an H-bridge multi-level inverter, characterized in that the PWM sampling time. The method of claim 1, wherein the function of compensating for the phase error is

Motor feedback control method using an H-bridge multi-level inverter, characterized in that calculated by. The method of claim 1, wherein the phase compensation of the output voltage in the stationary DQ coordinate system

Motor feedback control method using an H-bridge multi-level inverter, characterized in that calculated by.

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