JP5910001B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device that can suppress a surge voltage generated due to an on / off operation of a switching element.

  In general, when driving an AC motor, the voltage of the DC power supply is converted to a pulse voltage string equivalent to a sine wave by pulse width modulation (a waveform that becomes a sine wave when components above the switching frequency are removed). A modulated sinusoidal voltage is applied to the motor. FIG. 8 is a schematic configuration diagram of a system for driving an electric motor in such a manner. In the figure, 1 is a DC power source, 2 is a three-phase voltage type PWM inverter (hereinafter referred to as an inverter) connected to the DC power source 1, 3 is a control device for controlling the inverter 2, and 4 is driven by the inverter 2. This is an electric motor.

  The inverter 2 has a three-phase structure including a U-phase arm in which switching elements Q1 and Q2 are connected in series, a V-phase arm in which switching elements Q3 and Q4 are connected in series, and a W-phase arm in which switching elements Q5 and Q6 are connected in series. It consists of a bridge. The U-phase arm, the V-phase arm, and the W-phase arm are connected in parallel between the high potential side terminal P and the low potential side terminal N of the DC power source 1, respectively. The switching elements Q1 to Q6 are IGBTs that are one of semiconductor elements having a self-extinguishing function, and diodes are connected in antiparallel to each of the switching elements Q1 to Q6.

  The connection midpoint of each phase arm is also the output terminal of the inverter 2. Below, each is called output terminal U, V, W or U, V, W terminal. The U terminal is connected to the terminal Um of the electric motor 4. The V terminal is connected to the terminal Vm of the electric motor 4. The W terminal is connected to the terminal Wm of the electric motor 4.

  Connection between the inverter 2 and the electric motor 4 is performed by wiring, and a resistance component and an inductance component exist in the wiring. Furthermore, stray capacitance exists between the wirings of each phase between the inverter 2 and the electric motor 4 and between the wirings of each phase and the ground or the reference potential. In FIG. 8, Ls represents the inductance of the wiring between the inverter 2 and the electric motor 4, and Cs represents the stray capacitance between the wiring of each phase and the ground or the reference potential. Note that the resistance component of each phase wiring is omitted.

  In such an electric motor drive system, the control device 3 turns on and off the switching elements Q1 to Q6 in the inverter 2 by a pulse width modulation calculation that compares the magnitude of a sine wave (modulation signal) and a triangular wave (carrier signal). Control signals G1 to G6 are generated. The inverter 2 converts the voltage of the DC power source 1 into a pulse-shaped pulse-shaped rectangular wave voltage by switching the on / off states of the switching elements Q1 to Q6 according to the control signals G1 to G6. The pulse-width-modulated pulse-shaped rectangular wave voltage is output to the output terminals U, V, and W of the inverter 2 and is applied to the input terminals Um, Vm, and Wm of the electric motor 4 through the wiring.

  By the way, as shown in the drawing, an inductance Ls and a stray capacitance Cs exist in the wiring between the inverter 2 and the electric motor 4. When the pulse-shaped pulse-shaped rectangular wave voltage subjected to pulse width modulation is applied to the LC circuit composed of the inductance Ls and the stray capacitance Cs, a resonance phenomenon occurs between the inverter 2 and the LC circuit.

FIG. 9 is a diagram showing a resonance voltage generated between the input terminals Um-N of the electric motor 4 when the switching element Q1 of the inverter 2 performs an on / off operation.
Hereinafter, the potential reference point of each terminal is the potential of the low potential side terminal N (hereinafter also referred to as N terminal) of the DC power supply 1.

  When the control signal G1 of the switching element Q1 changes from Low to High, the switching element Q1 changes from the off state to the on state. When the switching element Q1 changes from the off state to the on state, the potential of the output terminal U of the inverter 2 changes from 0 [V] to the voltage Ed [V] of the DC power supply 1. The potential of the output terminal U of the inverter 2 is applied to the input terminal Um of the electric motor 4. At this time, LC resonance occurs between the inverter 2, the inductance Ls, and the stray capacitance Cs, and a resonance voltage is applied between the Um-N terminals of the electric motor 4.

  This resonance voltage is a surge voltage that attenuates and oscillates with time due to a resistance component (not shown) of the wiring between the inverter 2 and the electric motor 4, and the maximum value is the voltage Ed [ V] is approximately doubled. It is known that this excessive surge voltage and its time change rate dv / dt cause dielectric breakdown of the electric motor 4.

  As a measure to prevent breakdown of the motor due to such an excessive surge voltage, a surge voltage suppressor comprising a rectifier constituted by a diode bridge at the input terminal of the motor and a capacitor and a resistor connected in parallel at both ends of the DC terminal Has been proposed (see, for example, Patent Document 1). As an improvement, a surge voltage suppression device has been proposed in which a current flowing through a resistor connected to a DC terminal of a rectifier is controlled by a switching element (see, for example, Patent Document 2). In addition, a surge voltage suppression method has been proposed in which the DC terminal of the rectifier is connected to the input terminal of the inverter and the energy of the surge voltage is regenerated to the power source (see, for example, Patent Document 3). Further, a surge voltage suppression method has been proposed in which a reactor is connected between an inverter and an electric motor, and a series body of a resistor and a capacitor is connected in parallel to the reactor (see, for example, Patent Document 4).

JP-A-8-23682 JP 2006-115667 A JP 2010-136564 A JP 2007-166708 A

  However, in the above measures, it is necessary to add a surge voltage suppression device composed of a rectifier, a resistor, a capacitor, and a surge voltage suppression circuit composed of a reactor, a resistor, and a capacitor in order to suppress the surge voltage. This will lead to higher prices.

  The present invention seeks to solve the problems of such a conventional surge voltage suppressor, and its purpose is to add no special parts or a minimum number of parts. It is providing the power converter device which can suppress the surge voltage applied to an electric motor.

In order to achieve the above object, a control device according to the present invention operates a switching element connected in series between a high potential side terminal and a low potential side terminal of a DC power supply to turn on and off the voltage of the DC power supply. After the voltage is converted to the above voltage, the power conversion device that shapes the waveform by the filter circuit and supplies it to the load is controlled. That is, the control device according to the present invention includes a switching element connected to a high potential side terminal of a DC power source in the switching element group during a period in which a positive current is output from the switching element group connected in series. A control signal for on / off operation and a control signal for turning off the switching element connected to the low potential side terminal are generated. On the other hand, the control device according to the present invention includes a switching element connected to a low potential side terminal of a DC power source in the switching element group during a period in which a negative polarity current is output from the switching element group connected in series. A control signal for on / off operation and a control signal for turning off the switching element connected to the high potential side terminal are generated. In the control device according to the present invention, the control signal for turning on the switching element is followed by a first on signal that is turned on for the first on time after the first off time is off, and the first on signal. A second on signal that is turned on for a second on time after the second off time is off, and a control signal for turning the switching element off is supplied from the start of the first off time to the second on signal. It is kept off until the end of time .

  Further, the first off time is set so that a short circuit does not occur between the switching element connected to the high potential side terminal of the DC power supply and the switching element connected to the low potential side terminal. Is set to the time when is simultaneously off.

Furthermore, the first on-time and the second off-time are set to a time width that is 1/6 of the resonance period of the filter circuit.
Further, the control signal for turning on the switching element can be composed of a third on signal in addition to the first on signal and the second on signal.

The third ON signal is a signal that is turned ON for the third ON time after the third OFF time is OFF after the second ON signal.
Further, the third off time and the third on time are set to a time width of 1/6 of the resonance period of the filter circuit.

In addition, the control device according to the present invention can adjust the first on-time and the second off-time and the third off-time and the third on-time according to a change in the resonance period of the filter circuit.
In other words, the control device according to the present invention provides a first on-time, a second off-time, a third off-time, and a third on-time with the magnitude of the current output from the switching elements connected in series or the filter circuit. It can adjust according to the inductance value of the reactor to comprise.

  Further, the power conversion device according to the present invention turns on and off the switching element group connected in series between the high potential side terminal and the low potential side terminal of the DC power source based on the control signal generated by the control device. In operation, the voltage of the DC power source is converted into a pulse train voltage, and then the waveform is shaped by a filter circuit and supplied to a load.

  The power conversion device according to the present invention can prevent the upper and lower arms from being short-circuited when the switching element connected to the high-potential side terminal or the low-potential side terminal of the DC power supply is turned on and off at a high frequency. By canceling the oscillating voltage generated in the filter circuit during operation, the surge voltage generated at the input terminal of the load such as an electric motor can be suppressed.

It is a figure for demonstrating embodiment of the power converter device which concerns on this invention. It is a figure for demonstrating the block diagram which produces | generates the control signal G1 of the switching element Q1. It is a figure for demonstrating the relationship between the PWM signal when the polarity of U-phase current is positive, and the control signal of a switching element, (a) is PWM signal PWMu, (b) is control signal G1, (c) is This is the control signal G2. It is a figure for demonstrating the relationship between the PWM signal when the polarity of U-phase current is negative, and the control signal of a switching element, (a) is PWM signal PWMu, (b) is control signal G1, (c) is This is the control signal G2. It is a figure for demonstrating suppression of the surge voltage which generate | occur | produces when a switching element turns ON, (a) is PWM signal PWMu, (b) is control signal G1, (c) is a voltage waveform between UN terminals, (D) is a first step voltage waveform, (e) is a second step voltage waveform, (f) is a third step voltage waveform, (g) is a resonance voltage waveform generated by each step voltage, and (h) is It is a voltage waveform between Um-N terminals. It is a figure for demonstrating suppression of the surge voltage which generate | occur | produces when a switching element turns off, (a) is PWM signal PWMu, (b) is control signal G1, (c) is a voltage waveform between UN terminals, (D) is a fourth step voltage waveform, (e) is a fifth step voltage waveform, (f) is a sixth step voltage waveform, (g) is a resonance voltage waveform generated by each step voltage, and (h) is It is a voltage waveform between Um-N terminals. It is a figure for demonstrating the relationship between the inductance value of a reactor, and an electric current. It is a figure for demonstrating the power converter device which concerns on a prior art. It is a figure for demonstrating the surge voltage which generate | occur | produces in an electric motor input terminal when an electric motor is driven with the power converter device shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 7, the same reference numerals are given to the same components as those shown in FIG. 8, and the description thereof is omitted.

  FIG. 1 is a diagram for explaining an embodiment of a power converter according to the present invention. In the figure, the DC power source 1, the inverter 2, the electric motor 4, the wiring inductance Ls, and the stray capacitance Cs are the same as those shown in FIG.

  A filter circuit including a reactor Lf and a capacitor Cf is provided at the output portion of the inverter 2. Reactor Lf is inserted between output terminals U, V, W of inverter 2 and input terminals Um, Vm, Wm of electric motor 4. Capacitor Cf has one end connected to each terminal U1, V1, W1 of reactor Lf, and the other end connected to the N terminal side of DC power supply 1 at once.

  Between the filter circuit and the electric motor 4, a current detector 5 for detecting the U-phase current, the V-phase current and the W-phase current flowing in the electric motor 4 is provided. Detection signals Iu, Iv, and Iw of each phase current detected by the current detector 5 are input to the control device 3a.

  The control device 3a performs an adjustment operation so that the phase current detection signals Iu, Iv, and Iw of the respective motors coincide with the command values of the respective phase currents, and generates output voltage commands for the respective phases. Further, pulse width modulation calculation is performed using the generated output voltage command for each phase, and control signals G1 to G6 described later are generated.

  Switching elements Q1 to Q6 of inverter 2 perform an on / off operation in accordance with control signals G1 to G6 generated by control device 3a. That is, the switching elements Q1 to Q6 are turned on when the control signals G1 to G6 are High, and the switching elements Q1 to Q6 are turned off when the control signals G1 to G6 are Low.

As a result of the on / off operation of the switching elements Q1 to Q6, the inverter 2 outputs a three-phase AC voltage (pulse-width-modulated rectangular wave pulse voltage train).
The pulse-width-modulated rectangular wave pulse voltage train output from the inverter is shaped into a substantially sinusoidal three-phase AC voltage by the filter circuit described above and applied to the motor 4.

  Here, if the inductance value of the reactor Lf and the capacitance value of the capacitor Cf are selected to be approximately 10 times or more than the inductance value of the wiring inductance Ls and the capacitance value of the stray capacitance Cs, the inductance Ls and the stray capacitance Cs The rise and fall of the voltage applied to the configured LC circuit becomes gradual. As a result, the resonance of the LC circuit composed of the inductance Ls and the stray capacitance Cs can be suppressed.

  However, it is conceivable that resonance occurs between the inserted filter circuit and the inverter 2. The resonance period T of the filter circuit is determined by the inductance value L [H] of the reactor Lf and the capacitance value C [F] of the capacitor Cf, and T = 2π√ (LC) [s].

  Therefore, in order to cancel the resonance generated in the filter circuit, the control device 3a is configured with the first ON signal G01, the second ON signal G02, and the third ON signal G03 as the control signals of the respective switching elements to be generated. To do.

Hereinafter, a method for generating a control signal for the switching element and a configuration of the control signal will be described.
FIG. 2 is a control block diagram for generating control signals G1 and G2 of the switching elements Q1 and Q2 connected in series between the high potential side terminal and the low potential side terminal of the DC power supply 1.

  FIG. 3 shows one pulse of the PWM signal PWMu generated in a period in which the polarity of the U-phase current is positive (the polarity signal Iup is High) (a signal that becomes Low again after having become High for a predetermined time from the Low state) The relationship between the control signal G1 and the control signal G2 generated based on the PWM signal PWMu is represented by a timing chart.

  In FIG. 2, 301 is a means for adding a pause time Td, 302 is a pulse signal generation means, 303 is a delay signal generation means, 304 is an exclusive logical operation means (XOR), and 305 is a logical product operation means (AND). The output of the AND operation means 305 becomes the control signal G1 for the switching element Q1.

  First, a U-phase PWM signal PWMu is generated by PWM signal generation means (not shown). The PWM signal PWMu is obtained by comparing the magnitude of a sine wave signal (modulation signal) obtained by normalizing the U-phase output voltage command with the voltage of the DC power supply 1 and a triangular wave signal (carrier signal).

  The pause time adding means 301 adds a pause time Td to the U-phase PWM signal PWMu. This pause time is added only when the PWM signal PWMu changes from Low to High. The idle time Td is an off period provided in order to prevent the switching elements Q1 and Q2 from being simultaneously turned on and causing a short circuit, that is, a period in which the switching elements Q1 and Q2 are simultaneously turned off.

  Therefore, the PWM signal PWMu ′ to which the pause time Td is added is a signal that becomes High after being delayed by the pause time Td from the original PWM signal PWMu, and becomes Low simultaneously with the original PWM signal PWMu.

  The pulse signal generation unit 302 generates a signal Gt1 that becomes High only for the time T1 at the rising and falling timings of the PWM signal PWMu ′ to which the pause time Td is added. Time T1 is 1/6 time of the resonance period of the filter circuit.

  The delay signal generation unit 303 generates a signal Gt2 in which the rise and fall timings of the PWM signal PWMu ′ to which the pause time Td is added are delayed by the time T2. Time T2 is set to be twice as long as time T1.

The exclusive logic operation means 304 performs an exclusive logic operation between the signal Gt1 output from the pulse signal generation means 32 and the signal Gt2 output from the delay signal generation means 303.
The AND operation means 305 performs an AND operation between the signal output from the exclusive logic operation means 304 and the polarity signal Iup of the U-phase current, and generates a control signal G1 for the switching element Q1.

  By calculating in this way, the first ON signal G01 and the second ON signal are generated with respect to the U-phase PWM signal PWMu (FIG. 3A) that becomes High again after a predetermined time Low from the High state. A control signal G1 (FIG. 3B) composed of the signal G02 and the third ON signal G03 is generated.

  Specifically, the first on signal G01 includes a signal that is turned off for the first off time after the PWM signal PWMu becomes High, and a signal that is turned on for the first on time thereafter. The first off time is the pause time Td. The first on-time is time T1.

  The second on signal G02 is composed of a signal that is turned off for the second off time after the first on time of the first on signal G01 has passed, and a signal that is turned on for the second on time after that. The second off time is time T1. The second on-time is a time until the PWM signal PWMu becomes Low after the second off-time has elapsed.

  The third on signal G03 includes a signal that turns off for the third off time after the second on time of the second on signal G02 elapses, and a signal that turns on for the third on time after that. The third off time and the third on time are time T1.

On the other hand, the control signal G2 of the switching element Q2 is always low because the polarity of the U-phase current is positive (FIG. 3C).
Next, when the polarity of the U-phase current is negative (the polarity signal Iup is Low), the control signal G2 of the switching element Q2 is a signal obtained by inverting the polarity signal Iup of the U-phase current with High and Low by the logical inversion operator 311. And the PWM signal PWMu can be generated by using a signal obtained by inverting High and Low by the logic inversion operator 312.

  The method of generating the control signal G2 of the switching element Q2 is the same as the method of generating the control signal G1 of the switching element Q1 except that the inverted signal of the polarity signal Iup of the U-phase current and the inverted signal of the PWM signal PWMu are used. The description is omitted.

  FIG. 4 shows one pulse of the PWM signal PWMu generated in a period in which the polarity of the U-phase current is negative (the polarity signal Iup is Low), and the control signal G1 and the control signal G2 generated based on the PWM signal PWMu. The relationship is represented by a timing chart.

FIG. 4A shows a PWM signal PWMu that becomes High again after a predetermined time Low from the High state.
FIG. 4B shows a control signal G1 for the switching element Q1. The control signal G2 of the switching element Q2 is always low because the polarity of the U-phase current is negative.

  FIG. 4C shows the control signal G2 for the switching element Q2. The control signal G2 for the switching element Q2 is a signal composed of a first on signal G01, a second on signal G02, and a third on signal G03.

  Specifically, the first on signal G01 includes a signal that is turned off for the first off time after the PWM signal PWMu becomes Low, and a signal that is turned on for the first on time thereafter. The first off time is the pause time Td. The first on-time is time T1.

  The second on signal G02 is composed of a signal that is turned off for the second off time after the first on time of the first on signal G01 has passed, and a signal that is turned on for the second on time after that. The second off time is time T1. The second on-time is a time until the PWM signal PWMu becomes High after the second off-time has elapsed.

  The third on signal G03 includes a signal that turns off for the third off time after the second on time of the second on signal G02 elapses, and a signal that turns on for the third on time after that. The third off time and the third on time are time T1.

  The pause time adding means 301 may add the pause time Td only when the PWM signal PWMu first changes from Low to High after the polarity signal Iup of the U-phase current changes from Low to High. good. Similarly, the pause time adding means 321 adds the pause time Td only when the PWM signal PWMu first changes from High to Low after the polarity signal Iup of the U-phase current changes from High to Low. Also good.

  By doing so, the PWM signal PWMu and the PWM signal PWMu ′ can be matched in the period when the polarity signal Iup of the U-phase current thereafter is High and Low, and a voltage closer to the output voltage command is generated at the U terminal. Control signals G1 and G2 can be generated.

  The control device 3a generates the control signals G3 and G4 of the switching elements Q3 and Q4 using the V-phase PWM signal PWMv, and uses the W-phase PWM signal PWMw to control the control signals G5 of the switching elements Q5 and Q6. , G6.

  Control signals G3 and G4 of switching elements Q3 and Q4 and control signals G5 and G6 of switching elements Q5 and Q6 can be generated using substantially the same function as the block diagram shown in FIG.

  Switching elements Q1 to Q6 of inverter 2 perform an on / off operation in accordance with control signals G1 to G6 generated in this way. Accordingly, the switching elements Q1 to Q6 can be turned on / off at a high frequency because the other switching element of the same phase is always turned off.

  The voltage of the DC power source 1 is converted into a pulse wave train of rectangular wave shape that is pulse width modulated by the on / off operation of the switching elements Q1 to Q6. This pulse voltage train is output to the output terminals U, V, and W of the inverter 2, shaped by a filter circuit including the reactor Lf and the capacitor Cf, and then applied to the input terminals Um, Vm, and Wm of the electric motor 4. The

  FIG. 2 is an example of a control block diagram for generating a control signal for the switching element in the control device according to the present invention. Therefore, as long as the control signal of the switching element shown in FIGS. 3 and 4 can be generated, the control signal is not limited to the control block diagram of FIG. 2, and the control signal may be generated by another method.

  Next, with reference to FIGS. 5A to 5H, in the motor drive system shown in FIG. 1, the principle that the surge voltage generated when the switching element Q1 shifts from the off state to the on state is suppressed. explain. The reference point for the potential of each terminal is the potential of the N terminal of the DC power supply 1.

FIG. 5A shows the U-phase PWM signal PWMu.
FIG. 5B shows a control signal G1 for the switching element Q1. Here, among the control signals G1 shown in FIG. 3B, the first on signal G01 and the second on signal G02 are shown. The timing at which the first on signal G01 changes from low to high is the first timing, the timing at which the first on signal G01 changes from high to low is the second timing, and the second on signal G02 changes from low to high. Let timing be the third timing.

  Since the third ON signal G03 is a signal for suppressing the surge voltage when the switching element Q1 shifts from the ON state to the OFF state, the details thereof will be described later and the description thereof is omitted here.

FIG. 5C shows a voltage waveform appearing between the U terminal and the N terminal as a result of the switching element Q1 being turned on and off.
The switching element Q1 sequentially shifts from the off state to the on state at the first timing, the off state at the second timing, and the on state at the third timing in accordance with the control signal G1. As a result, the voltage between the U and N terminals of the inverter 2 changes from 0 [V] → Ed [V] → 0 [V] → Ed [V] corresponding to the control signal G1.

Here, changes in voltage at the first, second, and third timings are defined as a first step voltage, a second step voltage, and a third step voltage, respectively.
The voltage output between the U and N terminals of the inverter 2 can be regarded as a combined voltage of the first step voltage, the second step voltage, and the third step voltage shown in FIGS. it can.

  The first step voltage is a rectangular wave voltage that becomes the positive amplitude value Ed [V] at the first timing from the initial voltage 0 [V] (FIG. 5D). The second step voltage is a rectangular wave voltage that becomes the negative amplitude value −Ed [V] at the second timing from the initial voltage 0 [V] (FIG. 5E). The third step voltage is a rectangular wave voltage that becomes the positive amplitude value Ed [V] at the third timing from the initial voltage 0 [V] (FIG. 5F).

Each step change of the voltage at the first to third timings causes resonance of the filter circuit including the reactor Lf and the capacitor Cf shown in FIG.
As shown in FIG. 5G, the resonance voltage Vr1 generated by the first step voltage is a sine wave voltage having an initial voltage 0 [V], a center voltage Ed [V], and an amplitude value Ed [V]. The resonance voltage Vr2 generated by the second step voltage is a sine wave voltage having an initial voltage 0 [V], a center voltage −Ed [V], and an amplitude Ed [V]. The resonance voltage Vr3 generated by the third step voltage is a sine wave voltage having an initial voltage 0 [V], a center voltage Ed [V], and an amplitude Ed [V].

  Further, when the inductance value of the reactor Lf is L [H] and the capacitance value of the capacitor Cf is C [F], the period T of the resonance voltages Vr1 to Vr3 generated by the first to third step voltages is T = 2π√ ( LC) [s]. Therefore, the resonance frequency f is 1 / T [Hz], and the angular frequency ω is 2πf [rad / s].

  Here, if the time T1 is set to 1/6 of the resonance period T, the resonance voltages Vr2 and Vr3 generated by the second step voltage and the third step voltage are the resonance voltage Vr1 generated by the first step voltage. In contrast, the phases are respectively (4π / 3) [rad] delayed and (2π / 3) [rad] delayed.

  Therefore, the resonance voltages Vr1 to Vr3 generated by the first to third step voltages are Vr1 = Ed {1 + sin [ωt]}, Vr2 = −Ed {1−sin [ωt− (4π / 3)]}, Vr3 = It is represented by Ed {1 + sin [ωt− (2π / 3)]}.

  From the above, the voltage generated between the U1 terminal and the N terminal of the filter circuit between the first timing and the third timing is generated by the resonance voltage Vr1 generated by the first step voltage and the second step voltage. The resonance voltage Vr2 is combined (FIG. 5 (h)). Therefore, the voltage generated between the U1-N terminals during this period is a voltage having a more gradual rise than the resonance voltage shown in FIG.

  The voltage generated between the U1 and N terminals after the third timing is a voltage obtained by synthesizing the resonance voltages Vr1 to Vr3. Therefore, the voltage generated between the U1 and N terminals after the third timing is a direct current of Ed [V] (FIG. 5 (h)).

  As described above, in the power conversion device according to the present invention, when the switching element shifts from the off state to the on state, the on / off operation is performed with a predetermined time width, so that the resonance voltage generated in the filter circuit is canceled out. . As a result, the voltage between the U1 terminal and the N terminal of the filter circuit is a voltage that gradually rises from 0 [V] to the voltage Ed [V] of the DC power supply 1. As a result, a voltage with a suppressed surge voltage is applied to the input terminals Um, Vm, and Wm of the electric motor 4.

  Next, in the electric motor drive system shown in FIG. 1, the principle that the surge voltage generated when the switching element Q1 of the inverter 2 shifts to the off state is suppressed will be described with reference to FIGS. explain. The potential reference point of each terminal is the potential of the N terminal of the DC power supply 1.

FIG. 6A shows a U-phase PWM signal PWMu.
FIG. 6B shows a control signal G1 for the switching element Q1. Here, among the signals shown in FIG. 3B, the second ON signal G02 and the third ON signal G03 are shown. The timing when the second ON signal G02 changes from High to Low is the fourth timing, the timing when the third ON signal G03 changes from Low to High, the fifth timing, and the third ON signal G03 changes from High to Low. The timing is the sixth timing.

FIG. 6C shows a voltage waveform appearing between the U terminal and the N terminal as a result of the switching element Q1 being turned on and off.
The switching element Q1 sequentially shifts from the on state to the off state at the fourth timing, the on state at the fifth timing, and the off state at the sixth timing in accordance with the control signal G1. As a result, the voltage between the U and N terminals of the inverter 2 changes from Ed [V] → 0 [V] → Ed [V] → 0 [V] corresponding to the control signal G1.

Here, the voltage changes at the fourth, fifth, and sixth timings are defined as a fourth step voltage, a fifth step voltage, and a sixth step voltage, respectively.
As shown in FIGS. 6C to 6F, the voltage output between the UN terminals of the inverter 2 is a composite voltage of the fourth step voltage, the fifth step voltage, and the sixth step voltage. Can be caught.

  The fourth step voltage is a rectangular wave voltage that becomes 0 [V] at the first timing from the initial voltage Ed [V]. The fifth step voltage is a rectangular wave voltage that becomes 0 [V] at the second timing from the initial voltage −Ed [V]. The sixth step voltage is a rectangular wave voltage that becomes 0 [V] at the third timing from the initial voltage Ed [V].

By the way, the voltage step change from the fourth timing to the sixth timing causes resonance of the filter circuit composed of the reactor Lf and the capacitor Cf shown in FIG.
As shown in FIG. 6G, the resonance voltage Vr4 generated by the fourth step voltage is a sine wave voltage having an initial voltage Ed [V], a center voltage 0 [V], and an amplitude Ed [V]. The resonance voltage Vr5 generated by the fifth step voltage is a sine wave voltage having an initial value −Ed [V], a center voltage 0 [V], and an amplitude Ed [V]. The resonance voltage Vr6 generated by the sixth step voltage is a sine wave voltage having an initial voltage Ed [V], a center voltage 0 [V], and an amplitude Ed [V].

  The period T of the resonance voltages Vr4 to Vr6 generated by the fourth to sixth step voltages is T = 2π√ (LC) [s]. Therefore, the resonance frequency f is 1 / T [Hz], and the angular frequency ω is 2πf [rad / s].

  Here, if the time T1 is set to 1/6 of the resonance period T of Vr4 to Vr6, the resonance voltages Vr5 and Vr6 generated by the fifth step voltage and the sixth step voltage are resonances generated by the fourth step voltage. The phase of the voltage Vr4 is (4π / 3) [rad] delayed and (2π / 3) [rad] delayed.

Then, the resonance voltages Vr4 to Vr6 generated by the fourth to sixth step voltages are
Vr4 = Edsin [ωt], Vr5 = Edsin [ωt− (4π / 3)], and Vr6 = Edsin [ωt− (2π / 3)].

  From the above, the voltage generated between the U1 terminal and the N terminal of the filter circuit between the fourth timing and the sixth timing is generated by the resonance voltage Vr4 generated by the fourth step voltage and the fifth step voltage. The resonance voltage Vr5 is a synthesized voltage (FIG. 6 (h)). Therefore, the voltage generated between the U1 and N terminals during this period is a voltage having a more gradual fall than the resonance voltage shown in FIG.

  The voltage generated between the U1 and N terminals after the sixth timing is a voltage obtained by synthesizing the resonance voltages Vr4 to Vr6. Accordingly, the voltage generated between the U1 and N terminals after the sixth timing is a direct current having a magnitude of 0 [V] (FIG. 6H).

  That is, in the power conversion device according to the present invention, when the switching element Q1 shifts from the on state to the off state, the on / off operation is performed with a predetermined time width, so that the resonance voltage generated in the filter circuit is canceled. As a result, the voltage between the U1 terminal and the N terminal of the filter circuit is a voltage that gradually falls from the voltage Ed [V] to 0 [V] of the DC power supply 1. As a result, a voltage with a suppressed surge voltage is applied to the input terminals Um, Vm, and Wm of the electric motor 4.

  As described above, when the switching element Q1 changes from the off state to the on state and when the switching element Q1 changes from the on state to the off state, the voltage between the U1 terminal and the N terminal of the filter circuit changes gently. When the other switching elements Q2 to Q6 change from the off state to the on state and when the switching element Q2 changes from the on state to the off state, the U1 terminal, the V1 terminal, and the W1 terminal of the filter circuit are substantially the same in principle. And the N terminal change slowly. As a result, a voltage with a suppressed surge voltage is applied to the input terminals Um, Vm, and Wm of the electric motor 4.

Next, a method for canceling the resonance voltage generated in the filter circuit even when the resonance period T of the filter circuit changes depending on the circuit operation state will be described.
The resonance period T of the filter circuit including the reactor Lf and the capacitor Cf is represented by T = 2π√ (LC) [s]. That is, the resonance period T is directly proportional to the square root of the inductance value L of the reactor Lf.

  Further, it is known that there is a relationship shown in FIG. 7 between the inductance value L of the reactor Lf and the current If flowing through the coil of the reactor Lf. A magnetic material typified by a ferrite magnet or an amorphous alloy is used for the core material of the reactor Lf. A reactor using such a magnetic material for the iron core has a characteristic that the inductance value L decreases as the value of the current If flowing through the coil increases.

  When the inductance value L changes as the value of the current If flowing through the coil increases, a deviation occurs between the resonance period T of the set filter circuit and the periods of the actually generated resonance voltages Vr1 to Vr3 and Vr4 to Vr6. As a result, the resonance voltage generated in the filter circuit is not sufficiently canceled out, and the surge voltage suppression effect is reduced.

Therefore, it is necessary to adjust the times T1 and T2 in direct proportion to the length of the resonance period T of the filter circuit so that the resonance voltage is surely canceled.
As described above, the resonance period T of the filter circuit is directly proportional to the square root of the inductance value L of the reactor Lf. Therefore, if the times T1 and T2 are adjusted so as to be directly proportional to the square root of the inductance value L of the reactor Lf, the resonance voltage is effectively canceled. Even if the square value of the times T1 and T2 is adjusted to be directly proportional to the inductance value L of the reactor Lf, the resonance voltage is effectively canceled out.

  For example, the inductance value L of the reactor Lf is set to the current value flowing through the reactor Lf by providing a data table indicating the relationship between the inductance value L of the reactor Lf and the current value flowing through the coil shown in FIG. Can be based on.

  As shown in FIG. 1, the current value detected by the current detector 5 provided between the filter circuit including the reactor Lf and the capacitor Cf and the motor 4 can be used as the current value flowing through the reactor Lf. When the ratio of the current flowing to the capacitor Cf out of the current flowing to the reactor Lf is small, the time T1 can be made substantially coincident with the time 1/6 of the resonance period T. Since the time T2 is set to be twice as long as the time T1, the time T2 substantially coincides with the time of 1/3 of the resonance period T.

  In order to more accurately detect the current flowing through the reactor, the current detector 5 may be provided between the inverter 2 and the reactor Lf or between the reactor Lf and the U1 terminal to W1 terminal. The time T1 can be made to coincide more accurately with the time 1/6 of the resonance period T. Similarly, the time T2 can be made to coincide more accurately with the time of 1/3 of the resonance period T.

  Further, the resonance period T of the filter circuit is calculated from the inductance value L of the reactor Lf and the capacitance value C of the capacitor Cf obtained as described above, and the times T1 and T2 are adjusted in direct proportion to the calculated resonance period T. it can.

  Further, a data table indicating the phase between the resonance period T of the filter circuit obtained as described above and the current value flowing through the reactor is created in advance and provided in the control device 3a, and this table is referred to based on the current value flowing through the reactor Lf. The times T1 and T2 can be adjusted in direct proportion to the resonance period obtained by referring to the table.

  Thus, by adjusting the time T1 to be 1/6 of the resonance period of the filter circuit and adjusting the time T2 to be twice the time T1, the effect of canceling the resonance voltage in the filter circuit can be ensured. Can be demonstrated. As a result, the surge voltage generated at the input terminal of the electric motor 4 can be effectively suppressed.

The adjustment of the time T1 and the time T2 is performed by the pulse signal generation means 302 and 322 and the delay signal generation means 303 and 323 in the control block diagram shown in FIG.
In the embodiment of the present invention described above, the operation and effect of the present invention have been described by taking an example of an electric motor drive system using a three-phase voltage type PWM inverter. However, the load of the inverter is not limited to the electric motor, and an electric circuit other than the electric motor or Even an inverter that uses an electrical component as a load can exhibit the same operations and effects. The inverter is not limited to a three-phase inverter, and may be a single-phase or a multi-phase inverter having three or more phases. Further, the inverter is not limited to a two-level inverter, and may be a multi-level inverter having three or more levels.

  Further, the modulation method is not limited to PWM modulation, and any method may be used as long as a rectangular wave voltage is output to the load.

  DESCRIPTION OF SYMBOLS 1 ... DC power source, 2 ... Inverter 3, 3a ... Control device, 4 ... Electric motor, 5 ... Current detector, Ls ... Inductance of wiring, Cs ... Stray capacitance, Lf ... Reactor, Cf ... Capacitor

Claims (10)

The switching element group connected in series between the high potential side terminal and the low potential side terminal of the DC power supply is turned on and off to convert the voltage of the DC power supply to a pulse train voltage, and then the waveform is shaped by the filter circuit and then loaded. A control device for a power conversion device to be supplied to
A control signal for turning on / off a switching element connected to the high potential side terminal of the DC power source in the switching element group during a period in which a positive current is output from the switching element group connected in series; Generating a control signal for turning off the switching element connected to the low potential side terminal,
A control signal for turning on / off a switching element connected to the low potential side terminal of the DC power source in the switching element group during a period of outputting a negative current from the switching element group connected in series; Generating a control signal for turning off the switching element connected to the high potential side terminal,
A control signal for turning on the switching element includes a first on signal that is turned on for the first on time after the first off time is off, and a second off time off that follows the first on signal, And a second on signal that is turned on for two on-times, and a control signal for turning off the switching element is maintained in the off-state from the start of the first off-time to the end of the second on-time. A control device for a power conversion device.   The first off-time is configured so that a short circuit does not occur between the switching element connected to the high potential side terminal and the switching element connected to the low potential side terminal of the DC power supply. The control device for the power conversion device according to claim 1, wherein the time is simultaneously off.   3. The control device for a power converter according to claim 2, wherein the first on-time and the second off-time are set to a time width of 1/6 of a resonance period of the filter circuit.   A control signal for turning on the switching element is composed of a third on signal in addition to the first on signal and the second on signal, and the third on signal is the second on signal. 4. The control device for a power converter according to claim 3, wherein the third on-time is turned on after the third off-time is turned off following the on signal.   5. The control device for a power converter according to claim 4, wherein the third off time and the third on time are set to a time width that is 1/6 of a resonance period of the filter circuit.   6. The control device for a power converter according to claim 1, wherein the filter circuit is a circuit including a reactor and a capacitor.   The first on-time and the second off-time, and the third off-time and the third on-time are adjusted according to a change in a resonance period of the filter circuit. Control device for power converter.   The first on-time and the second off-time, and the third off-time and the third on-time are adjusted according to the magnitude of the current output from the switching elements connected in series. The control apparatus of the power converter device of Claim 6.   The power converter according to claim 6, wherein the first on-time and the second off-time and the third off-time and the third on-time are adjusted according to an inductance value of the reactor. Control device.   A switching element group connected in series between the high potential side terminal and the low potential side terminal of the DC power source is turned on and off based on the control signal generated by the control device according to claim 1 to claim 9, A power conversion device, wherein the voltage of the DC power supply is converted into a pulse train voltage, and then the waveform is shaped by a filter circuit and supplied to a load.

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