JP2016165201A - Inverter device and vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter device and a vehicle which improves operation efficiency with the suppression of a motor torque ripple.SOLUTION: The inverter device includes: a converter circuit 10 which includes a multilevel inverter INV and power detector parts 12U to 12W which detect output power from the inverter INV to a motor 40; and a control circuit 20. The control circuit 20 includes: a table having a plurality of equivalent carrier frequencies which are set according to the amplitude of a voltage command; a carrier generator part 28 which calculates the voltage command amplitude based on an externally input current command, and reads from the table the equivalent carrier frequency corresponding to the voltage command amplitude, to generate a carrier signal using the equivalent carrier frequency; and a comparison part 26 which performs PWM modulation of a voltage command using the carrier signal, to output to each switching element.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to an inverter device and a vehicle.

  Due to the multi-level inverter, various effects such as a reduction in loss, a reduction in device breakdown voltage, and a reduction in current pulsation are expected. The same applies to motor drive, and research is being conducted on reduction of motor loss by reducing pulsation of drive current of the motor and minimization of total loss of the inverter and the motor. In addition, the use of a multi-level inverter is also expected to have an effect on improving motor control performance.

  For example, when switching elements in an inverter, it is common to provide a dead time and apply a method to prevent a DC short circuit. However, due to a voltage error due to dead time and a zero current clamping phenomenon, the output current waveform of the motor It is known to distort. These distortions appear at multiples of 6 of the electrical angular frequency and cause current pulsations to increase. An increase in current pulsation increases torque pulsation (torque ripple), which causes deterioration in motor control performance.

  Also, current-induced torque ripple tends to increase when the motor operates at low speed and low current. This is because when the motor is operating at a low speed and a low current, the time ratio of the dead time to the pulse of PWM (pulse width modulation) that controls the switching element of the inverter becomes large.

T. Murai, T. Watanabe, and H. Iwasaki ‘’ Waveform Distortion and Correction Circuit for PWM Inverters with Switching Lag-Times, ”IEEE Transactions on Ind. Appl. Vol. IA-23, No.5 1987 Ito et al. “Analysis of dead time error compensation method using disturbance observer in vector control”, 2007 IEEJ Industrial Application Conference, 1-5

  Embodiments of the present invention have been made in view of the above circumstances, and an object of the present invention is to provide an inverter device and a vehicle that suppress torque ripple of a motor and improve driving efficiency.

  The inverter device according to the embodiment includes a plurality of upper switching elements connected in series and a plurality of lower switching elements connected in series, and the plurality of upper switching elements and the plurality of lower switching elements are connected in series. A converter circuit including a connected leg, and a power detection unit that detects output power supplied to an AC load from a connection between the plurality of upper switching elements and the plurality of lower switching elements, and a voltage command A table having a plurality of equivalent carrier frequencies set corresponding to the amplitude and an amplitude of a voltage command based on a current command input from the outside are calculated, and an equivalent carrier frequency corresponding to the amplitude of the voltage command is calculated from the table. A carrier generation unit for reading and generating a carrier signal using the equivalent carrier frequency, and using the carrier signal The serial voltage command to the PWM modulation, comprising a comparator for outputting to each of the switching elements, and a control circuit having a a.

FIG. 1 is a block diagram schematically illustrating a configuration example of an inverter device and a vehicle according to the first embodiment. FIG. 2 is a diagram for explaining an example of the operation of the control circuit of the inverter device according to the first embodiment. FIG. 3A is a diagram schematically illustrating an example of the influence of the dead time of the switching element on the output of the inverter in the gate drive device according to the first embodiment. FIG. 3B is a diagram schematically illustrating another example of the influence of the dead time of the switching element on the output of the inverter in the gate drive device according to the first embodiment. FIG. 4 is a diagram showing an example of the relationship between the equivalent carrier frequency and the distortion index in a two-level circuit for a plurality of modulation rates. FIG. 5 is a diagram showing an example of the relationship between the equivalent carrier frequency and the distortion index in a three-level circuit for a plurality of modulation rates. FIG. 6 is a diagram showing an example of the relationship between the ratio of the equivalent carrier frequency and the distortion index in a four-level circuit for a plurality of modulation rates. FIG. 7 is a block diagram schematically illustrating a configuration example of the inverter device according to the third embodiment. FIG. 8 is a diagram illustrating an example of a relationship between an equivalent carrier frequency and a distortion index in a two-level circuit when using an observer for a plurality of modulation rates. FIG. 9 is a diagram illustrating an example of a relationship between an equivalent carrier frequency and a distortion index in a three-level circuit when using an observer for a plurality of modulation rates. FIG. 10 is a diagram illustrating an example of a relationship between an equivalent carrier frequency and a distortion index in a four-level circuit when using an observer for a plurality of modulation rates. FIG. 11 is a flowchart illustrating an example of an operation for generating a carrier signal in the inverter device of the third embodiment. FIG. 12 is a flowchart for explaining another example of the operation of generating the carrier signal in the inverter device of the third embodiment.

Hereinafter, an inverter device and a vehicle according to an embodiment will be described in detail with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

FIG. 1 is a block diagram schematically illustrating a configuration example of an inverter device and a vehicle according to the first embodiment.
The vehicle of the present embodiment includes an inverter device, a DC power supply 30 as a DC load, a motor 40 as an AC load, and an axle driven by the power of the motor 40. The inverter device of the present embodiment includes a converter circuit 10 and a control circuit 20, and is connected to a DC power supply 30 and a motor 40.

  The inverter device is detachably connected to the DC power supply 30 and the load 40 via, for example, a connector. Note that in this specification, “connection” includes not only direct contact and connection but also a case of electrical connection through another conductive member or the like. In addition, the case of magnetic coupling through a transformer or the like is also included in “connection”.

  The DC power supply 30 supplies DC power to the inverter device. The DC power supply 30 may be, for example, one that rectifies system power to generate stable power, or may be power storage means such as a secondary battery or a capacitor. The DC power source 30 may be, for example, a gas turbine engine. The DC power supply 30 may be other than the above as long as it is an arbitrary power supply capable of supplying DC power. In the case where the DC power supply 30 is a power storage means, it is possible to store the power generated by the motor 40 via an inverter INV described later.

  The motor 40 is a part that converts electric energy into driving energy and rotates the main shaft of the motor 40. The motor 40 may be, for example, a permanent magnet (PM) motor using a permanent magnet or a reluctance motor without a permanent magnet. The motor 40 may be other than the above as long as it is an arbitrary motor that converts electric power into power. In the present embodiment, the motor 40 is, for example, a three-phase PM motor.

  The inverter device converts DC power supplied from the DC power source 30 into AC power corresponding to the motor 40, and outputs the converted AC power to the motor 40. The inverter device outputs active power or active power and reactive power to the motor 40. The inverter device is a so-called motor driver, a variable voltage variable frequency (VVVF) inverter. The voltage of the AC power output from the inverter device is, for example, 48V (effective value) or 100V (effective value). The frequency of the AC power output from the inverter device is variable from 0 Hz to 500 Hz, for example.

Converter circuit 10 includes an inverter INV and power detection units 12U to 12W.
A DC line of the inverter INV is connected to the DC power supply 30. The AC line of the inverter INV is connected to the motor 40. The inverter INV converts DC power supplied from the DC power supply 30 into AC power. In the present embodiment, the inverter INV is a three-phase AC inverter that converts DC power supplied from the DC power supply 30 into AC power corresponding to the motor 40.

  The power detection units 12U to 12W detect the output power of the converter circuit 10. The power detection units 12U to 12W include a voltage detector and a current detector. The voltage detector detects the output voltage of the converter circuit 10. The current detector detects an output current of an AC line connected between the inverter INV and the motor 40. For example, when the inverter INV is a three-phase inverter, the voltage detector detects the output voltage of each phase of the three-phase AC power, and the current detector detects the output current of each phase of the three-phase AC power. The voltage detector and the current detector are connected to the control circuit 20. The voltage detector supplies the detected output voltage to the control circuit 20. The current detector supplies the detected output current to the control circuit. That is, the power detection units 12U to 12W are connected to the control circuit 20 and input the detected output power to the control circuit 20.

  In this example, the power detection units 12U to 12W include a voltage detector and a current detector, but are not limited to this. For example, the power detection units 12U to 12W only need to include at least one of a voltage detector and a current detector. That is, the power detection units 12U to 12W may detect at least one of the output voltage of the converter circuit 10 and the output current of the converter circuit 10 as information on the output power of the AC line. In the present embodiment, three-phase output power is detected, but at least two-phase output detection may be performed.

  The inverter INV includes a high potential input terminal 10a, a low potential input terminal 10b, and a plurality of legs LG1, LG2, LG3. The high potential input terminal 10 a is connected to the anode of the DC power supply 30. The low potential input terminal 10 b is connected to the cathode of the DC power supply 30. The inverter INV is electrically connected to the DC power supply 30 through the input terminals 10a and 10b. DC power supplied from the DC power supply 30 is input between the input terminals 10a and 10b.

In the present embodiment, the inverter INV includes three legs: a first leg LG1, a second leg LG2, and a third leg LG3.
The first leg LG1 includes two arms, a first upper arm UA1 and a first lower arm LA1. The first upper arm UA1 is connected to the high potential input terminal 10a. The first lower arm LA1 is connected between the first upper arm UA1 and the low potential input terminal 10b.

  The second leg LG2 includes two arms, a second upper arm UA2 and a second lower arm LA2. The second upper arm UA2 is connected to the high potential input terminal 10a. The second lower arm LA2 is connected between the second upper arm UA2 and the low potential input terminal 10b.

  The third leg LG3 includes two arms, a third upper arm UA3 and a third lower arm LA3. The third upper arm UA3 is connected to the high potential input terminal 10a. The third lower arm LA3 is connected between the third upper arm UA3 and the low potential input terminal 10b.

  Each of the first leg LG1, the second leg LG2, and the third leg LG3 is connected in parallel between the input terminals 10a and 10b (between DC lines). In each leg LG1, LG2, LG3, “upper side” and “lower side” do not mean an arrangement in the vertical direction. In each leg LG1, LG2, LG3, “upper side” means the higher potential side of the input DC power, and “lower” means the lower side of the input DC power potential. In other words, each upper arm UA1, UA2, UA3 is a high-potential side arm. In other words, each lower arm LA1, LA2, LA3 is an arm on the low potential side.

  In the present embodiment, the inverter INV is a so-called three-phase inverter having three legs and six arms. The inverter INV converts DC power into three-phase AC power. Therefore, the output power of the converter circuit 10 (or the output power of the inverter device) is three-phase AC power. The output power of the converter circuit 10 may be set according to the configuration of the motor 40.

  The first upper arm UA1 of the first leg LG1 includes a first upper switching element U1, a second upper switching element U2, and a third upper switching element U3. The first upper switching element U1 is connected between the input terminals 10a and 10b. The second upper switching element U2 is connected between the first upper switching element U1 and the high potential input terminal 10a. The third upper switching element U3 is connected between the second upper switching element U2 and the high potential input terminal 10a.

  The first lower arm LA1 of the first leg LG1 includes a first lower switching element X1, a second lower switching element X2, and a third lower switching element X3. The first lower switching element X1 is connected between the first upper switching element U1 and the low potential input terminal 10b. The second lower switching element X2 is connected between the first lower switching element X1 and the low potential input terminal 10b. The third lower switching element X3 is connected between the second lower switching element X2 and the low potential input terminal 10b.

  The first leg LG1 includes a first charge storage element CU1 and a second charge storage element CU2. One end of the first charge storage element CU1 is connected between the first upper switching element U1 and the second upper switching element U2. The other end of the first charge storage element CU1 is connected between the first lower switching element X1 and the second lower switching element X2. One end of the second charge storage element CU2 is connected between the second upper switching element U2 and the third upper switching element U3. The other end of the second charge storage element CU2 is connected between the second lower switching element X2 and the third lower switching element X3.

  The second upper arm UA2 of the second leg LG2 includes a first upper switching element V1, a second upper switching element V2, and a third upper switching element V3. The first upper switching element V1 is connected between the input terminals 10a and 10b. The second upper switching element V2 is connected between the first upper switching element V1 and the high potential input terminal 10a. The third upper switching element V3 is connected between the second upper switching element V2 and the high potential input terminal 10a.

  The second lower arm LA2 of the second leg LG2 includes a first lower switching element Y1, a second lower switching element Y2, and a third lower switching element Y3. The first lower switching element Y1 is connected between the first upper switching element V1 and the low potential input terminal 10b. The second lower switching element Y2 is connected between the first lower switching element Y1 and the low potential input terminal 10b. The third lower switching element Y3 is connected between the second lower switching element Y2 and the low potential input terminal 10b.

  The second leg LG2 includes a first charge storage element CV1 and a second charge storage element CV2. One end of the first charge storage element CV1 is connected between the first upper switching element V1 and the second upper switching element V2. The other end of the first charge storage element CV1 is connected between the first lower switching element Y1 and the second lower switching element Y2. One end of the second charge storage element CV2 is connected between the second upper switching element V2 and the third upper switching element V3. The other end of the second charge storage element CV2 is connected between the second lower switching element Y2 and the third lower switching element Y3.

  The third upper arm UA3 of the third leg LG3 includes a first upper switching element W1, a second upper switching element W2, and a third upper switching element W3. The first upper switching element W1 is connected between the input terminals 10a and 10b. The second upper switching element W2 is connected between the first upper switching element W1 and the high potential input terminal 10a. The third upper switching element W3 is connected between the second upper switching element W2 and the high potential input terminal 10a.

  The third lower arm LA3 of the third leg LG3 includes a first lower switching element Z1, a second lower switching element Z2, and a third lower switching element Z3. The first lower switching element Z1 is connected between the first upper switching element W1 and the low potential input terminal 10b. The second lower switching element Z2 is connected between the first lower switching element Z1 and the low potential input terminal 10b. The third lower switching element Z3 is connected between the second lower switching element Z2 and the low potential input terminal 10b.

  The third leg LG3 includes a first charge storage element CW1 and a second charge storage element CW2. One end of the first charge storage element CW1 is connected between the first upper switching element W1 and the second upper switching element W2. The other end of the first charge storage element CW1 is connected between the first lower switching element Z1 and the second lower switching element Z2. One end of the second charge storage element CW2 is connected between the second upper switching element W2 and the third upper switching element W3. The other end of the second charge storage element CW2 is connected between the second lower switching element Z2 and the third lower switching element Z3.

  For example, a capacitor is used for each of the first charge storage elements CU1, CV1, and CW1. Each of the first charge storage elements CU1, CV1, and CW1 is called a flying capacitor, for example. That is, the inverter INV is a so-called flying capacitor circuit type inverter.

  In the inverter INV, three switching elements are connected in series to each of the arms UA1, UA2, UA3, LA1, LA2, and LA3. The second charge storage element CU2 generates an intermediate voltage between the DC power supply 30 and the first charge storage element CU1. The first charge storage element CU1 generates a voltage intermediate between the second charge storage element CU2 and the reference potential. Similarly, the second charge storage element CV2 generates a voltage intermediate between the DC power supply 30 and the first charge storage element CV1. The first charge storage element CV1 generates a voltage intermediate between the second charge storage element CV2 and the reference potential. Similarly, the third charge storage element CW2 generates an intermediate voltage between the DC power supply 30 and the first charge storage element CW1. The first charge storage element CW1 generates a voltage intermediate between the second charge storage element CW2 and the reference potential. For this reason, the charge storage elements CU1, CU2, CV1, CV2, CW1, and CW2 may be referred to as intermediate capacitors.

Thereby, in the inverter INV, the level of the output voltage can be changed to 3 levels in each leg and 4 levels in total including the level of the reference potential. That is, the inverter INV is a multilevel inverter having four levels for each phase.
The number of switching elements provided in each of the arms UA1, UA2, UA3, LA1, LA2, and LA3 may be two, or four or more. The level of the voltage of each phase output from the inverter INV may be 3 levels or 5 levels or more.

  As described above, when the inverter INV that changes the output voltage level to 4 levels is used, when the switching frequency per element is constant, the frequency of the output voltage (equivalent carrier frequency) is 2 level output. Compared to, each phase is 3 times (number of levels minus 1).

  On the other hand, the value of the voltage error due to the dead time at each switching is reduced to 1/3 by increasing the number of levels, but since the equivalent carrier frequency is three times higher, the appearance frequency of the dead time is 3 Doubled. Therefore, the average voltage error due to dead time is not changed compared to the case of 2 levels. From this point of view, if the equivalent carrier frequency is lowered, the value of the dead time voltage error can be reduced. In other words, instead of increasing the number of levels, the switching frequency per element can be decreased and the average dead time voltage error itself can be reduced.

  The inverter INV includes each first upper switching element U1, V1, W1, each second upper switching element U2, V2, W2, each first lower switching element X1, Y1, Z1, and each second lower switching. It is only necessary to include at least the elements X2, Y2, and Z2 and the first charge storage elements CU1, CV1, and CW1. In the case where three or more switching elements are provided in each arm UA1, UA2, UA3, LA1, LA2, LA3, a plurality of charge storage elements are provided in the inverter. The number of charge storage elements is a value obtained by subtracting 1 from the number of switching elements of each arm UA1, UA2, UA3, LA1, LA2, LA3. One end of each charge storage element is connected to a connection point between two adjacent switching elements of the upper arm. The other end of each charge storage element is connected to a connection point between two adjacent switching elements of the lower arm.

  In the inverter INV, the connection point between the first upper arm UA1 and the first lower arm LA1, the connection point between the second upper arm UA2 and the second lower arm LA2, the third upper arm UA3 and the third lower side. A connection point with the arm LA3 is an AC output point. In other words, the connection point between the first upper switching element U1 and the first lower switching element X1, the connection point between the first upper switching element V1 and the first lower switching element Y1, and the first upper switching. A connection point between the element W1 and the first lower switching element Z1 is an AC output point.

  For example, self-extinguishing elements are used for the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3. More specifically, for example, GTO (Gate Turn-Off thyristor), IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor), etc. are used.

  Each of the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3 includes a pair of main electrodes and a control electrode that controls a current flowing between the main electrodes. . The control electrode is, for example, a gate electrode. Each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3 are connected in series in each main electrode.

  Each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3 changes to an ON state and an OFF state according to the voltage applied to a control electrode. Each of the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3 are turned on when, for example, the first voltage is applied to the control electrode. Each of the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, Z1 to Z3 is applied to the control electrode when a second voltage lower than the first voltage is applied to the control electrode. When no voltage is applied, it is turned off. The off state is a state in which substantially no current flows between the main electrodes. The off state may be, for example, a state in which a weak current that does not affect power conversion in the inverter flows between the main electrodes. In other words, the on state is a first state in which current flows between the main electrodes. The off state is a second state in which the current flowing between the main electrodes is lower than the first state. In this embodiment, each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3 is a normally-off type. In addition, normally-on type may be sufficient as each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3.

  Moreover, the diode is connected to each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3. Each diode is connected in parallel to each main electrode of each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3. In addition, the forward direction of each diode is set to be opposite to the direction of current flowing between the main electrodes. That is, each diode is a so-called free-wheeling diode. Each diode may be a parasitic diode.

  The converter circuit 10 may further include, for example, a noise cut filter or a transformer. The noise cut filter is provided, for example, between the DC power supply 30 and the inverter INV, and suppresses noise included in DC power supplied from the DC power supply 30. For example, the transformer is provided between the converter circuit 10 and the motor 40 and transforms AC power output from the converter circuit 10.

  The control circuit 20 is connected to each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3 of the inverter INV. More specifically, the control circuit 20 is connected to each control electrode of each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3. The control circuit 20 controls on / off of the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3. For example, the control circuit 20 inputs the control signal to the control electrodes of the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3, and changes the voltage of the control signal. Thus, the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3 are controlled on / off. The control signal is a so-called gate signal. Thereby, the control circuit 20 converts the DC power into AC power having a voltage and frequency corresponding to the motor unit.

  The control circuit 20 is a processor such as a CPU or MPU, for example. For example, the control circuit 20 reads out a predetermined program from the memory M and sequentially processes the program, thereby comprehensively controlling each unit of the inverter device. Specifically, the control circuit 20 controls the operation in which the inverter INV converts DC power to AC power. The memory M storing the program may be provided in the control circuit 20 or may be provided separately from the control circuit 20 and connected to the control circuit 20. The control circuit 20 is not limited to the above-described configuration, and the functions described below may be realized by hardware or software, and may be realized by a combination of hardware and software. It may be realized.

  The control circuit 20 includes an AC value detection unit 27, a dq conversion unit 21, a non-interference control unit 22, a current control unit 23d and 23q, a speed control unit 24, an inverse dq conversion unit 25, and a comparison unit 26. , A carrier generation unit 28, and a memory M.

  The AC value detection unit 27 is arranged in front of the dq conversion unit 21. The output value of the converter circuit 10 detected by the power detection units 12U to 12W is input to the AC value detection unit. For example, at least one of the output voltage of the converter circuit 10 detected by the voltage detector and the output current of the converter circuit 10 detected by the current detector is input to the AC value detector. The AC value detection unit detects the AC value of the detected output power of the converter circuit 10. The AC value detection unit acquires, for example, the maximum value of the frequency and amplitude of the output power of the converter circuit 10 as an AC value. The AC value of the output power of the main circuit unit (AC line) is the AC value of the output current of the converter circuit 10. Note that the AC value of the output power may be the AC value of the output voltage of the converter circuit 10.

  The dq conversion unit 21 is a vector conversion unit, and based on the AC value of the output current detected by the AC value detection unit, the three-phase output current of the converter circuit 10 is converted into a vector value of a d-axis current and a q-axis. Convert to current and treat as direct current. Usually, the active power is converted on the q axis. That is, the dq conversion unit 21 converts the output current into an effective component and an ineffective component, and calculates a DC conversion value.

The current control units 23d and 23q perform control for causing the d-axis current and the q-axis current obtained by the dq conversion unit 21 to follow a desired current value. The current control units 23d and 23q include, for example, a PI controller that takes the difference between the command values i _d ^* and i _q ^{* of} each axis current and the response value and performs PI control. The controlled object at this time is the inductance and resistance of each axis, and the controlled variable is the voltage of each axis. That is, the output of the PI controller is voltage dimension. The output value of the non-interference control unit 22 is added to or subtracted from the output values of the current control units 23d and 23q, and non-interference control for removing interference between dq axes is used.

The speed control unit 24 is used in the outer loop of the current control unit 23q, and inputs the difference between the speed command value ω _m ^* and the speed response value ω (d / dt · θ) to the PI controller to obtain the current command value. Generate. This control output becomes the q-axis current command value i _q ^* and is supplied to the current control unit 23q. The speed response value may be directly measured by a speed sensor or the like, or rotation angle information θ obtained from an encoder, a hall sensor, or the like may be differentiated.

The inverse dq conversion unit 25 is an inverse vector conversion unit, and converts the voltage command values generated by the current control units 23d and 23q into UVW three-phase AC voltage command values ν _u ^* , ν _v ^* , and ν _w ^* . Reverse conversion. That is, the output of the inverse dq conversion unit 25 becomes the voltage command values ν _u ^* , ν _v ^* , ν _w ^{* of the} three-phase inverter INV. The voltage command value converted into three phases may be called a modulated wave. In addition, the amplitude of the modulated wave may be referred to as a modulation rate.

The carrier generation unit 28 receives the voltage command values ν _u ^* , ν _v ^* , ν _w ^* , and, as will be described later, based on the modulation rate, the equivalent carrier frequency of the carrier signal is the same as the carrier frequency of the two-level circuit. It sets so that it may become a grade (for example, 10 kHz or more and 50 kHz or less). For example, when the frequency of the carrier signal of one switching element is constant, the carrier generation unit 28 sets a value obtained by dividing the equivalent carrier frequency by (number of levels−1) as the frequency of the carrier signal.

The comparison unit 26 receives the three-phase voltage command values ν _u ^* , ν _v ^* , ν _w ^* and the carrier signal output from the inverse dq conversion unit 25. The comparison unit 26 compares the voltage command values ν _u ^* , ν _v ^* , ν _w ^* of each phase with the carrier signal of each phase, and switches the switching elements U1 to U3, X1 to X3, and V1 of each phase. Control signals (gate signals) of V3, Y1 to Y3, W1 to W3, and Z1 to Z3 are output to the converter circuit 10.

FIG. 2 is a diagram for explaining an example of the operation of the control circuit of the inverter device according to the first embodiment.
The comparison unit 26 of the control circuit 20 includes the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 to W3, and Z1 to Z3 based on the carrier signals CS1 to CS3 and the modulated wave MW. A control signal for controlling an operation of turning on or off is generated.

  FIG. 2A shows an example of carrier signals CS1 to CS3 and a modulated wave MW used for controlling the switching elements U1 to U3 and X1 to X3 of the first leg LG1. The modulated wave MW is set for each leg LG1, LG2, LG3, and in this embodiment, three modulated waves MW are set.

  The carrier signal is in each leg LG1, LG2, LG3 for each upper switching element U1-U3, V1-V3, W1-W3, or for each lower switching element X1-X3, Y1-Y3, Z1-Z3. Is set. That is, in this embodiment, nine carrier signals are set. The carrier signals set in the switching elements U1 to U3 and X1 to X3 of the first leg LG1 are converted into the switching elements V1 to V3, Y1 to Y3 of the second leg LG2, and the switching elements W1 of the third leg LG3. -W3 and Z1-Z3 can also be used in common. Therefore, in the present embodiment, at least three types of carrier signals may be prepared.

  The carrier signal CS1 is an example of a carrier signal used for controlling the first upper switching element U1. The carrier signal CS2 is an example of a carrier signal used for controlling the second upper switching element U2. The carrier signal CS3 is an example of a carrier signal used for controlling the third upper switching element U3.

FIG. 2B is an example of a control signal for the first upper switching element U1 generated based on the modulated wave MW and the carrier signal CS1.
FIG. 2C is an example of a control signal for the second upper switching element U2 generated based on the modulated wave MW and the carrier signal CS2.
FIG. 2D is an example of a control signal for the third upper switching element U3 generated based on the modulated wave MW and the carrier signal CS3.

Modulated wave MW and carrier signals CS1 to CS3 change periodically. The modulation wave MW is, for example, a sine wave. The frequency of modulated wave MW is set according to the frequency of AC power output from converter circuit 10 and the speed command value ω _m ^* used in control circuit 20. The frequency of the modulation wave MW is variable from 0 Hz to 500 Hz, for example. Each of the carrier signals CS1 to CS3 is, for example, a triangular wave. The carrier signals CS1 to CS3 may be sawtooth waves or trapezoidal waves. The frequencies of the carrier signals CS1 to CS3 are higher than the frequency of the modulated wave MW. The frequency of each of the carrier signals CS1 to CS3 is, for example, about 0.5 kHz to 50 kHz. In the present embodiment, the frequencies of the carrier signals CS1 to CS3 are substantially the same.

  The carrier signals CS1 to CS3 are set with a phase shift of 120 degrees from each other. The phase of the carrier signal is set according to the number of carrier signals. For example, when each arm is a three-level inverter including two switching elements, two carrier signals are set, and the phase of each carrier signal is shifted by 180 degrees. For this reason, the modulation method of the inverter in this case may be called a carrier phase shift signal generation method.

  The comparison unit 26 of the control circuit 20 compares the modulated wave MW with the carrier signals CS1 to CS3. For example, when the modulated wave MW is equal to or higher than the carrier signals CS1 to CS3, the comparison unit 26 turns on the upper switching elements U1 to U3 and turns off the lower switching elements X1 to X3. In this case, the comparison unit 26 outputs a control signal that turns off the upper switching elements U1 to U3 and turns on the lower switching elements X1 to X3 when the modulated wave MW is less than the carrier signals CS1 to CS3. . As described above, the control circuit 20 alternately turns on and off the upper switching elements U1 to U3 and the lower switching elements X1 to X3. Conversely, the comparison unit 26 may output a control signal that turns off the upper switching elements U1 to U3 and turns on the lower switching elements X1 to X3 when the modulated wave MW is equal to or higher than the carrier signal CS. . At this time, a dead time is provided in order to avoid simultaneously turning on the upper and lower elements.

  The control circuit 20 controls each of the first leg LG1, the second leg LG2, and the third leg LG3 as described above. Thereby, the control circuit 20 controls on / off of each switching element U1-U3, X1-X3, V1-V3, Y1-Y3, W1-W3, Z1-Z3. That is, the conversion from DC power to AC power by the inverter INV is controlled.

FIG. 3A is a diagram schematically illustrating an example of the influence of the dead time of the switching element on the output of the inverter in the gate drive device according to the first embodiment.
In the upper part of FIG. 3A, an example of a theoretical waveform of the output voltage of the two-level inverter INV from the control circuit 20 is shown. In the interruption of FIG. 3B, an example of a modulated wave (sine wave) and a carrier signal (triangular wave) to be compared by the comparison unit 26 is shown. The lower part of FIG. 3A shows an example of the dead time of the switching element and the voltage error average value due to the dead time. Here, the case where the power factor is 1 and the voltage phase and the current phase are the same is shown.

For example, in the case of a two-level circuit, assuming that the switching frequency is constant fc and the dead time is Td, the dead time voltage error average value V ^err can be expressed by the following equation (1).
V ^err = 1 / Tc · (Videal−Vprac) · Td
= 2Edc · Td · fc · sgn (i) (1)
Here, V ^err represents an average dead time voltage error, Tc is a switching period, Video is an ideal output voltage, and Vprac is an actual output voltage. Edc indicates a half value of the DC voltage, and sgn is a sign function. In other words, the magnitude of the dead time voltage error is proportional to the DC voltage, dead time, and switching frequency, and its polarity is equal to the polarity of the output current. This dead time voltage error, the output torque is widely known that pulsates at six times the fundamental frequency f _0.

FIG. 3B is a diagram schematically illustrating another example of the influence of the dead time of the switching element on the output of the inverter in the gate drive device according to the first embodiment.
In the upper part of FIG. 3B, an example of a theoretical waveform of the output voltage of the multi-level inverter INV from the control circuit 20 is shown. In the interruption of FIG. 3B, an example of a modulated wave (sine wave) and a carrier signal (triangular wave) to be compared by the comparison unit 26 is shown. The lower part of FIG. 3B shows an example of the dead time of the switching element and the voltage error average value due to the dead time. Here, the case where the power factor is 1 and the voltage phase and the current phase are the same is shown.

  For example, in the case of a 4-level circuit, if the switching frequency per switching element is made constant as fc, the value of the dead time error per time becomes small in the case of a 4-level circuit, compared with the case of 2 levels. It can be seen that 1/3. However, the appearance frequency is tripled, and as a result, the average value of the dead time voltage error is not different from the equation (1).

On the other hand, in a phase shift carrier type multi-level circuit, if the switching frequency per element is fixed as fc, the equivalent carrier frequency feq per phase is fc for a 2-level circuit, 2fc for a 3-level circuit, and 4 levels. In the circuit, it becomes 3fc, and when the number of levels is m, it can be expressed as follows.
feq = (m−1) fc (2)
That is, assuming that the switching frequency per element is constant at fc and the number of levels is m, the equivalent carrier frequency feq is (m-1) times the switching frequency per element, and the equivalent carrier frequency increases. However, the average value of the dead time voltage error is not different from that of the two levels.

Substituting equation (2) into equation (1) yields equation (3).
V ^err = 2Edc · Td · feq / (m−1) · sgn (i) (3)
That is, it can be seen that if the switching frequency per element is not fc but the equivalent carrier frequency feq is constant and the number of levels m is increased, the dead time voltage error average value V ^err decreases.

  The equivalent carrier frequency feq means the switching frequency of the output voltage per phase and is a frequency that affects the controlled object. For this reason, the control amount can be changed only for the controlled object at the period of the equivalent carrier frequency. That is, it can be considered that a sample and hold equal to the equivalent carrier frequency is inserted, which is equivalent to the control sampling period.

That is, it can be seen from equation (3) that if the equivalent carrier frequency feq is lowered, the dead time voltage error average value V ^err can be reduced, but the control cycle becomes slow and control with good performance cannot be performed. Therefore, increasing the number of levels and keeping the equivalent carrier frequency feq constant is a useful means that makes it possible to keep the control performance constant while reducing the dead time voltage error average value V ^err .

  From the above, in the inverter device according to the present embodiment, the multilevel inverter INV is used, and the carrier signal used by the carrier generation unit 28 in the multilevel inverter INV is 2 when the equivalent carrier frequency obtains the same output. It is set to be approximately the same as the carrier frequency used in the level inverter INV (for example, 10 kHz to 50 kHz). Thus, it is possible to provide an inverter device that keeps the control performance constant while reducing the average dead time voltage error value of the inverter INV.

Further, in the inverter device of this embodiment, by setting the equivalent carrier frequency feq of the carrier to 10 kHz to 50 kHz which is about the same as the carrier frequency of the two-level circuit, the width of the current ripple by switching is the same as that of the two-level circuit. Is set to be Furthermore, by using a multi-level converter as the inverter INV, it is possible to reduce the dead time voltage error average value V ^err and reduce the torque ripple while keeping the loss (harmonic loss) at the same level. The principle will be described in detail below.

If the dq-axis inductance is L, the voltage is V, and the current is I, the following equation holds.
V = L · ΔI / Δt (4)
Here, Δt means a minute time, and ΔI means the magnitude of current ripple in that period. Further, in the m level circuit, the output voltage is 1 / (m−1) times when the maximum voltage appearing on the dq axis is Vmax, and therefore equation (5) is established.
V = Vmax / (m−1) (5)
Vmax is equal to a value obtained by multiplying a value Edc which is a half of the DC voltage by √3 / 2 which is a value considering norm conversion at the time of dq conversion. Since the minute switching time Δt given to the controlled object is an equivalent carrier period, the equation (4) is rewritten to the equation (6).
ΔI = V / L · Δt
= Vmax / (L.feq. (M-1)) (6)

That is, it can be seen that the magnitude of the current ripple is proportional to the equivalent carrier frequency feq and the inverse of the number of levels (m−1). Further, from the expression (2), the expression (6) becomes the expression (7).
ΔI = Vmax / (L · fc · (m−1) ² ) (7)
That is, when the switching frequency fc per element is constant, the current ripple magnitude ΔI is inversely proportional to the square of the number of levels (m−1). Therefore, if the current ripple of the two levels is 1, it is 1/4 for 3 levels and 1/9 for 4 levels. Here, the current ripple means a short-time ripple due to switching, and does not occur at a period of 6 times the fundamental wave.

Substituting equation (6) into equation (3) yields equation (8).
V ^err = 2Edc · Td · Vmax / (L · ΔI · (m−1) ² ) · sgn (i) (8)
That is, the dead time voltage error average value V ^err is inversely proportional to the square of the number of levels (m−1) and the current ripple ΔI. That is, if the number of levels (m−1) is increased while keeping the current ripple ΔI constant, the dead time voltage error average value V ^err decreases in inverse proportion to the square of the number of levels (m−1). I mean. Keeping the magnitude of the current ripple ΔI constant means keeping the loss at the same level, and the dead time voltage error average value V ^err can be reduced.

  Therefore, according to the inverter device of the present embodiment, it is possible to provide an inverter device that keeps the loss at the same level while reducing the average dead time voltage error. That is, according to the present embodiment, it is possible to provide an inverter device and a vehicle that suppresses torque ripple of the motor and improves driving efficiency.

Next, the inverter apparatus of 2nd Embodiment is demonstrated in detail with reference to drawings.
In the inverter device of the present embodiment, the equivalent carrier frequency of the carrier signal is the optimum equivalent carrier frequency that minimizes the distortion index. The principle will be described below.

In the above equation (3), when the number of levels m is constant, the dead time voltage error average value V ^err is proportional to the equivalent carrier frequency feq. That is, under the condition of a certain level, the dead time voltage error average value V ^err can be lowered as the equivalent carrier frequency feq is lowered, resulting in a current ripple of 6 times the fundamental wave that appears due to the influence of the dead time voltage error. The resulting torque ripple can be reduced.

  On the other hand, if the equivalent carrier frequency is lowered too much, the output voltage itself approaches a rectangular wave, and current ripple increases due to the influence. That is, there is a trade-off relationship between torque ripple caused by the average value of the dead time voltage error and torque ripple caused by current distortion caused by lowering the output voltage. In other words, it means that there is an equivalent carrier frequency that minimizes the sum of both spectra.

The output phase voltage harmonics of the carrier phase shift type multi-level circuit can be expressed by the following equation.

Here, Edc is a half value of the DC voltage, m is the number of levels, a is the modulation factor, ω ₀ is the fundamental wave angular frequency, ω _c is the carrier angular frequency per element, and J _k is the k-th order. A kind of Bessel function is shown. Note that λ = n (m−1) π / 2. From this equation, the spectrum of the n (m−1) fc ± kf ₀ component can be expressed by the following equation.
However, when n (m−1) is an odd number, k is an even number, and when n (m−1) is an even number, k is an odd number.

If the dq conversion is applied to the equation (9), the theoretical harmonic on the dq axis can be obtained. However, the dq conversion in this paper is defined by the following equation.

If dq conversion is applied to the equation (11), the following equation is obtained.

Therefore, the spectrum of the n (m−1) fc ± kf ₀ component on the dq axis can be expressed by the following equation.

However, when n (m−1) is an odd number, k = 6l−3 (l is a positive integer), and when n (m−1) is an even number, k = 6l (l is a positive integer). is there. A common mode of the k + 1 order Bessel function and the k−1 order Bessel function appears in the d-axis voltage, and a normal mode of the k + 1 order Bessel function and the k−1 order Bessel function appears in the q axis voltage. However, only when k = 0, the q-axis voltage can be expressed as follows.

The average dead time voltage error could be expressed by equation (3). Therefore, the following equation is obtained by applying the Fourier series expansion of a rectangular wave.

When dq conversion is applied to the equation (17), the following equation is obtained.

Here, Γ + k = 1 / (6k + 1) and Γ−k = 1 / (6k−1) are shown. Therefore, the spectrum of the 6 kf ₀ component can be expressed by the following equation.

Similar to equations (14) and (15), the Γ + k and Γ−k common modes appear on the d-axis, and the Γ + k and Γ−k normal modes appear on the q-axis, which is six times the fundamental wave. Recognize. However, only when k = 0, the q-axis voltage can be expressed as follows.

  That is, the q-axis voltage is offset due to the influence of dead time.

The output torque of the permanent magnet synchronous motor can be expressed by the following equation.

  Here, T is the output torque, ψa is the armature flux linkage, Ld is the d-axis inductance, and Lq is the q-axis inductance.

In particular, in the case of SPMSM, Ld = Lq is established, and the equation (23) can be rewritten as the equation (24).

Therefore, the torque ripple due to the distortion of the output voltage waveform can be expressed by the following equation using the spectrum of the n (m−1) fc ± kf ₀ component.

The torque ripple based on the spectrum of the 6 kf ₀ component can be expressed by the following equation.

In the above (26), while indicating the torque ripple caused by spectrum 6Kf ₀ components, the 6Kf _{0 component,} contains all of the frequency components of the 6f 0, _12f 0, multiples of 18f 0 _... 6. Therefore, the 6-fold pulsation includes all pulsations that occur at multiples of 6. Among 6-fold pulsations, the spectrum is the largest at (6 kf0), which is the main factor for generating torque ripple.

The equivalent carrier frequency at which the distortion index described below is minimized is a spectrum of n (m−1) fc ± kf ₀ of the harmonic Vq generated by 6 times pulsation (6 kf ₀ ) of the dead time voltage error V _q ^err and switching. It means the point where the sum of

  In the present embodiment, since calculation is performed by converting three-phase alternating current into two axes of dq, attention is paid to 6-fold pulsation. For example, motors such as four-phase, five-phase instead of three-phase are used. In the case of driving, attention is paid to pulsations generated at other multiple frequencies.

Thus, as an example of an index indicating the degree of distortion of the output voltage waveform, the distortion index PI can be defined by the following equation.

FIG. 4 is a diagram showing an example of the relationship between the equivalent carrier frequency and the distortion index in a two-level circuit for a plurality of modulation rates.
FIG. 5 is a diagram showing an example of the relationship between the equivalent carrier frequency and the distortion index in a three-level circuit for a plurality of modulation rates.
FIG. 6 is a diagram illustrating an example of the relationship between the equivalent carrier frequency and the distortion index in a four-level circuit for a plurality of modulation rates.

  4 to 6, the horizontal axis represents the equivalent carrier frequency, and the vertical axis represents the value of the distortion index PI. Here, the torque T in the equation (27) indicates a fundamental wave component. 4 to 6 show an approximate curve LA passing through the vicinity of the minimum value of each modulation factor curve.

  According to FIGS. 4 to 6, the 2-level circuit, the 3-level circuit, and the 4-level circuit all have an equivalent carrier frequency at which the distortion index PI is a minimum value, and the value varies depending on the modulation factor a. . For example, when the optimum value of the equivalent carrier frequency exceeds the frequency upper limit value of the carrier signal used for driving the motor, the optimum value of the equivalent carrier frequency may be the upper limit value.

  From the above, in the inverter device of the present embodiment, the control circuit 20 has a table in which the value of the equivalent carrier frequency at which the distortion index becomes a minimum value is stored for each modulation factor, and is read from this table. A carrier signal is generated in the carrier generation unit 28 using the equivalent carrier frequency. The table storing the equivalent carrier frequency for each modulation factor may be stored in advance in the memory M, for example, or read from the outside.

Hereinafter, an operation in which the control circuit 20 determines the equivalent carrier frequency will be described.
First, the carrier generation unit 28 sets the equivalent carrier frequency to an initial value (for example, 20 kHz) and starts control.

  Subsequently, the carrier generation unit 28 calculates the rotational speed and load torque of the motor 40 based on the magnetic pole position θ of the motor 40 and the output power of the inverter INV, and obtains the modulation rate from the rotational speed and load torque of the motor 40. . In this embodiment, since the command value to the motor 40 is known by the control circuit 20, the modulation rate can be obtained from the command value.

Subsequently, the carrier generation unit 28 accesses, for example, a table stored in the memory M, and reads out an equivalent carrier frequency corresponding to the obtained modulation rate.
The carrier generation unit 28 generates a carrier signal using the read value of the equivalent carrier frequency and outputs the carrier signal to the comparison unit 26. As a result, the inverter INV outputs a voltage having an equivalent carrier frequency that minimizes the distortion index.

  As described above, in the inverter device of the present embodiment, an equivalent carrier frequency that takes the minimum value of the distortion index with respect to the m-level multi-level inverter can be obtained based on the equation (27). As a result, torque ripple Can be reduced. That is, according to the present embodiment, it is possible to provide an inverter device and a vehicle that suppresses torque ripple of the motor and improves driving efficiency.

Next, the inverter apparatus of 3rd Embodiment is demonstrated in detail with reference to drawings.
Torque pulsations due to current increase in the low speed, low current region. This is due to the dead time of the converter (inverter) supplying power to the motor, and the time ratio of the dead time to the PWM pulse becomes large in the low-speed low-current region. . However, it is difficult to determine the polarity of the current in the low current region. Therefore, it is desired to realize a dead time compensation method that does not require determination of current polarity.

  To be precise, the switching element is not an ideal switch, and is turned on or off with a finite time during the dead time period, and it is necessary to consider the effects of the turn-off delay and turn-on delay.

  Therefore, in this embodiment, an observer is used. By using observers 29d and 29q, which will be described later, it is not necessary to determine the polarity of the current. Furthermore, since all the differences from the ideal model are compensated as disturbances, the effects of switching element turn-off delay and turn-on delay are also compensated. can do.

  Furthermore, the observers 29d and 29q can completely compensate the DC component. According to the equation (22), the dead time voltage error includes a direct current component. Therefore, the torque offset can be completely canceled by using the observers 29d and 29q.

  FIG. 7 is a block diagram schematically illustrating a configuration example of the inverter device according to the third embodiment. In FIG. 7, only the configuration necessary for the description is shown, and the description of other configurations is omitted. In the inverter device of the present embodiment, the control circuit 20 further includes observers 29d and 29q arranged in the subsequent stage of the current control units 23d and 23q and in the previous stage of the inverse dq conversion unit 25, respectively.

For example, the observers 29d and 29q use the value of the dead time voltage disturbance average value V ^err calculated by the equation (1) as an input value, and output a compensation value. The observers 29d and 29q can be equivalently regarded as a system in which a high-pass filter is added to the dead time voltage error. As a result, the attenuation rate of the dead time voltage error for a specific frequency can be calculated, and the operation can be performed at the optimum point for reducing the dead time voltage disturbance. The strain index PI when the observer 29 is used together can be expressed by the following equation.

  In this embodiment, by using the observers 29d and 29q, it is possible to effectively reduce pulsations having a period six times that of the fundamental wave generated by the dead time voltage error. Therefore, the optimum equivalent carrier frequency feq is higher than that in the case where the observer 29 is not used.

FIG. 8 is a diagram illustrating an example of a relationship between an equivalent carrier frequency and a distortion index in a two-level circuit when using an observer for a plurality of modulation rates.
FIG. 9 is a diagram illustrating an example of a relationship between an equivalent carrier frequency and a distortion index in a three-level circuit when using an observer for a plurality of modulation rates.
FIG. 10 is a diagram illustrating an example of a relationship between an equivalent carrier frequency and a distortion index in a four-level circuit when using an observer for a plurality of modulation rates.

  8 to 10, the horizontal axis represents the equivalent carrier frequency, and the vertical axis represents the value of the distortion index PI. Here, the torque T in the equation (28) indicates a fundamental wave component. 8 to 10 show an approximate curve LA passing through the vicinity of the minimum value of each modulation factor curve. In FIG. 9, there is a minimum value of the distortion index in a region where the equivalent carrier frequency is higher than 50 kHz.

  According to FIGS. 8 to 10, when the observers 29d and 29q are used, the optimum equivalent carrier frequency feq at which the distortion index PI becomes a minimum value is greater than when the observers 29d and 29q shown in FIGS. 4 to 6 are not used. Even higher. Therefore, in the present embodiment, for example, the table stored in the memory M stores the value of the optimum equivalent carrier frequency feq with respect to the modulation rate when the observers 29d and 29q are used. For example, when the optimum value of the equivalent carrier frequency exceeds the frequency upper limit value of the carrier signal used for driving the motor, the optimum value of the equivalent carrier frequency may be the upper limit value.

  In the inverter device of this embodiment, as in the second embodiment described above, the control circuit 20 has a table in which the value of the equivalent carrier frequency at which the distortion index is a minimum value is stored in advance for each modulation factor. The carrier generation unit 28 generates a carrier signal using the equivalent carrier frequency read from the table.

FIG. 11 is a flowchart for explaining an example of an operation for generating a carrier signal in the inverter device of this embodiment.
Hereinafter, an example of the operation in which the carrier generation unit 28 of the control circuit 20 determines the equivalent carrier frequency in the present embodiment will be described.

First, the carrier generation unit 28 sets the equivalent carrier frequency to an initial value (for example, 20 kHz) and starts control. (Step SA1)
Subsequently, the carrier generation unit 28 calculates the motor rotation speed and the load torque based on the magnetic pole position θ of the motor 40 and the output power of the inverter INV, and obtains the modulation rate from the motor rotation speed and the load torque. (Step SA2) In the present embodiment, the voltage command values ν _u ^* , ν _v ^* , and ν _w ^* calculated by the inverse dq conversion unit 25 of the control circuit 20 are used as the modulation factor. . As described above, the carrier generation unit 28 obtains the modulation rate.

  Subsequently, the carrier generation unit 28 determines whether or not the observers 29d and 29q are included. (Step SA3) Whether or not the observers 29d and 29q are provided may be determined based on values set in advance in a table or the like, depending on whether or not the control using the observers 29d and 29q is performed. This can be determined by a flag for setting the value. The value of this flag may be recorded in the memory or supplied from the outside.

If the observers 29d and 29q are not provided, the table storing the values when the observers 29d and 29q are not provided is accessed in the same manner as in the second embodiment, and the obtained modulation rate is supported. The equivalent carrier frequency is read out. (Step SA4)
Subsequently, the carrier generation unit 28 generates a carrier signal having the read equivalent carrier frequency and outputs the carrier signal to the comparison unit 26. As a result, the inverter INV outputs a voltage having an equivalent carrier frequency at which the distortion index is minimized. (Step SA5)

When the observers 29d and 29q are provided, the carrier generation unit 28 accesses the table storing the values when the observers 29d and 29q are provided, and calculates the equivalent carrier frequency corresponding to the obtained modulation rate. Is read. (Step SA6)
The carrier generation unit 28 generates a carrier signal using the read value of the equivalent carrier frequency and outputs the carrier signal to the comparison unit 26. As a result, the inverter INV outputs a voltage having an equivalent carrier frequency at which the distortion index is minimized. (Step SA7)

  As described above, by selecting a distortion index table based on the presence or absence of the observers 29d and 29q, an equivalent carrier frequency at which the distortion index is minimized can be obtained. As a result, torque ripple of the motor 40 can be suppressed and the driving efficiency of the motor can be improved.

Further, according to the above equation (28), if the observer gain g is a value that varies in proportion to the electrical angle fundamental frequency ω ₀ , the fundamental frequency f ₀ is proportional to the electrical angle frequency ω ₀ (f ₀ = ω _0). / 2π) relationship, the fundamental frequency f ₀ of the distortion index PI is canceled, and the distortion index PI becomes a value independent of the fundamental frequency f ₀ (or the electrical angular frequency ω ₀₎ . Therefore, in the present embodiment, the observer 29 sets the observer gain g to a function hω ₀ proportional to the electrical angle fundamental frequency ω ₀ or to a function hf ₀ proportional to the fundamental frequency f ₀ , and the electrical angle fundamental frequency ω _0, Alternatively, and sequentially updates the value of the gain g in accordance with the value of the fundamental frequency f _0. As described above, when the observer gain g is the function hω ₀ proportional to the electrical angle fundamental frequency ω ₀ or the function hf ₀ proportional to the fundamental frequency f ₀ , the speed dependence of the torque ripple (due to 6 times pulsation) is avoided. be able to.

FIG. 12 is a flowchart for explaining another example of the operation of generating the carrier signal in the inverter device of the third embodiment.
First, the carrier generation unit 28 sets the equivalent carrier frequency to an initial value (for example, 20 kHz) and starts control. (Step SB1)
Subsequently, the observers 29d and 29q calculate the value of the observer gain g based on the value of the electrical angle fundamental frequency ω ₀ and update the value of the observer gain g. (Step SB2)

Subsequently, the carrier generation unit 28 calculates the motor rotation speed and the load torque based on the magnetic pole position θ of the motor 40 and the output power of the inverter INV, and obtains the modulation rate from the motor rotation speed and the load torque. (Step SB3) In this embodiment, the amplitude of the sine wave of the voltage command values ν _u ^* , ν _v ^* , ν _w ^* calculated by the inverse dq conversion unit 25 of the control circuit 20 is used as the modulation factor. As described above, the carrier generation unit 28 obtains the modulation rate.

Subsequently, the carrier generation unit 28 accesses a table storing values when the observer 29 is provided, and reads an equivalent carrier frequency corresponding to the obtained modulation rate. (Step SB4)
The carrier generation unit 28 generates a carrier signal using the read value of the equivalent carrier frequency and outputs the carrier signal to the comparison unit 26. As a result, the inverter INV outputs a voltage having an equivalent carrier frequency at which the distortion index is minimized. (Step SB5)
As described above, by selecting a distortion index table based on the presence or absence of the observer 29, an equivalent carrier frequency at which the distortion index is minimized can be obtained. As a result, torque ripple of the motor 40 can be suppressed and the driving efficiency of the motor can be improved.

  As described above, according to the inverter device of the present embodiment, the dead time voltage average error value reduced by the multilevel circuit can be used in combination with the observer, and the dead time voltage average error value can be further reduced. As a result, the torque ripple of the motor 40 can be suppressed and the driving efficiency of the motor can be improved. That is, according to the present embodiment, it is possible to provide an inverter device and a vehicle that suppresses torque ripple of the motor and improves driving efficiency.

Next, modified examples of the above-described plurality of embodiments will be described.
In the above embodiments, it has been described that the average dead time voltage error value can be reduced when the motor 40 is driven by a multi-level circuit. In addition, since the dead time voltage error average value can theoretically be calculated by the equation (3), it can be compensated by feedforward. In this case, the control circuit 20 further includes a feedforward compensation unit (not shown). The feedforward compensation unit determines the polarity of the output current of the motor 40 and compensates for the control signal output to the inverter INV using equation (3).

  In addition, in the region where the output current of the motor 40 is low, it is difficult to determine the current polarity, and if compensation is performed with a rectangular wave as shown in equation (3), the direction of compensation is reversed, which in turn has an adverse effect. Sometimes. For this reason, a method of compensating for a slightly smooth waveform from equation (3) may be used.

  By combining the feedforward type dead time compensation with the above-described embodiments as described above, the average value of dead time voltage errors reduced by the multilevel circuit can be further reduced.

  Further, the voltages Vcu1, Vcu2, Vcv1, Vcv2, Vcw1, and Vcw2 of the charge storage elements CU1, CU2, CV1, CV2, CW1, and CW2 are motor conditions and switching elements U1 to U3, X1 to X3, V1 to V3, and Y1. ~ Y3, W1 to W3, change depending on the state of Z1 to Z3.

  In this example, the control circuit 20 controls the voltage Vcu1, Vcu2, Vcv1, Vcv2, Vcw1, and Vcw2 based on the detection results of the voltage detection units 51U, 51V, 52U, 52V, 53U, and 53V. (Not shown). The capacitor voltage control unit, for example, switches each of the switching elements U1 to U3, X1 to X3, V1 to V3, Y1 to Y3, W1 so that the voltages Vcu1, Vcu2, Vcv1, Vcv2, Vcv1 and Vcv2 are substantially constant. Controls on and off operations of .about.W3 and Z1 to Z3.

  The voltage control method of each voltage Vcu1, Vcu2, Vcv1, Vcv2 of each charge storage element CU1, CU2, CV1, CV2, CW1, CW2 is described in, for example, “IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL.59, NO. 2, FEBRUARY 2012 Active Capacitor Voltage Balancing in Single-Phase Flying-Capacitor Multilevel Power Converters.

  Thereby, for example, fluctuations in the voltages Vcu1, Vcu2, Vcv1, Vcv2, Vcw1, and Vcw2 can be suppressed, and for example, the operation of the inverter INV can be further stabilized.

  In addition, without controlling each voltage Vcu1, Vcu2, Vcv1, Vcv2, Vcw1, Vcw2 of each charge storage element CU1, CU2, CV1, CV2, CW1, CW2, for example, each voltage detection unit 51U, 51V, 52U, Resistance elements may be connected in parallel to the charge storage elements CU1, CU2, CV1, CV2, CW1, and CW2, such as 5V, 53U, and 53V. Thereby, for example, fluctuations in the voltages Vcu1, Vcu2, Vcv1, Vcv2, Vcv1, and Vcw2 of the charge storage elements CU1, CU2, CV1, CV2, CW1, and CW2 can be suppressed as compared with the case where no resistance element is provided. The voltages Vcu1, Vcu2, Vcv1, Vcv2, Vcw1, and Vcw2 can be stabilized.

  According to the embodiments described above, it is possible to provide an inverter device that suppresses torque ripple of the motor 40 and improves the operating efficiency of the motor.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, each configuration of the converter circuit 10 and the control circuit 20 included in the inverter device, a high potential input terminal, a low potential input terminal, a leg, a first upper switching element, a second upper switching element, and a first lower switching element , Second lower switching element, charge storage element, power detection unit, AC value detection unit, dq conversion unit, non-interference control unit, speed control unit, current control unit, inverse dq conversion unit, comparison unit, etc. With respect to the specific configuration, the above-described embodiment can be implemented in the same manner by appropriately selecting from a range that can be implemented by those skilled in the art, and is included in the scope of the invention as long as the same effect can be obtained. .

Moreover, you may combine any two or more elements of the said some embodiment in the technically possible range. In addition, all configurations that can be implemented by those skilled in the art based on the inverter device described above as an embodiment of the invention are included in the scope of the invention as long as they include the gist of the present invention. .
In addition, in the category of the idea of the invention, those skilled in the art can conceive various modifications and modifications, and these modifications and modifications are also within the scope of the invention.

  DESCRIPTION OF SYMBOLS 10 ... Converter circuit, 10a ... High potential input terminal, 10b ... Low potential input terminal, 12U-12W ... Electric power detection part, 20 ... Control circuit, 21 ... dq conversion part, 22 ... Non-interference control part, 23d ... Current control , 23q ... current control unit, 24 ... speed control unit, 25 ... inverse dq conversion unit, 26 ... comparison unit, 27 ... AC value detection unit, 28 ... carrier generation unit, 29 ... observer, 30 ... DC power source (DC load) 40 ... motor (AC load), CS1-CS3 ... carrier signal, LG1 ... first leg, LG2 ... second leg, LG3 ... third leg, U1-U3, X1-X3, V1-V3, Y1-Y3 , W1 to W3, Z1 to Z3... Switching elements, CU1, CU2, CV1, CV2, CW1, CW2.

Claims (5)

A plurality of upper switching elements connected in series; and a plurality of lower switching elements connected in series; a leg in which the plurality of upper switching elements and the plurality of lower switching elements are connected in series; A power detector that detects output power supplied from the connection between the upper switching element and the plurality of lower switching elements to the AC load, and a converter circuit,
A table having a plurality of equivalent carrier frequencies set corresponding to the amplitude of the voltage command and an amplitude of the voltage command based on the current command input from the outside, and an equivalent corresponding to the amplitude of the voltage command from the table A control including: a carrier generation unit that reads a carrier frequency and generates a carrier signal using the equivalent carrier frequency; and a comparison unit that PWM modulates the voltage command using the carrier signal and outputs the PWM signal to each switching element. An inverter device comprising: a circuit;   The inverter apparatus according to claim 1, wherein the table stores an equivalent carrier frequency of the carrier signal at which a distortion index is a minimum value for each amplitude of the voltage command. The control circuit includes a vector conversion unit that converts the output power of the converter circuit detected by the power detection unit into a vector value, and a vector value calculated by the vector conversion unit follows the current command. A current control unit that generates the voltage command; an observer that compensates the voltage command based on a value of a voltage error caused by a dead time of the switching element; and an inverse vector that converts the compensated voltage command into each phase voltage A conversion unit;
The inverter device according to claim 1, wherein the table stores, for each amplitude of the voltage command, an equivalent carrier frequency of the carrier signal at which a distortion index becomes a minimum value when the observer is used. .   4. The inverter apparatus according to claim 3, wherein the observer gain of the observer is set to an electrical angle fundamental frequency or a value proportional to the fundamental frequency. An inverter device according to any one of claims 1 to 4,
A motor as the AC load that operates with AC power supplied from the converter circuit;
DC power to supply DC power to the converter circuit, and to charge electrical energy generated by the motor via the converter circuit;
A vehicle comprising: an axle driven by the power of the motor.