JP2013021895A - Inverter device and system interconnection inverter system equipped with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter device for reducing the number of switching times of a switching element and controlling intermediate potential in a multilevel inverter circuit.SOLUTION: The inverter device includes a multilevel inverter circuit and a control circuit. The control circuit generates a PWM signal on the basis of a first command value signal obtained by combining a first signal and a second signal, a second command value signal obtained by combining a signal whose phase is delayed from the first signal by 2π/3 and a signal whose phase is delayed from the second signal by 2π/3, and a third command value signal obtained by combining a signal whose phase is delayed from the first signal by 4π/3 and a signal whose phase is delayed from the second signal by 4π/3. Amplitude of a change in the intermediate potential in the multilevel inverter circuit and central potential change depending on a combination of the first signal and the second signal.

Description

  The present invention relates to an inverter device and a grid-connected inverter system including the inverter device, and particularly relates to a case where a multilevel inverter is employed.

  In recent years, distributed power sources using natural energy such as sunlight have been in widespread use. A grid-connected inverter system has been developed that includes an inverter device that converts DC power generated by this distributed power source into AC power, and supplies the converted AC power to a connected load or power system.

  FIG. 28 is a block diagram for explaining a general grid-connected inverter system A ′ for supplying power to a three-phase power system B (hereinafter abbreviated as “system B”). FIG. 29 is a circuit diagram showing an example of the internal configuration of the inverter circuit 200.

  The grid interconnection inverter system A ′ includes a DC power supply 100, an inverter circuit 200, a filter circuit 300, a transformer circuit 400, and a control circuit 500. The inverter circuit 200 is a three-phase bridge inverter, and converts the DC voltage input from the DC power supply 100 into an AC voltage by switching between the ON state and the OFF state of the switching elements SW1 to SW6 (see FIG. 29). Is. The control circuit 500 generates a PWM signal for controlling the inverter circuit 200 based on signals input from various sensors. The inverter circuit 200 switches the switching element on and off based on the PWM signal input from the control circuit 500. The filter circuit 300 removes high-frequency components due to switching from the AC voltage input from the inverter circuit 200. The transformer circuit 400 boosts or steps down the AC voltage input from the filter circuit 300 to substantially the same level as the system voltage of the system B.

  As shown in FIG. 29, each phase (U phase, V phase, W phase) arm of the inverter circuit 200 has two switching elements connected in series (for example, switching elements SW1 and SW4 in the case of the U phase arm). And two diodes connected in antiparallel to each switching element. Output lines are connected to the connection points of the two switching elements of each phase, and the output lines of each phase are connected to the filter circuit 300.

  When the potential of the negative electrode of the DC power supply 100 is “0” and the potential of the positive electrode is “E”, the voltage of the output line of each phase of the inverter circuit 200 (hereinafter referred to as “output phase voltage”) is “0”. Alternatively, it becomes a two-level potential of “E”. Therefore, the inverter circuit 200 is generally called a two-level inverter circuit. The voltage applied to each of the switching elements SW1 to SW6 of the inverter circuit 200 is “E”.

  In recent years, multilevel inverter circuits have been developed in which the output phase voltage is a potential of 3 levels or more. For example, the output phase voltage is one of three potentials: “0” which is the negative potential of the DC power supply 100, “E” which is the positive potential, and “(1/2) E” which is an intermediate potential. The three-level inverter circuit has been developed as the most practical multi-level inverter.

  FIG. 30 is a circuit diagram for explaining an example of the internal configuration of the three-level inverter circuit.

  The inverter circuit 201 is a three-level inverter circuit, and is configured so that the output phase voltage can be “(1/2) E” that is an intermediate potential between “0” and “E”. Thus, it is different from the inverter circuit 200 shown in FIG. As shown in FIG. 30, in the inverter circuit 201, two capacitors connected in series are connected in parallel between a point P connected to the positive electrode of the DC power supply 100 and a point N connected to the negative electrode. Since the two capacitors have the same capacitance, the potential at the connection point O is an intermediate potential “(1/2” between the negative electrode potential “0” and the positive electrode potential “E” of the DC power supply 100. ) E ". The output line of each phase is connected to point O via two switching elements (for example, switching elements SW7 and SW8 in the case of a U-phase arm). The two switching elements are turned on and off at the same time so that the connection between the point O and the output line is conducted when the switch is on, and the connection is not conducted when the switch is off.

  The output phase voltage of each phase of the inverter circuit 201 becomes a three-level potential depending on the state of the switching element. For example, in the U phase, when the switching element SW1 is on and the switching elements SW4, SW7, and SW8 are off, the output phase voltage is “E”, and the switching element SW4 is on and the switching elements SW1, SW7, and SW8 are on. Is in the off state, the output phase voltage is “0”, and when the SW7 and SW8 are in the on state and the switching elements SW1 and SW4 are in the off state, the output phase voltage is “(1/2) E”.

  In the inverter circuit 201, the voltage applied to each of the switching elements SW1 to SW6 is “(1/2) E”. Therefore, compared to the inverter circuit 200, power loss (hereinafter referred to as “switching loss”) during switching of the switching elements SW1 to SW6 can be reduced. Further, since the amplitude of the switching frequency component removed by the filter circuit 300 is also halved, the filter capacity of the filter circuit 300 can be reduced. Therefore, power loss due to the filter circuit 300 can also be reduced. Furthermore, a device with a low breakdown voltage can be used as each of the switching elements SW1 to SW6.

JP 2009-27818 A JP 2010-68630 A JP 2010-136547 A

  However, since the inverter circuit 201 uses more switching elements than the inverter circuit 200, switching loss due to the added switching elements becomes a problem. For example, in the U phase, while one of the switching element SW1 and the switching element SW4 is turned on and off, the other is fixed to be off. Accordingly, when only the switching element SW1 and the switching element SW4 are viewed, the number of times of switching is halved, so that the switching loss is reduced. However, since the added switching element SW7 and switching element SW8 are always on / off (compared with the inverter circuit 200), switching loss occurs between the switching element SW7 and the switching element SW8. Therefore, the switching loss in the entire switching element increases.

  In addition, the potential at the point O may change from an intermediate potential “(1/2) E” between the positive electrode side and the negative electrode side of the DC power supply 100. That is, when the switching element connected to the point O is in the on state, a current flows between the point O and the system B, so that the potential at the point O may change transiently. In some cases, the potential at the point O may be significantly decreased (or increased). If the potential at the point O changes greatly, the waveform of the output phase voltage may be disturbed, making it impossible to perform appropriate control. There is also a demand for controlling the potential at the point O to an arbitrary potential.

  The present invention has been conceived under the circumstances described above, and is an inverter device capable of reducing the number of switching times of a switching element and controlling an intermediate potential in a multilevel inverter circuit. The purpose is to provide.

  In order to solve the above problems, the present invention takes the following technical means.

  An inverter device provided by the first aspect of the present invention includes a multi-level inverter circuit, a waveform of an AC phase voltage output from the multi-level inverter circuit, a combination of the first waveform and the second waveform, A control circuit that generates a PWM signal and inputs the PWM signal to the multi-level inverter circuit, wherein the first waveform has a predetermined lower limit voltage value in a period of 1/3. In the subsequent 1/3 period, the waveform of the sine wave having a phase of 0 to 2π / 3 is shifted upward by the predetermined lower limit voltage value, and the phase is π in the remaining 1/3 period. A waveform obtained by shifting the waveform of a sine wave in the interval from / 3 to π upward by the predetermined lower limit voltage value, and the second waveform has a predetermined upper limit in a period of 1/3. It is a voltage value. Is a waveform obtained by shifting the waveform of the sine wave in the interval from π to 5π / 3 upward by the predetermined upper limit voltage value, and the sine wave in the interval from 4π / 3 to 2π in the remaining 1/3 period. This waveform is a waveform obtained by shifting upward the waveform by the predetermined upper limit voltage value. “Shifting upward by a predetermined lower limit voltage value” means shifting downward by an absolute value of the predetermined lower limit voltage value when the predetermined lower limit voltage value is a negative value.

  In a preferred embodiment of the present invention, the control circuit includes a first command value signal obtained by combining the first signal and the second signal, and a phase of 2π / 3 with respect to the first signal. A second command value signal obtained by combining a delayed signal and a signal delayed in phase by 2π / 3 with respect to the second signal, and a signal delayed in phase by 4π / 3 relative to the first signal. And command value signal generating means for generating a third command value signal that combines a signal delayed in phase by 4π / 3 with respect to the second signal, and a PWM signal based on each command value signal PWM signal generation means for generating, wherein the first signal has a predetermined lower limit value in a period of 1/3, and a phase of 0 to 2π in the subsequent period of 1/3. A waveform obtained by shifting the waveform of the sine wave in the section of / 3 upward by the predetermined lower limit value. There is a waveform obtained by shifting the waveform of the sine wave in the interval of π / 3 to π upward by the predetermined lower limit value in the remaining 1/3 period, and the second signal has one cycle The waveform is a predetermined upper limit value in a period of 1/3, and a waveform obtained by shifting a sine wave waveform having a phase of π to 5π / 3 in the subsequent period of 1/3 upward by the predetermined upper limit value. In the remaining 1/3 period, the waveform of the sine wave having a phase of 4π / 3 to 2π is shifted upward by the predetermined upper limit value. Note that “shifting upward by a predetermined lower limit value” means shifting downward by an absolute value of the predetermined lower limit value when the predetermined lower limit value is a negative value.

  In a preferred embodiment of the present invention, the command value signal generating means generates a flag signal that repeats a high level and a low level at a predetermined cycle, and the first signal and the first signal are generated based on the flag signal. The first command value signal is generated by switching between two signals.

In a preferred embodiment of the present invention, the command value signal generation means generates three phase voltage command value signals generated to command the waveforms of the three-phase AC phase voltages output from the multilevel inverter circuit. The first to third command value signals are generated by the following method using the three line voltage command value signals, which are the difference signals, and the flag signal.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B1) When the flag signal is at a low level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, the first command value signal Xu1 is set to Xuv. The second command value signal Xv1 is set to “0”, and the third command value signal Xw1 is set to a negative value of Xvw.
(C1) When the flag signal is at a low level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, Xu1 is set to “0” and Xv1 is set to Xuv Let it be a negative value, and let Xw1 be Xwu.
(D1) When the flag signal is at a low level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, Xu1 is set to a negative value of Xwu, and Xv1 is set to Xvw Xw1 is set to “0”.
(E1) When the flag signal is at a low level and the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu1 is set to Xuv and Xv1 is set to “0”. , Xw1 is a negative value of Xvw.
(F1) When the flag signal is at a low level and the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu1 is set to “0” and Xv1 is set to Xuv Let it be a negative value, and let Xw1 be Xwu.
(G1) When the flag signal is at a low level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu1 is set to a negative value of Xwu, and Xv1 is set to Xvw Xw1 is set to “0”.
(B2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, Xu1 is set to a predetermined value, and Xv1 is set to the predetermined value Xuv is subtracted from Xuv, and Xw1 is the value obtained by adding Xwu to the predetermined value.
(C2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, a value obtained by adding Xuv to the predetermined value and Xuv Xv1 is the predetermined value, and Xw1 is a value obtained by subtracting Xvw from the predetermined value.
(D2) When the flag signal is at a high level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, a value obtained by adding Xuv to the predetermined value and Xuv Xv1 is the predetermined value, and Xw1 is a value obtained by subtracting Xvw from the predetermined value.
(E2) When the flag signal is at a high level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu1 is a value obtained by subtracting Xwu from the predetermined value Xv1 is a value obtained by adding Xvw to the predetermined value, and Xw1 is the predetermined value.
(F2) When the flag signal is at a high level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu1 is obtained by subtracting Xwu from the predetermined value Xv1 is a value obtained by adding Xvw to the predetermined value, and Xw1 is the predetermined value.
(G2) When the flag signal is at a high level, the absolute value of Xwu is larger than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu1 is set as the predetermined value, and Xv1 is set as the predetermined value. Xuv is subtracted from the value, and Xw1 is the value obtained by adding Xwu to the predetermined value.

  In a preferred embodiment of the present invention, the command value signal generating means sets a cycle setting unit that sets a cycle of the flag signal and a duty ratio that is a ratio of a high level period to the cycle of the flag signal. A duty ratio setting unit.

  In a preferred embodiment of the present invention, the command value signal generating means further includes duty ratio changing means for changing the duty ratio set by the duty ratio setting unit.

  In a preferred embodiment of the present invention, the multilevel inverter circuit is a three-level inverter circuit.

  In a preferred embodiment of the present invention, the PWM signal generation means includes a first carrier signal that fluctuates between an intermediate value between the predetermined upper limit value and the predetermined lower limit value and the predetermined upper limit value. First carrier signal generating means for generating a second carrier signal generating means for generating a second carrier signal that fluctuates between the intermediate value and the predetermined lower limit value, and each command value signal, A first pulse generating means for generating a first pulse signal by comparing with the first carrier signal; and a second pulse signal by comparing each command value signal with the second carrier signal. Second pulse generating means for generating, and third pulse generating means for generating a third pulse signal based on a negative OR of the first pulse signal and the second pulse signal. , The first pulse signal, the second pulse, Scan signals, and a third pulse signal output as a PWM signal.

  In a preferred embodiment of the present invention, the first carrier signal and the second carrier signal have the same frequency.

  In a preferred embodiment of the present invention, the multi-level inverter circuit is configured such that the voltage of each phase has a negative electrode side potential, a positive electrode side potential of the DC power supply, and an intermediate between the negative electrode side potential and the positive electrode side potential. It is comprised so that it may become this electric potential.

  In a preferred embodiment of the present invention, the power supply for supplying power to the multilevel inverter circuit includes a solar cell.

  The grid interconnection inverter system provided by the second aspect of the present invention includes the inverter device provided by the first aspect of the present invention.

  According to the present invention, the PWM signal generated by the control circuit is input to the multilevel inverter circuit. The PWM signal is a waveform obtained by combining the waveform of the AC phase voltage output from the multilevel inverter circuit with the first waveform and the second waveform. The first waveform is a waveform that is fixed to a predetermined lower limit voltage value in a period of 1/3 of one cycle, and the second waveform is fixed to a predetermined upper limit voltage value in a period of 1/3 of one cycle. It is a waveform. Therefore, the PWM signal continues at a low level or a high level for a predetermined period. While the PWM signal continues at the low level or the high level, the switching means to which the PWM signal is input does not perform switching. Thereby, the frequency | count of switching of the said switching means can be reduced, and a switching loss can be reduced.

  Since there is a period during which the negative-side switching element continues to be on while the AC phase voltage waveform is the first waveform, the intermediate potential of the multilevel inverter circuit drops. On the other hand, since there is a period during which the positive-side switching element continues to be on while the waveform of the AC phase voltage is the second waveform, the intermediate potential of the multilevel inverter circuit rises. Therefore, by adjusting the combination of the first waveform and the second waveform, the intermediate potential of the multilevel inverter circuit can be controlled to a desired potential.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a block diagram for demonstrating the grid connection inverter system which concerns on 1st Embodiment. It is a circuit diagram for demonstrating the internal structure of the inverter circuit which concerns on 1st Embodiment. It is a block diagram for demonstrating the internal structure of the control circuit which concerns on 1st Embodiment. It is a figure for demonstrating the phase voltage signal and line voltage signal of each phase of a three-phase alternating current of a three-phase equilibrium state by a vector. It is a figure for demonstrating the view of the production | generation of a 1st signal with a vector. It is a figure for demonstrating the waveform of a 1st signal. It is a figure for demonstrating the concept of the production | generation of a 2nd signal with a vector. It is a figure for demonstrating the waveform of a 2nd signal. It is a block diagram for demonstrating the internal structure of the command value signal generation part which concerns on 1st Embodiment. It is a figure for demonstrating the waveform of a command value signal. It is a flowchart for demonstrating command value signal generation processing. It is a figure for demonstrating the method to produce | generate a PWM signal from a command value signal and a carrier signal. It is a block diagram for demonstrating the internal structure of the PWM signal generation part which concerns on 1st Embodiment. It is a figure for demonstrating the method to produce | generate the PWM signal of an intermediate | middle side switch from the PWM signal of a positive electrode side switch, and the PWM signal of a negative electrode side switch. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a figure for demonstrating the simulation result of a command value signal. It is a circuit diagram for demonstrating the internal structure of the inverter circuit which concerns on 2nd Embodiment. It is a block diagram for demonstrating the internal structure of the PWM signal generation part which concerns on 2nd Embodiment. It is a block diagram for demonstrating the inverter circuit and DC power supply which concern on 3rd Embodiment. It is a block diagram for demonstrating the command value signal generation part which concerns on 3rd Embodiment. It is a block diagram for demonstrating a general grid connection inverter system. It is a circuit diagram which shows an example of an internal structure of an inverter circuit. It is a circuit diagram for demonstrating an example of the internal structure of a 3 level inverter circuit.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, taking as an example the case where the inverter device according to the present invention is used in a grid-connected inverter system.

  FIG. 1 is a block diagram for explaining a grid-connected inverter system including an inverter device according to the present invention.

  As shown in FIG. 1, the grid interconnection inverter system A includes a DC power source 1, an inverter circuit 2, a filter circuit 3, a transformer circuit 4, and a control circuit 5. The DC power source 1 is connected to the inverter circuit 2. The inverter circuit 2 is a three-phase inverter, and the inverter circuit 2, the filter circuit 3, and the transformer circuit 4 are connected in series by output lines of output voltages of U phase, V phase, and W phase in this order. . The output line is connected to the three-phase power system B (system B) via a switch (not shown). A control circuit 5 is connected to the inverter circuit 2. The grid interconnection inverter system A is linked to the grid B by a switch, converts the DC power output from the DC power supply 1 into AC power by the inverter circuit 2 and supplies the AC power to the grid B. Note that various sensors are provided in the grid-connected inverter system A, and the control circuit 5 performs control based on the detection value of the sensor. However, in FIG. 1, the description of various sensors is omitted. Moreover, the structure of the grid connection inverter system A is not restricted to this. For example, instead of the transformer circuit 4, a so-called transformerless system in which a DC / DC converter circuit is provided between the DC power supply 1 and the inverter circuit 2 may be used.

  The DC power source 1 outputs DC power and includes, for example, a solar battery. A solar cell generates direct-current power by converting solar energy into electrical energy. The DC power source 1 outputs the generated DC power to the inverter circuit 2. Note that the DC power source 1 is not limited to one that generates DC power from a solar cell. For example, the DC power source 1 may be a fuel cell, a storage battery, an electric double layer capacitor, or a lithium ion battery. Moreover, the apparatus which converts and outputs the alternating current power produced | generated by the diesel engine generator, the micro gas turbine generator, the wind turbine generator, etc. to direct current power may be sufficient.

  The inverter circuit 2 converts a DC voltage input from the DC power source 1 into an AC voltage and outputs the AC voltage to the filter circuit 3. The inverter circuit 2 is a three-phase PWM control type inverter provided with a switching element (described later), and is a multi-level inverter circuit in which the output phase voltage of each phase becomes a three-level potential. The inverter circuit 2 converts the DC voltage input from the DC power supply 1 into an AC voltage by switching each switching element on and off based on the PWM signal P input from the control circuit 5. A detailed description of the inverter circuit 2 will be described later.

  The filter circuit 3 removes high frequency components due to switching from the AC voltage input from the inverter circuit 2. The filter circuit 3 includes a low-pass filter (not shown) composed of a reactor and a capacitor. The AC voltage from which the high frequency component has been removed by the filter circuit 3 is output to the transformer circuit 4. The configuration of the filter circuit 3 is not limited to this, and any known filter circuit for removing high frequency components may be used. The transformer circuit 4 boosts or steps down the AC voltage output from the filter circuit 3 to a level substantially the same as the system voltage of the system B.

  The control circuit 5 generates a PWM signal P that controls switching of the switching elements of the inverter circuit 2. The control circuit 5 receives detection signals from various sensors (not shown) and outputs a PWM signal P to the inverter circuit 2. The control circuit 5 generates command value signals Xu1, Xv1, and Xw1 for actually instructing the waveform of the phase voltage output from the grid interconnection inverter system A based on detection signals input from various sensors. A PWM signal P is generated based on the value signals Xu1, Xv1, and Xw1. The inverter circuit 2 outputs phase voltages corresponding to the command value signals Xu1, Xv1, and Xw1 by switching each switching element on and off based on the input PWM signal P. The control circuit 5 controls the output current by changing the phase voltage output from the inverter circuit 2 by changing the waveforms of the command value signals Xu1, Xv1, and Xw1. Thereby, the control circuit 5 performs various feedback controls. A detailed description of the control circuit 5 will be described later. Hereinafter, the inverter circuit 2 and the control circuit 5 may be collectively referred to as an inverter device.

  Next, with reference to FIG. 2, the internal configuration and detailed description of the inverter circuit 2 will be described.

  FIG. 2 is a circuit diagram for explaining the internal configuration of the inverter circuit 2. The inverter circuit 2 is a three-phase PWM control type three-level inverter circuit.

  As shown in the figure, the inverter circuit 2 includes 12 switching elements S1 to S12, 12 freewheeling diodes D1 to D12, and 2 voltage dividing capacitors C1 and C2. In the present embodiment, IGBTs (Insulated Gate Bipolar Transistors) are used as the switching elements S1 to S12. The switching elements S1 to S12 are not limited to IGBTs, and may be bipolar transistors, MOSFETs, reverse blocking thyristors, or the like. The types of the freewheeling diodes D1 to D12 and the voltage dividing capacitors C1 and C2 are not limited.

  The voltage dividing capacitors C1 and C2 are capacitors having the same capacitance, and divide the DC voltage input from the DC power supply 1. The voltage dividing capacitor C1 and the voltage dividing capacitor C2 are connected in series at a point O, and are connected in parallel between a point P connected to the positive electrode of the DC power supply 1 and a point N connected to the negative electrode. Since the negative electrode of the DC power supply 1 is grounded, the potential at the point N is “0”. When the potential of the positive electrode of the DC power source 1, that is, the potential at the point P is “E”, the potential at the point O is an intermediate potential between the potential “0” at the point N and the potential “E” at the point P “(1 / 2) E ".

  When the switching element connected to the point O is in the on state, a current flows between the point O and the system B, so that the potential at the point O may change transiently. That is, the potential at the point O is not fixed but changes. If the potential at the point O changes greatly, the waveform of the output phase voltage may be disturbed, making it impossible to perform appropriate control. In the present embodiment, the period of the flag signal fg described later is set so that the amplitude of the change in potential at the point O is a desired value. In some cases, the potential at the point O may be set to a desired potential. In the present embodiment, the duty ratio of the flag signal fg described later (the ratio of the high level period to the cycle) is set so that the center potential of the change in potential at the point O is a desired value.

  The switching elements S1 and S4 are connected in series by connecting the emitter terminal of the switching element S1 and the collector terminal of the switching element S4. The collector terminal of the switching element S1 is connected to the point P, and the emitter terminal of the switching element S4 is connected to the point N to form a bridge structure. Similarly, switching elements S2 and S5 are connected in series to form a bridge structure, and switching elements S3 and S6 are connected in series to form a bridge structure. Since the switching elements S1, S2, and S3 are connected to the positive electrode side of the DC power supply 1, the switching elements S1, S2, and S3 may be described as “positive electrode side switch Sp” if they are not distinguished from each other. On the other hand, since the switching elements S4, S5, and S6 are connected to the negative electrode side of the DC power supply 1, when the switching elements S4, S5, and S6 are not distinguished, they may be described as “negative electrode side switch Sn”. PWM signals P (Pup, Pvp, Pwp, Pun, Pvn, Pwn) output from the control circuit 5 are input to the base terminals of the switching elements S1 to S6, respectively. Details of each PWM signal will be described later.

  The bridge structure formed of switching elements S1 and S4 is a U-phase arm, the bridge structure formed of switching elements S2 and S5 is a V-phase arm, and the bridge structure formed of switching elements S3 and S6 is W Phase arm. The U-phase output line is connected to the connection point U between the switching elements S1 and S4 of the U-phase arm, and the V-phase output line is connected to the connection point V between the switching elements S2 and S5 of the V-phase arm. A W-phase output line is connected to a connection point W between the switching elements S3 and S6 of the W-phase arm.

  The connection point U is connected to the point O via an intermediate switch composed of switching elements S7 and S8. The switching elements S7 and S8 are connected in series with their collector terminals connected. The emitter terminal of the switching element S7 is connected to the point O, and the emitter terminal of the switching element S8 is connected to the point U. Similarly, the connection point V is connected to the point O via an intermediate switch composed of switching elements S9 and S10. Switching elements S9 and S10 have their collector terminals connected, the emitter terminal of switching element S9 is connected to point O, and the emitter terminal of switching element S10 is connected to point V. Further, the connection point W is connected to the point O via an intermediate switch composed of the switching elements S11 and S12. Switching elements S11 and S12 have their collector terminals connected, the emitter terminal of switching element S11 is connected to point O, and the emitter terminal of switching element S12 is connected to point W. The switching elements S7 and S8 perform an on / off operation at the same timing, and conduct the connection between the point O and the point U when in the on state and do not conduct the connection when in the off state. Similarly, the switching elements S9 and S10 also perform the on / off operation at the same timing so that the connection between the point O and the point V is made conductive when in the on state and the connection is not made conductive when in the off state. The switching elements S11 and S12 also perform on / off operations at the same timing so that the connection between the point O and the point W is made conductive when in the on state and the connection is not made conductive when in the off state. In addition, when not distinguishing each intermediate side switch, it may be described as “intermediate side switch So”. PWM signals P (Puo, Pvo, Pwo) output from the control circuit 5 are input to the base terminals of the switching elements S7 and S8, the base terminals of the switching elements S9 and S10, and the base terminals of the switching elements S11 and S12, respectively. Is done.

  Each of the switching elements S1 to S12 can be switched between an on state and an off state based on the PWM signal P. When the positive switch Sp is on and the negative switch Sn and the intermediate switch So are off, the potential of the output line of the phase is the potential of the point P (that is, the positive potential “E” of the DC power supply 1). It becomes. When the negative switch Sn is on and the positive switch Sp and the intermediate switch So are off, the potential of the output line of the phase is the potential at the point N (that is, the negative potential “0” of the DC power supply 1). It becomes. Further, when the intermediate side switch So is on and the positive side switch Sp and the negative side switch Sp are off, the potential of the output line of the phase is the potential of the point O (that is, the positive side and the negative side of the DC power supply 1). The intermediate potential is “(1/2) E”). As a result, the output phase voltage output from each output line has three levels of the potential “E” on the positive side of the DC power supply 1, the potential “0” on the negative side, and the intermediate potential “(1/2) E”. It becomes a potential. Further, the output line voltage, which is the voltage between the output lines, is a five-level potential.

  The free-wheeling diodes D1 to D12 are connected in antiparallel between the collector terminals and the emitter terminals of the switching elements S1 to S12, respectively. That is, the anode terminals of the freewheeling diodes D1 to D12 are connected to the emitter terminals of the switching elements S1 to S12, respectively, and the cathode terminals of the freewheeling diodes D1 to D12 are connected to the collector terminals of the switching elements S1 to S12, respectively. The free-wheeling diodes D1 to D12 are for preventing a high voltage in the reverse direction due to the counter electromotive force generated by switching the switching elements S1 to S12 from being applied to the switching elements S1 to S12.

  Next, the internal configuration and detailed description of the control circuit 5 will be described with reference to FIGS.

  FIG. 3 is a block diagram for explaining the internal configuration of the control circuit 5.

  The control circuit 5 includes a feedback control unit 51, a command value signal generation unit 52, and a PWM signal generation unit 53. Note that the control circuit 5 has a configuration for detecting an overcurrent, a ground fault, a short circuit, a single operation, etc., and stopping the operation of the inverter circuit 2, and a configuration for tracking the maximum power. Therefore, the description and explanation in FIG. 3 are omitted.

  The feedback control unit 51 performs feedback control based on a deviation between detection signals input from various sensors and a preset target value, and commands the waveform of the output phase voltage of the grid-connected inverter system A. The phase voltage command value signals Xu, Xv, and Xw are generated and output to the command value signal generator 52. Details of feedback control performed by the feedback control unit 51 are omitted. The feedback control performed by the feedback control unit 51 may control the output current, output voltage, output active power, and output reactive power output by the grid interconnection inverter system A, or may be output from the DC power supply 1. It may control a DC voltage.

  The command value signal generation unit 52 generates command value signals Xu 1, Xv 1, Xw 1 based on the phase voltage command value signals Xu, Xv, Xw input from the feedback control unit 51 and outputs them to the PWM signal generation unit 53. The command value signals Xu1, Xv1, and Xw1 are signals for actually commanding the waveform of the phase voltage output from the grid interconnection inverter system A. That is, the command value signal generation unit 52 converts the phase voltage command value signals Xu, Xv, Xw into command value signals Xu1, Xv1, Xw1. The waveforms of the command value signals Xu1, Xv1, and Xw1 are specially shaped waveforms such as waveforms Xu1, Xv1, and Xw1 shown in FIG.

  The command value signal generation unit 52 generates line voltage command value signals Xuv, Xvw, Xwu from the phase voltage command value signals Xu, Xv, Xw. That is, the line voltage command value signal Xuv is generated by the difference between the phase voltage command value signals Xu and Xv, the line voltage command value signal Xvw is generated by the difference between the phase voltage command value signals Xv and Xw, and the phase voltage A line voltage command value signal Xwu is generated based on the difference between the command value signals Xw and Xu. The line voltage command value signals Xuv, Xvw, and Xwu are signals for commanding the waveform of the line voltage output from the grid interconnection inverter system A.

  Further, the command value signal generation unit 52 generates signals Xvu, Xwv, and Xuw obtained by inverting the polarities of the line voltage command value signals Xuv, Xvw, and Xwu. Instead of inverting the polarity, the signal Xvu is generated by the difference between the phase voltage command value signals Xv and Xu, the signal Xwv is generated by the difference between the phase voltage command value signals Xw and Xv, and the phase voltage command value The signal Xuw may be generated based on the difference between the signals Xu and Xw.

  The command value signal generation unit 52 uses the line voltage command value signals Xuv, Xvw, Xwu and the signals Xvu, Xwv, Xuw to generate first signals Xu ′, Xv ′, Xw ′ (FIG. 6C described later). And second signals Xu ″, Xv ″, Xw ″ (see FIG. 8C described later) and the first signals Xu ′, Xv ′, Xw ′ and the second signal Xu ″. , Xv ″, Xw ″ are combined to generate command value signals Xu1, Xv1, Xw1. The first signals Xu ′, Xv ′, and Xw ′ are signals having a waveform described in Japanese Patent Laid-Open No. 2010-136547, and the three-phase neutral point potential is changed every 1/3 period. This is a signal for controlling the switching of each phase to be stopped for a period fixed to the negative side potential by fixing the potential of each phase to the negative side potential every 1/3 period. The second signals Xu ″, Xv ″, Xw ″ are signals having waveforms obtained by inverting the polarities of the waveforms of the first signals Xu ′, Xv ′, Xw ′ and shifting them upward by a predetermined value, A period in which the switching of each phase is fixed to the positive potential by shifting the neutral point potential of the three phases every 1/3 cycle and fixing the potential of each phase to the positive potential by 1/3 cycle. It is a signal for performing control to stop.

  Hereinafter, the first signals Xu ′, Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″ will be described with reference to FIGS. 4 to 8.

  FIG. 4 is a diagram for explaining the phase voltage signal and the line voltage signal of each phase of the three-phase alternating current in a three-phase equilibrium state with vectors.

  If the phase voltage signal of the U phase is Vu = A · sin (ωt), the phase of the V phase is delayed by 2π / 3 from the U phase, so the phase voltage signal of the V phase is Vv = A · sin (ωt−2π). / 3). Further, since the phase of the W phase is delayed by 4π / 3 from the U phase (advanced by 2π / 3), Vw = A · sin (ωt + 2π / 3). The U-phase line voltage signal for the V phase is Vuv = Vu−Vv = √ (3) · A · sin (ωt + π / 6), and the V-phase line voltage signal for the W phase is Vvw = Vv−Vw = √ (3) · A · sin (ωt−π / 2), the W-phase line voltage signal for the U phase is Vwu = Vw−Vu = √ (3) · A · sin (ωt−7π / 6) .

  In FIG. 4, the phase voltage signals Vu, Vv, Vw are represented by vectors Pu, Pv, Pw, and the line voltage signals Vuv, Vvw, Vwu are represented by vectors Puv, Pvw, Pwu. A regular triangle T connecting the end points of the vectors Pu, Pv, and Pw starting from the neutral point N is indicated by a broken line, and each vertex is indicated by u, v, and w. This figure shows the state when the X axis is the phase reference (θ = 0 °) and the vector Pu corresponding to the U-phase phase voltage signal Vu matches the X axis. Further, the vectors Pvu, Pwv, and Puw are obtained by reversing the directions of the vectors Puv, Pvw, and Pwu, respectively. Therefore, the signals Vvu, Vwv, and Vuw corresponding to the vectors Pvu, Pwv, and Puw are obtained by shifting the phase of the line voltage signals Vuv, Vvw, and Vwu by π, and Vvu = −Vuv = √ (3) · A Sin (ωt + 7π / 6), Vwv = −Vvw = √ (3) · A · sin (ωt + π / 2), Vuw = −Vwu = √ (3) · A · sin (ωt−π / 6).

  In FIG. 4, a state in which the vectors Pu, Pv, and Pw hold a phase difference of 2π / 3 with each other and rotate at an angular velocity ω counterclockwise around the neutral point N represents a three-phase equilibrium state. ing. Generally, since the neutral point N is set to a reference voltage of 0 [v], each phase voltage signal Vu, Vv, Vw is an orthogonal projection of the vectors Pu, Pv, Pw on the Y axis, as described above. The sine wave signals are out of phase with each other by 2π / 3.

  FIG. 5 is a diagram for explaining the concept of generation of the first signals Xu ′, Xv ′, and Xw ′ using vectors as in FIG. 4. In the vector diagram shown in FIG. 5, the neutral point N is not fixed to 0 [v] and is changed every 1/3 period, and the potential of each phase is changed to the negative side potential (for example, 0 [ v]).

  In FIG. 5, the neutral point N and the vector Pu are shown, and the vectors Pv and Pw are omitted except for the left diagram of FIG. A regular triangle T connecting the end points of the vectors Pu, Pv, and Pw starting from the neutral point N is indicated by a broken line, and each vertex is indicated by u, v, and w. Moreover, in each figure, the white vertex is attached | subjected to the fixed vertex.

  FIG. 4A shows a state where the angle (hereinafter referred to as “angle θ”) made by the vector Pu with the X axis changes from −π / 6 to π / 2. When −π / 6 ≦ θ ≦ π / 2, the V-phase potential is fixed at 0 [v]. This state is referred to as “mode 1”. In mode 1, the vertex v of the regular triangle T is fixed at the origin, and the regular triangle T is counterclockwise about the vertex v (in the direction of the dashed arrow shown in the figure, and the same applies hereinafter) 2π / 3. Represented by rotating. The left figure shows θ = −π / 6, the middle figure shows θ = π / 6, and the right figure shows θ = π / 2. When θ = π / 2, the W-phase potential is fixed at 0 [v]. The figure on the right shows that the phase to be fixed changes from the V phase to the W phase. The equilateral triangle T moves so that the vertex w coincides with the origin, and the neutral point N transitions. It is shown that.

  FIG. 5B shows a state when the angle θ changes from π / 2 to 7π / 6. When π / 2 ≦ θ ≦ 7π / 6, the W-phase potential is fixed at 0 [v]. This state is referred to as “mode 2”. Mode 2 is represented by the vertex w of the equilateral triangle T being fixed at the origin, and the equilateral triangle T being rotated counterclockwise by 2π / 3 around the vertex w. The left figure shows when θ = π / 2, the middle figure shows when θ = 5π / 6, and the right figure shows when θ = 7π / 6. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 7π / 6, the U-phase potential is fixed at 0 [v]. The right figure shows that the phase to be fixed changes from the W phase to the U phase. The equilateral triangle T moves so that the vertex u coincides with the origin, and the neutral point N transitions. It is shown that.

  FIG. 4C shows a state when the angle θ changes from 7π / 6 to 11π / 6 (= −π / 6). When 7π / 6 ≦ θ ≦ 11π / 6, the U-phase potential is fixed at 0 [v]. This state is referred to as “mode 3”. Mode 3 is represented by the fact that the vertex u of the regular triangle T is fixed at the origin, and the regular triangle T rotates counterclockwise by 2π / 3 around the vertex u. The left figure shows θ = 7π / 6, the middle figure shows θ = 3π / 2, and the right figure shows θ = 11π / 6. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 11π / 6, the V-phase potential is fixed at 0 [v]. The figure on the right shows that the phase to be fixed changes from the U phase to the V phase, and the neutral triangle N is moved by moving the equilateral triangle T so that the vertex v coincides with the origin. It is shown that. The figure after this transition is the same as the left figure of FIG. Thereafter, modes 1 to 3 are repeated.

  In the vector diagram shown in FIG. 5, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. For example, the phase voltage of the U phase is represented by the Y coordinate of the vertex u. In mode 1, since the vertex v is fixed at the origin, the orthogonal projection on the Y axis of the vector Puv obtained by subtracting the vector Pv from the vector Pu from the vertex v, that is, the vector Pu is the U-phase phase voltage. (See (a) of the same figure). Therefore, in mode 1, the U-phase first signal Xu ′ may be the line voltage command value signal Xuv.

  In mode 2, since the vertex w is fixed at the origin, the orthogonal projection onto the Y-axis of the vector Puw obtained by subtracting the vector Pw from the vector Pu, that is, the vector Pu from the vertex Pu becomes the U-phase phase voltage. (See (b) of the figure). Therefore, in mode 2, the U-phase first signal Xu ′ may be the signal Xuw (= −Xwu). In mode 3, since the vertex u is fixed at the origin, the phase voltage of the U phase is “0” (see FIG. 10C). Therefore, in mode 3, the U-phase first signal Xu ′ may be a zero signal having a value of “0”.

  Similarly, the V-phase first signal Xv ′ may be a zero signal in mode 1, a line voltage command value signal Xvw in mode 2, and a signal Xvu (= −Xuv) in mode 3. . The W-phase first signal Xw ′ may be a signal Vwv (= −Xvw) in mode 1, a zero signal in mode 2, and a line voltage signal Vwu in mode 3.

  FIG. 6 is a diagram for explaining the waveforms of the first signals Xu ′, Xv ′, and Xw ′.

  A waveform Xuv shown in FIG. 5A is a waveform of the line voltage command value signal Xuv for commanding the waveform of the U-phase line voltage with respect to the V phase. The line voltage command value signal Xuv is a difference signal between the phase voltage command value signal Xu for commanding the waveform of the U-phase phase voltage and the phase voltage command value signal Xv for commanding the waveform of the V-phase phase voltage. It is. Since the amplitude of the phase voltage command value signal Xu is set to “1”, the amplitude of the line voltage command value signal Xuv is √ (3). The waveform Xvw is a waveform of the line voltage command value signal Xvw for commanding the waveform of the V phase line voltage with respect to the W phase. The line voltage command value signal Xvw is a difference signal between the phase voltage command value signal Xv for commanding the waveform of the V-phase voltage and the phase voltage command value signal Xw for commanding the waveform of the W-phase voltage. It is. The waveform Xwu is a waveform of the line voltage command value signal Xwu for commanding the waveform of the W phase line voltage with respect to the U phase. The line voltage command value signal Xwu is a difference signal between the phase voltage command value signal Xw for commanding the waveform of the W phase voltage and the phase voltage command value signal Xu for commanding the waveform of the U phase voltage. It is. In the figure, the phase of the U-phase phase voltage command value signal Xu is described as a reference.

  A waveform Xvu shown in FIG. 5B is a waveform of the signal Xvu obtained by inverting the polarity of the line voltage command value signal Xuv. The waveform Xwv is the waveform of the signal Xwv obtained by inverting the polarity of the line voltage command value signal Xvw, and the waveform Xuw is the waveform of the signal Xuw obtained by inverting the polarity of the line voltage command value signal Xwu.

  Waveforms Xu ′, Xv ′, and Xw ′ shown in FIG. 5C are the waveforms of the first signals Xu ′, Xv ′, and Xw ′, respectively. As described with reference to FIG. 5, the first signals Xu ′, Xv ′, and Xw ′ are generated by being divided into modes 1 to 3.

  The U-phase first signal Xu ′ is generated by switching the line voltage command value signal Xuv, the signal Xuw, and the zero signal. The waveform Xu ′ becomes the waveform Xuv in mode 1 (−π / 6 ≦ θ ≦ π / 2 (= 3π / 6)), and becomes the waveform Xuw in mode 2 (3π / 6 ≦ θ ≦ 7π / 6). In mode 3 (7π / 6 ≦ θ ≦ 11π / 6), the waveform is fixed to “0”. Note that the phase of the phase voltage command value signal Xu is θ.

  Similarly, the V-phase first signal Xv ′ is generated by switching the line voltage command value signal Xvw, the signal Xvu, and the zero signal. The waveform Xv ′ is a waveform fixed to “0” in the mode 1, the waveform Xvw in the mode 2, and the waveform Xvu in the mode 3. The first W-phase signal Xw ′ is generated by switching the line voltage command value signal Xwu, the signal Xwv, and the zero signal. The waveform Xw ′ is a waveform Xwv in mode 1, a waveform fixed to “0” in mode 2, and a waveform Xwu in mode 3.

  7 is a diagram for explaining the concept of generation of the second signals Xu ″, Xv ″, and Xw ″ in terms of vectors. In FIG. 7, as with the vector diagram shown in FIG. N, a vector Pu, and an equilateral triangle T are shown, and the vectors Pv and Pw are omitted except for the figure on the left side of Fig. 7A. 5, each vertex of the regular triangle T is fixed at the origin in the vector diagram shown in Fig. 5, but each vertex of the regular triangle T is "0" in the vector diagram shown in Fig. 7. It is fixed to a point whose Y coordinate is B (hereinafter referred to as “maximum point”).

  FIG. 6A shows a state where the angle θ (the angle that the vector Pu makes with the X axis) changes from π / 6 to 5π / 6. When π / 6 ≦ θ ≦ 5π / 6, the U-phase potential is fixed to B. This state is referred to as “mode 1 ′”. In mode 1 ′, the vertex u of the equilateral triangle T is fixed at the maximum point, and the equilateral triangle T is counterclockwise about the vertex u (in the direction of the broken line arrow shown in the figure, the same applies hereinafter) 2π. It is expressed by rotating 3/3. The left figure shows θ = π / 6, the middle figure shows θ = π / 2 (= 3π / 6), and the right figure shows θ = 5π / 6. When θ = 5π / 6, the V-phase potential is fixed to B. The right figure shows that the phase to be fixed changes from the U phase to the V phase. When the equilateral triangle T moves so that the vertex v coincides with the maximum point, the neutral point N changes. It shows that.

  FIG. 4B shows a state when the angle θ changes from 5π / 6 to 3π / 2 (= 9π / 6). When 5π / 6 ≦ θ ≦ 3π / 2, the V-phase potential is fixed to B. This state is referred to as “mode 2 ′”. Mode 2 ′ is represented by the vertex v of the equilateral triangle T being fixed at the maximum point, and the equilateral triangle T being rotated counterclockwise by 2π / 3 around the vertex v. The left figure shows the case when θ = 5π / 6, the middle figure shows the case when θ = 7π / 6, and the right figure shows the case when θ = 3π / 2 (= 9π / 6). The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 3π / 2, the W-phase potential is fixed to B. The figure on the right shows that the phase to be fixed changes from the V phase to the W phase. The equilateral triangle T moves so that the vertex w coincides with the maximum point, and the neutral point N transitions. It shows that.

  FIG. 4C shows a state when the angle θ changes from 3π / 2 (= 9π / 6) to 13π / 6 (= π / 6). When 3π / 2 ≦ θ ≦ 13π / 6, the potential of the W phase is fixed to B. This state is referred to as “mode 3 ′”. Mode 3 ′ is represented by the vertex w of the regular triangle T being fixed at the maximum point, and the regular triangle T being rotated 2π / 3 counterclockwise around the vertex w. The left figure shows θ = 3π / 2 (= 9π / 6), the middle figure shows θ = 11π / 6, and the right figure shows θ = 13π / 6. The figure on the left is the same figure as after the neutral point transition in the figure on the right in FIG. When θ = 13π / 6, the U-phase potential is fixed to B. The right figure shows that the phase to be fixed changes from the W phase to the U phase. The equilateral triangle T moves so that the vertex u coincides with the maximum point, and the neutral point N transitions. It shows that. The figure after this transition is the same as the left figure of FIG. Thereafter, modes 1 'to 3' are repeated.

  In the vector diagram shown in FIG. 7, the phase voltage of each phase is represented by the Y coordinate of each vertex of the equilateral triangle T. In mode 1 ', the vertex u is fixed at the maximum point, so the phase voltage of the U phase is B (see FIG. 5A). Therefore, in the mode 1 ′, the U-phase second signal Xu ″ may be a signal whose value is B.

  In mode 2 ′, the vertex v is fixed at the maximum point, so the value obtained by adding B to the orthogonal projection of the vector Puv from the vertex v to the vertex u on the Y axis is the U-phase voltage (see FIG. (See (b)). Therefore, in the mode 2 ′, the U-phase second signal Xu ″ may be obtained by adding B to the line voltage command value signal Xuv. In the mode 3 ′, the vertex w is fixed at the maximum point. Therefore, the value obtained by adding B to the orthogonal projection of the vector Puw from the vertex w to the vertex u on the Y axis is the phase voltage of the U phase (see FIG. 5C). The U-phase second signal Xu ″ may be obtained by adding B to the signal Xuw (= −Xwu).

  Similarly, it is assumed that the V-phase second signal Xv ″ is obtained by adding B to the signal Xvu (= −Xuv) in the mode 1 ′, the signal having the value B in the mode 2 ′, and the mode 3 ′. In this case, it is only necessary to add B to the line voltage command value signal Xvw. In addition, in the mode 1 ′, B is added to the line voltage command value signal Xwu. In the mode 2 ′, it is assumed that B is added to the signal Xwv (= −Xvw), and in the mode 3 ′, a signal having a value B may be used.

  FIG. 8 is a diagram for explaining the waveforms of the second signals Xu ″, Xv ″, and Xw ″.

  The waveforms Xuv, Xvw, and Xwu shown in FIG. 8A are the same as the waveforms Xuv, Xvw, and Xwu shown in FIG. 6A, and the waveforms Xvu, Xwv, and Xwu shown in FIG. Since it is the same as the waveforms Xvu, Xwv, and Xuw shown in FIG. Also in FIG. 8, the phase of the phase voltage command value signal Xu is described as a reference.

  Waveforms Xu ″, Xv ″, Xw ″ shown in FIG. 8C are waveforms of the second signals Xu ″, Xv ″, Xw ″, respectively. As described with reference to FIG. 7, the second signals Xu ″, Xv ″, and Xw ″ are generated by being divided into modes 1 ′ to 3 ′. In FIG. The waveform is shown.

  The U-phase second signal Xu ″ switches between a signal obtained by adding “2” to the line voltage command value signal Xuv, a signal obtained by adding “2” to the signal Xuw, and a signal having a value “2”. Generated. The waveform Xu ″ is a waveform fixed to “2” in the mode 1 ′ (π / 6 ≦ θ ≦ 5π / 6), and the mode 2 ′ (5π / 6 ≦ θ ≦ 3π / 2 (= 9π / 6) ) Is a waveform obtained by shifting the waveform Xuv upward by “2”. In mode 3 ′ (3π / 2 ≦ θ ≦ 13π / 6), the waveform Xuv is shifted upward by “2”. Yes. Note that the phase of the phase voltage command value signal Xu is θ.

  Similarly, the V-phase second signal Xv ″ includes a signal obtained by adding “2” to the line voltage command value signal Xvw, a signal obtained by adding “2” to the signal Xvu, and a signal having a value “2”. It is generated by switching. The waveform Xv ″ is a waveform obtained by shifting the waveform Xvu upward by “2” in the mode 1 ′, is a waveform fixed to “2” in the mode 2 ′, and the waveform Xvw is “2” in the mode 3 ′. The waveform is shifted upward by "." The second signal Xw "for the W phase includes a signal obtained by adding" 2 "to the line voltage command value signal Xwu, a signal obtained by adding" 2 "to the signal Xwv, and a signal having a value" 2 ". Generated by switching. The waveform Xw ″ is a waveform obtained by shifting the waveform Xwu upward by “2” in the mode 1 ′, a waveform obtained by shifting the waveform Xwv upward by “2” in the mode 2 ′, and in the mode 3 ′. The waveform is fixed at “2”.

  FIG. 9 is a block diagram for explaining the internal configuration of the command value signal generator 52.

  As shown in the figure, the command value signal generation unit 52 includes a first signal generation unit 521, a second signal generation unit 522, a cycle setting unit 523, a duty ratio setting unit 524, a flag signal generation unit 525, and a signal combination. Part 526 is provided.

  The first signal generation unit 521 generates the first signals Xu ′, Xv ′, and Xw ′. The first signal generation unit 521 generates line voltage command value signals Xuv, Xvw, Xwu from the phase voltage command value signals Xu, Xv, Xw input from the feedback control unit 51, and a signal obtained by inverting these polarities. Xvu, Xwv, and Xuw are generated. The first signal generation unit 521 generates the first signal Xu ′ from the line voltage command value signal Xuv, the signal Xuw, and the zero signal whose value is “0”, and the line voltage command value signal Xvw and the signal Xvu The first signal Xv ′ is generated from the zero signal and the zero signal, and the first signal Xw ′ is generated from the line voltage command value signal Xwu, the signal Xwv, and the zero signal (see FIG. 6). The first signal generation unit 521 outputs the generated first signals Xu ′, Xv ′, and Xw ′ to the signal combination unit 526.

  The second signal generator 522 generates the second signals Xu ″, Xv ″, and Xw ″. The second signal generator 522 receives the phase voltage command value signal Xu, Line voltage command value signals Xuv, Xvw, Xwu are generated from Xv, Xw, and signals Xvu, Xwv, Xuw are generated by inverting these polarities, and the second signal generator 522 is a line voltage command value signal. A second signal Xu ”is generated from the signal obtained by adding“ 2 ”to Xuv, the signal obtained by adding“ 2 ”to the signal Xuw, and the signal having the value“ 2 ”, and the line voltage command value signal Xvw includes“ The second signal Xv ″ is generated from the signal obtained by adding “2”, the signal obtained by adding “2” to the signal Xvu, and the signal having the value “2”, and “2” is added to the line voltage command value signal Xwu. The signal and value obtained by adding “2” to the added signal and the signal Xwv are The second signal Xw ″ is generated from the signal 2 ″ (see FIG. 8). The second signal generation unit 522 supplies the generated second signals Xu ″, Xv ″, Xw ″ to the signal combination unit 526. Output.

  The period setting unit 523 sets a period of a flag signal fg described later. The amplitude of the potential change at the point O (see FIG. 2) of the inverter circuit 2 varies depending on the cycle of the flag signal fg. A value for setting the amplitude to a desired amplitude is acquired in advance by experiment, and the period setting unit 523 sets the value as the period of the flag signal fg. In the following description of the command value signals Xu1, Xv1, and Xw1, the cycle of the flag signal fg is twice the cycle of the first signals Xu ′, Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″. The command value signals Xu1, Xv1, and Xw1 when the cycle of the flag signal fg is changed will be described later.

  The duty ratio setting unit 524 sets a duty ratio of a flag signal fg described later. Depending on the duty ratio of the flag signal fg, the center potential of the potential change at the point O varies. A value for setting the center potential to a desired potential is acquired in advance by experiments, and the duty ratio setting unit 524 sets the value as the duty ratio of the flag signal fg. In the following description of the command value signals Xu1, Xv1, and Xw1, when the duty ratio of the flag signal fg is “0.5”, that is, the period in which the flag signal fg is at the high level is the same as the period in which the flag signal fg is at the low level. The case will be described. The command value signals Xu1, Xv1, and Xw1 when the duty ratio of the flag signal fg is changed will be described later.

  The flag signal generation unit 525 generates a flag signal fg for switching between the first signal and the second signal. The flag signal fg is a signal that switches between “0” (low level) and “1” (high level) in a predetermined cycle. The flag signal generation unit 525 generates a pulse signal having the duty ratio set by the duty ratio setting unit 524 as the flag signal fg in the cycle set by the cycle setting unit 523.

  The signal combination unit 526 includes the first signals Xu ′, Xv ′, Xw ′ input from the first signal generation unit 521 and the second signals Xu ″, Xv ″, Xw ″ is combined to generate command value signals Xu1, Xv1, and Xw1. The signal combination unit 526 is based on the flag signal fg input from the flag signal generation unit 525, and generates the first signal Xu ′. , Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″. That is, the signal combination unit 526 outputs the second signals Xu ″, Xv ″, and Xw ″ while the flag signal fg is “1”, and the first signal Xu ′ while the flag signal fg is “0”. , Xv ′, Xw ′. Signals output from the signal combination unit 526 are output to the PWM signal generation unit 53 as command value signals Xu1, Xv1, and Xw1.

  FIG. 10 is a diagram for explaining the waveforms of the command value signals Xu1, Xv1, and Xw1.

  A waveform fg shown in FIG. 5A shows the waveform of the flag signal fg. The cycle of the flag signal fg is set to be twice the cycle of the first signals Xu ′, Xv ′, Xw ′ and the second signals Xu ″, Xv ″, Xw ″. The first signal Xu ′. Is a cycle of the phase voltage command value signal Xu (hereinafter, the cycle is “T”. Since the cycle T is made to coincide with the cycle of the system voltage, for example, T = 1/60) [S].), The period of the flag signal fg is twice the period T (2T). Further, in the present embodiment, the flag signal fg is switched to “1” when θ = 0 with reference to the phase θ of the phase voltage command value signal Xu. Therefore, the flag signal fg is switched to “0” when θ = 2π, and is switched to “1” when θ = 4π.

  A waveform Xu1 shown in FIG. 5B is a waveform of the U-phase command value signal Xu1. Since the flag signal fg is “1” in the period of 0 ≦ θ ≦ 2π, the command value signal Xu1 is the second signal Xu ″, and in the period of 2π ≦ θ ≦ 4π, the flag signal fg is “0”. The command value signal Xu1 becomes the first signal Xu ′. Therefore, the waveform Xu1 becomes the waveform Xu ″ (see FIG. 8C) in the period of 0 ≦ θ ≦ 2π, and becomes the waveform Xu ′ (see FIG. 6C) in the period of 2π ≦ θ ≦ 4π. .

  Similarly, the waveform Xv1 of the V-phase command value signal Xv1 becomes the waveform Xv ″ in the period of 0 ≦ θ ≦ 2π, and becomes the waveform Xv ′ in the period of 2π ≦ θ ≦ 4π. The waveform Xw1 of the value signal Xw1 becomes a waveform Xw ″ during a period of 0 ≦ θ ≦ 2π, and becomes a waveform Xw ′ during a period of 2π ≦ θ ≦ 4π.

  The difference signal between the command value signals Xu1 and Xv1 is a difference signal between the second signals Xu ″ and Xv ″ in the period of 0 ≦ θ ≦ 2π, and the first signal Xu ′ in the period of 2π ≦ θ ≦ 4π. And Xv ′. The difference signal between the second signals Xu ″ and Xv ″ matches the line voltage command value signal Xuv (see FIG. 8A). Further, the difference signal between the first signals Xu ′ and Xv ′ also matches the line voltage command value signal Xuv (see FIG. 6A). Therefore, the difference signal between the command value signals Xu1 and Xv1 matches the line voltage command value signal Xuv. Similarly, the difference signal between the command value signals Xv1 and Xw1 matches the line voltage command value signal Xvw, and the difference signal between the command value signals Xw1 and Xu1 matches the line voltage command value signal Xwu. Therefore, the line voltage signals Vuv, which are the difference signals between the phase voltage signals Vu1 and Vv1 output from the grid interconnection inverter system A, and the differences between the line voltage signals Vvw, Vw1 and Vu1 which are the difference signals between Vv1 and Vw1. The waveform of the line voltage signal Vwu, which is a signal, is the same as the waveforms Xuv, Xvw, and Xwu shown in FIGS. 8 (a) and 6 (a). That is, the line voltage signals Vuv, Vvw, and Vwu are sine wave signals balanced in three phases, and can be synchronized with the system voltage of the system B. Therefore, the AC power output from the grid interconnection inverter system A can be supplied to the grid B.

  In this embodiment, the amplitudes of the phase voltage command value signals Xu, Xv, Xw are set to “1” for normalization, and therefore the amplitudes of the line voltage command value signals Xuv, Xvw, Xwu are √ (3). (See FIG. 6 (a)). The upper limit value of the command value signals Xu1, Xv1, and Xw1 needs to be a value that is greater than or equal to the amplitude of the line voltage command value signals Xuv, Xvw, and Xwu. Therefore, in the present embodiment, the upper limit value is “2”. Since the upper limit value only needs to be a value greater than the amplitude of the line voltage command value signals Xuv, Xvw, Xwu, a predetermined value of √ (3) or more is set as the upper limit value according to the modulation degree to be set. Is done. The amplitude of a carrier signal to be described later is set according to the upper limit value.

  FIG. 11 is a flowchart for explaining the command value signal generation process performed by the command value signal generation unit 52. The command value signal generation process is executed at a predetermined timing.

  First, line voltage command value signals Xuv, Xvw, Xwu and a flag signal fg are acquired (S101). Next, it is determined whether or not fg is “0” (S102). When fg is “0” (S102: YES), the process proceeds to step S103, and processing for generating the first signals Xu ′, Xv ′, and Xw ′ is performed (S103 to S114). On the other hand, if fg is not “0” (S102: NO), that is, if fg is “1”, the process proceeds to step S115, and processing for generating the second signals Xu ″, Xv ″, Xw ″ is performed ( S115 to S126).

  When the process proceeds to step S103, it is determined whether or not the absolute value of Xuv is larger than the absolute value of Xvw (S103). When the absolute value of Xuv is larger (S103: YES), it is determined whether or not the absolute value of Xuv is larger than the absolute value of Xwu (S104). When the absolute value of Xuv is larger (S104: YES), that is, when the absolute value of Xuv is the maximum, the process proceeds to step S106. On the other hand, if the absolute value of Xuv is less than or equal to the absolute value of Xwu (S104: NO), that is, if the absolute value of Xwu is maximum, the process proceeds to step S107. If the absolute value of Xuv is less than or equal to the absolute value of Xvw in step S103 (S103: NO), it is determined whether or not the absolute value of Xvw is greater than the absolute value of Xwu (S105). When the absolute value of Xvw is larger (S105: YES), that is, when the absolute value of Xvw is the maximum, the process proceeds to step S108. On the other hand, if the absolute value of Xvw is equal to or smaller than the absolute value of Xwu (S105: NO), that is, if the absolute value of Xwu is the maximum, the process proceeds to step S107. In steps S103 to S105, it is determined which of Xuv, Xvw, and Xwu has the maximum absolute value.

  When it is determined that the absolute value of Xuv is the maximum (S103: YES, S104: YES), it is determined whether Xuv is a positive value (S106). When Xuv is a positive value (S106: YES), the command value signal Xu1 is set to Xuv, the command value signal Xv1 is set to “0”, and the command value signal Xw1 is set to a negative value of Xvw (S109). On the other hand, when Xuv is “0” or less (S106: NO), Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu (S110).

  When it is determined that the absolute value of Xwu is the maximum (S103: YES to S104: NO, or S103: NO to S105: NO), it is determined whether Xwu is a positive value (S107). . When Xwu is a positive value (S107: YES), Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu (S111). On the other hand, when Xwu is “0” or less (S107: NO), Xu1 is set to a negative value of Xwu, Xv1 is set to Xvw, and Xw1 is set to “0” (S112).

  When it is determined that the absolute value of Xvw is the maximum (S103: NO, S105: YES), it is determined whether Xvw is a positive value (S108). When Xvw is a positive value (S108: YES), Xu1 is set to a negative value of Xwu, Xv1 is set to Xvw, and Xw1 is set to “0” (S113). On the other hand, when Xvw is equal to or less than “0” (S108: NO), Xu1 is set to Xuv, Xv1 is set to “0”, and Xw1 is set to a negative value of Xvw (S114).

  When the process proceeds to step S115, it is determined whether or not the absolute value of Xuv is larger than the absolute value of Xvw (S115). When the absolute value of Xuv is larger (S115: YES), it is determined whether or not the absolute value of Xuv is larger than the absolute value of Xwu (S116). When the absolute value of Xuv is larger (S116: YES), that is, when the absolute value of Xuv is the maximum, the process proceeds to step S118. On the other hand, when the absolute value of Xuv is equal to or smaller than the absolute value of Xwu (S116: NO), that is, when the absolute value of Xwu is the maximum, the process proceeds to step S119. If the absolute value of Xuv is less than or equal to the absolute value of Xvw in step S115 (S115: NO), it is determined whether or not the absolute value of Xvw is greater than the absolute value of Xwu (S117). When the absolute value of Xvw is larger (S117: YES), that is, when the absolute value of Xvw is the maximum, the process proceeds to step S120. On the other hand, if the absolute value of Xvw is equal to or smaller than the absolute value of Xwu (S117: NO), that is, if the absolute value of Xwu is the maximum, the process proceeds to step S119. In steps S115 to S117, it is determined which of Xuv, Xvw, and Xwu has the maximum absolute value.

  When it is determined that the absolute value of Xuv is the maximum (S115: YES, S116: YES), it is determined whether Xuv is a positive value (S118). When Xuv is a positive value (S118: YES), Xu1 is “2”, Xv1 is a value obtained by subtracting Xuv from “2”, and Xw1 is a value obtained by adding Xwu to “2”. (S121). On the other hand, when Xuv is “0” or less (S118: NO), Xu1 is a value obtained by adding Xuv to “2”, Xv1 is “2”, and Xw1 is a value obtained by subtracting Xvw from “2”. (S122).

  When it is determined that the absolute value of Xwu is the maximum (S115: YES to S116: NO, or S115: NO to S117: NO), it is determined whether Xwu is a positive value (S119). . When Xwu is a positive value (S119: YES), Xu1 is a value obtained by subtracting Xwu from “2”, Xv1 is a value obtained by adding Xvw to “2”, and Xw1 is set to “2”. (S123). On the other hand, when Xwu is “0” or less (S119: NO), Xu1 is set to “2”, Xv1 is set to a value obtained by subtracting Xuv from “2”, and Xw1 is set to a value obtained by adding Xwu to “2”. (S124).

  When it is determined that the absolute value of Xvw is the maximum (S115: NO, S117: YES), it is determined whether Xvw is a positive value (S120). When Xvw is a positive value (S120: YES), Xu1 is a value obtained by adding Xuv to “2”, Xv1 is set to “2”, and Xw1 is a value obtained by subtracting Xvw from “2”. (S125). On the other hand, when Xvw is equal to or less than “0” (S120: NO), Xu1 is a value obtained by subtracting Xwu from “2”, Xv1 is a value obtained by adding Xvw to “2”, and Xw1 is “2”. (S126).

  That is, in the command value signal generation process, it is determined whether fg is “0” or “1”, the line voltage command value signals Xuv, Xvw, and Xwu are determined to have the maximum absolute value, Whether the phase voltage command value signal having the maximum absolute value is positive or negative is determined, and the command value signals Xu1, Xv1, and Xw1 are determined according to the determination result. That is, it is determined which of the modes 1 to 3 of the vector diagram shown in FIG. 5 and modes 1 ′ to 3 ′ of the vector diagram shown in FIG. 7 corresponds to the vector diagram of the determined mode. The command value signals Xu1, Xv1, and Xw1 for each phase are determined.

  In the period from the left figure to the middle figure in the mode 1 state shown in FIG. 5A (hereinafter referred to as “first half part”), the orthogonal projection of the vector Pvw onto the Y axis The length is the maximum, and the Y coordinate of the vector Pvw is a negative value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a negative value (S108: NO in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu1 is set to Xuv, Xv1 is set to “0”, and Xw1 is set to a negative value of Xvw (S114 in FIG. 11).

  In the period from the center diagram to the right diagram in the mode 1 state shown in FIG. 5A (hereinafter referred to as “second half portion”), the orthogonal projection of the vector Puv on the Y-axis is performed. The length is the maximum, and the Y coordinate of the vector Puv is a positive value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a positive value (S106: YES in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are the Y coordinate value of the vector Puv, “0”, and the negative value of the Y coordinate of the vector Pvw, respectively. Therefore, Xu1 is set to Xuv, Xv1 is set to “0”, and Xw1 is set to a negative value of Xvw (S109 in FIG. 11).

  In the case of the first half of the mode 2 state shown in FIG. 5B, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu is a negative value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a negative value (S107: NO in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu1 is a negative value of Xwu, Xv1 is Xvw, and Xw1 is “0” (S112 in FIG. 11).

  In the second half of the mode 2 state shown in FIG. 5B, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pvw has a positive value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a positive value (S108: YES in FIG. 11). Also at this time, the Y coordinates of the vertices u, v, and w are the negative value of the Y coordinate of the vector Pwu and the value of the Y coordinate of the vector Pvw, respectively, “0”. Therefore, Xu1 is a negative value of Xwu, Xv1 is Xvw, and Xw1 is “0” (S113 in FIG. 11).

  In the case of the first half of the mode 3 state shown in FIG. 5C, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Puv is a negative value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a negative value (S106: NO in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu (S110 in FIG. 11).

  In the latter half of the mode 3 state shown in FIG. 5C, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu has a positive value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a positive value (S107: YES in FIG. 11). Also at this time, the Y coordinates of the vertices u, v, and w are “0”, the negative value of the Y coordinate of the vector Puv, and the Y coordinate value of the vector Pwu, respectively. Therefore, Xu1 is set to “0”, Xv1 is set to a negative value of Xuv, and Xw1 is set to Xwu (S111 in FIG. 11).

  In the case of the first half of the mode 1 'state shown in FIG. 7A, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Puv is a positive value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a positive value (S118: YES in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the values obtained by adding the Y coordinate of the vector Pwu to “2”. Accordingly, Xu1 is “2”, Xv1 is a value obtained by subtracting Xuv from “2”, and Xw1 is a value obtained by adding Xwu to “2” (S121 in FIG. 11).

  In the latter half of the mode 1 'state shown in FIG. 7A, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu is a negative value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a negative value (S119: NO in FIG. 11). Also at this time, the Y coordinates of the vertices u, v, and w are values obtained by subtracting the Y coordinate of the vector Puv from “2” and “2”, respectively, and the value obtained by adding the Y coordinate of the vector Pwu to “2”. . Accordingly, Xu1 is “2”, Xv1 is a value obtained by subtracting Xuv from “2”, and Xw1 is a value obtained by adding Xwu to “2” (S124 in FIG. 11).

  In the first half of the mode 2 'state shown in FIG. 7B, the length of the orthogonal projection of the vector Pvw on the Y-axis is the maximum, and the Y coordinate of the vector Pvw is a positive value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a positive value (S120: YES in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. Therefore, Xu1 is a value obtained by adding Xuv to “2”, Xv1 is “2”, and Xw1 is a value obtained by subtracting Xvw from “2” (S125 in FIG. 11).

  In the latter half of the mode 2 'state shown in FIG. 7B, the length of the orthogonal projection of the vector Puv on the Y axis is the maximum, and the Y coordinate of the vector Puv is a negative value. That is, the absolute value of the line voltage command value signal Xuv becomes the maximum, and the line voltage command value signal Xuv becomes a negative value (S118: NO in FIG. 11). Also at this time, the Y coordinates of the vertices u, v, and w are values obtained by adding the Y coordinate of the vector Puv to “2”, and the values obtained by subtracting the Y coordinate of the vector Pvw from “2” and “2”. . Therefore, Xu1 is a value obtained by adding Xuv to “2”, Xv1 is “2”, and Xw1 is a value obtained by subtracting Xvw from “2” (S122 in FIG. 11).

  In the first half of the mode 3 'state shown in FIG. 7C, the length of the orthogonal projection of the vector Pwu on the Y axis is the maximum, and the Y coordinate of the vector Pwu is a positive value. That is, the absolute value of the line voltage command value signal Xwu becomes the maximum, and the line voltage command value signal Xwu becomes a positive value (S119: YES in FIG. 11). At this time, the Y coordinates of the vertices u, v, and w are “2”, a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, a value obtained by adding the Y coordinate of the vector Pvw to “2”, and “2”. Therefore, Xu1 is a value obtained by subtracting Xwu from “2”, Xv1 is a value obtained by adding Xvw to “2”, and Xw1 is “2” (S123 in FIG. 11).

  In the latter half of the mode 3 'state shown in FIG. 7C, the length of the orthogonal projection of the vector Pvw on the Y axis is the maximum, and the Y coordinate of the vector Pvw is a negative value. That is, the absolute value of the line voltage command value signal Xvw becomes the maximum, and the line voltage command value signal Xvw becomes a negative value (S120: NO in FIG. 11). Also at this time, the Y coordinates of the vertices u, v, and w are “2”, which is a value obtained by subtracting the Y coordinate of the vector Pwu from “2”, and a value obtained by adding the Y coordinate of the vector Pvw to “2”, respectively. . Therefore, Xu1 is set to a value obtained by subtracting Xwu from “2”, Xv1 is set to a value obtained by adding Xvw to “2”, and Xw1 is set to “2” (S126 in FIG. 11).

  The waveforms of the command value signals Xu1, Xv1, and Xw1 generated by the command value signal generation processing are as shown by waveforms Xu1, Xv1, and Xw1 shown in FIG. That is, in mode 1 ′, since the process proceeds to step S121 or S124 in the flowchart of FIG. 11, the waveform Xu1 is a waveform fixed to “2”, and the waveform Xv1 is the waveform Xvu (see FIG. 8B) “2”. ”And the waveform Xw1 is a waveform obtained by shifting the waveform Xwu (see FIG. 8A) upward by“ 2 ”. In mode 2 ′, since the process proceeds to step S122 or S125 in the flowchart of FIG. 11, the waveform Xu1 is a waveform obtained by shifting the waveform Xuv upward by “2”, and the waveform Xv1 is a waveform fixed to “2”. Thus, the waveform Xw1 is a waveform obtained by shifting the waveform Xwv upward by “2”. In mode 3 ′, since the process proceeds to step S123 or S126 in the flowchart of FIG. 11, the waveform Xu1 becomes a waveform obtained by shifting the waveform Xuw upward by “2”, and the waveform Xv1 shifts the waveform Xvw upward by “2”. The waveform Xw1 is a waveform fixed to “2”. In mode 1, since the process proceeds to step S109 or S114 in the flowchart of FIG. 11, the waveform Xu1 is the waveform Xuv (see FIG. 6A), the waveform Xv1 is a waveform fixed to “0”, and the waveform Xw1 is the waveform. Xwv (see FIG. 6B). In mode 2, since the process proceeds to step S112 or S113 in the flowchart of FIG. 11, the waveform Xu1 becomes the waveform Xuw, the waveform Xv1 becomes the waveform Xvw, and the waveform Xw1 becomes a waveform fixed to “0”. In mode 3, since the process proceeds to step S110 or S111 in the flowchart of FIG. 11, the waveform Xu1 becomes a waveform fixed to “0”, the waveform Xv1 becomes the waveform Xvu, and the waveform Xw1 becomes the waveform Xwu.

  In addition, the flowchart shown in FIG. 11 is an example of a command value signal generation process, and is not limited to this.

  Returning to FIG. 3, the PWM signal generation unit 53 includes a carrier signal (for example, a triangular wave signal) having a predetermined frequency (for example, 4 kHz) generated therein and a command value input from the command value signal generation unit 52. A PWM signal P is generated based on the signals Xu1, Xv1, and Xw1, and is output to the inverter circuit 2.

  The command value signals Xu1, Xv1, and Xw1 change between the upper limit value “2” and the lower limit value “0” (see FIG. 10B). The PWM signal generation unit 53 sets the upper limit value as the upper limit value “2” of the command value signals Xu1, Xv1, and Xw1, and sets the lower limit value as an intermediate value between the command value signals Xu1, Xv1, and Xw1 (the upper limit value “2” and the lower limit value “ The intermediate value of “0”) is “1”, the carrier signal (hereinafter referred to as “P-side carrier signal”), and the upper limit value is the intermediate value “1” of the command value signals Xu1, Xv1, Xw1, and the lower limit. Two carrier signals are generated, which are carrier signals whose values are the lower limit value “0” of the command value signals Xu1, Xv1, and Xw1 (hereinafter referred to as “N-side carrier signals”). The PWM signal generation unit 53 generates PWM signals Pup, Pvp, and Pwp based on the P-side carrier signal and the command value signals Xu1, Xv1, and Xw1, respectively, and the N-side carrier signal and the command value signals Xu1, Xv1, and Xw1 PWM signals Pun, Pvn and Pwn are generated based on

  FIG. 12 is a diagram for explaining a method of generating PWM signals Pup and Pun from the command value signal Xu1, the P-side carrier signal, and the N-side carrier signal. In the figure, the command value signal Xu1 is indicated by a waveform X, the P-side carrier signal is indicated by a waveform Ca1, and the N-side carrier signal is indicated by a waveform Ca2.

  As shown in FIG. 6A, the waveform Ca1 of the P-side carrier signal is a triangular wave that changes between “2” and “1”, and the waveform Ca2 of the N-side carrier signal is “1” and “0”. Is a triangular wave that changes between The waveform X of the command value signal Xu1 is compared with the waveform Ca1 of the P-side carrier signal and the waveform Ca2 of the N-side carrier signal, and PWM signals Pup and Pun are generated. The carrier signal is not limited to a triangular wave signal, and may be a sawtooth wave, for example.

  The PWM signal generation unit 53 generates a PWM signal Puo from the PWM signal Pup and the PWM signal Pun, generates a PWM signal Pvo from the PWM signal Pvp and the PWM signal Pvn, and generates the PWM signal Pwp from the PWM signal Pwn. A PWM signal Pwo is generated.

  FIG. 13 is a block diagram for explaining the internal configuration of the PWM signal generation unit 53. As shown in the figure, the PWM signal generation unit 53 includes a first comparison unit 531, a second comparison unit 532, and a NOR unit 533.

  The first comparison unit 531 compares the command value signals Xu1, Xv1, Xw1 input from the command value signal generation unit 52 with the P-side carrier signal, and generates PWM signals Pup, Pvp, Pwp, respectively.

  FIG. 12B is a diagram for explaining a method of generating the PWM signal Pup from the command value signal Xu1 and the P-side carrier signal. In FIG. 2B, the PWM signal Pup is indicated by a waveform P1. The first comparison unit 531 generates, as a PWM signal Pup, a pulse signal that becomes high level when the command value signal Xu1 is equal to or higher than the P-side carrier signal and becomes low level when the command value signal Xu1 is smaller than the P-side carrier signal. To do. Accordingly, in FIG. 6B, the waveform P1 is at a high level during a period when the waveform X is equal to or higher than the waveform Ca1, and the waveform P1 is at a low level during a period when the waveform X is smaller than the waveform Ca1.

  The same applies to the method for generating the PWM signal Pvp from the command value signal Xv1 and the P-side carrier signal and the method for generating the PWM signal Pwp from the command value signal Xw1 and the P-side carrier signal. The generated PWM signals Pup, Pvp, Pwp are input to the base terminals of the switching elements S1, S2, S3 of the inverter circuit 2, respectively. Further, the PWM signals Pup, Pvp, Pwp are also input to the NOR unit 533.

  The P-side carrier signal is not limited to a triangular wave signal, and may be, for example, a sawtooth wave signal. Further, the PWM signals Pup, Pvp, Pwp may be generated by a method other than the method based on the comparison between the command value signals Xu1, Xv1, Xw1 and the P-side carrier signal. For example, the pulse width can be calculated using the PWM hold method from the portion where the command value signals Xu1, Xv1, Xw1 are “1” or more, and the PWM signals Pup, Pvp, Pwp can be generated based on the pulse width. (See JP 2010-68630 A).

  The second comparison unit 532 compares the command value signals Xu1, Xv1, and Xw1 input from the command value signal generation unit 52 with the N-side carrier signal and generates PWM signals Pun, Pvn, and Pwn, respectively.

  FIG. 12C is a diagram for explaining a method of generating the PWM signal Pun from the command value signal Xu1 and the N-side carrier signal. In FIG. 3C, the PWM signal Pun is indicated by a waveform P2. The second comparison unit 532 generates, as a PWM signal Pun, a pulse signal that becomes low level when the command value signal Xu1 is larger than the N-side carrier signal and becomes high level when the command value signal Xu1 is equal to or lower than the N-side carrier signal. To do. Accordingly, in FIG. 9C, the waveform P2 is at a low level during a period when the waveform X is greater than the waveform Ca2, and the waveform P2 is at a high level during a period when the waveform X is equal to or less than the waveform Ca2.

  The method for generating the PWM signal Pvn from the command value signal Xv1 and the N-side carrier signal and the method for generating the PWM signal Pwn from the command value signal Xw1 and the N-side carrier signal are the same. The generated PWM signals Pun, Pvn, Pwn are input to the base terminals of the switching elements S4, S5, S6 of the inverter circuit 2, respectively. The PWM signals Pun, Pvn, and Pwn are also input to the NOR unit 533.

  Note that the N-side carrier signal is not limited to a triangular wave signal, and for example, a saw may be a signal. Further, the PWM signals Pun, Pvn, Pwn may be generated by a method other than the method based on the comparison between the command value signals Xu1, Xv1, Xw1 and the N-side carrier signal. For example, the pulse width can be calculated using the PWM hold method from the portion where the command value signals Xu1, Xv1, and Xw1 are less than “1”, and the PWM signals Pun, Pvn, and Pwn can be generated based on the pulse width. .

  The NOR unit 533 receives the PWM signals Pup, Pvp, and Pwp from the first comparison unit 531 and receives the PWM signals Pun, Pvn, and Pwn from the second comparison unit 532, and generates the PWM signals Puo, Pvo, and Pwo. .

  FIG. 14 is a diagram for explaining a method of generating the PWM signal Puo from the PWM signal Pup and the PWM signal Pun. In the figure, PWM signals Pup, Pun, Puo are indicated by waveforms P1, P2, P3, respectively. The NOR unit 533 calculates a negative logical sum of the PWM signal Pup and the PWM signal Pun to generate a PWM signal Puo. Accordingly, in the same figure, the waveform P3 is at the high level only during the period when both the waveform P1 and the waveform P2 are at the low level.

  Similarly, the NOR unit 533 calculates a negative logical sum of the PWM signal Pvp and the PWM signal Pvn to generate a PWM signal Pvo, and calculates a negative logical sum of the PWM signal Pwp and the PWM signal Pwn to calculate the PWM signal Pwo. Is generated. The generated PWM signal Puo is input to the base terminals of the switching elements S7 and S8 of the inverter circuit 2, the PWM signal Pvo is input to the base terminals of the switching elements S9 and S10, and the PWM signal Pwo is the base of the switching elements S11 and S12. Input to the terminal.

  As shown in FIG. 12B, the PWM signal Pup (waveform P1) becomes a high level only when the command value signal Xu1 (waveform X) is “1” or more (the command value signal Xu1 is less than “1”). When you continue low level). Further, as shown in FIG. 12C, the PWM signal Pun (waveform P2) becomes high level only when the command value signal Xu1 is less than “1” (when the command value signal Xu1 is “1” or more). Continue low level). That is, the high level periods of the PWM signal Pup and the PWM signal Pun do not overlap. Further, the PWM signal Puo becomes a high level when both the PWM signal Pup and the PWM signal Pun are at a low level. Accordingly, only one of the PWM signal Pup, the PWM signal Pun, and the PWM signal Puo is at a high level (see FIG. 14).

  When the PWM signal Pup is at a high level, the switching element S1 is turned on, and the switching element S4 and the switching elements S7, S8 are turned off, so that the U-phase output phase voltage is the potential at the point P (that is, the DC power supply 1 Potential (E) on the positive electrode side) (see FIG. 2). When the PWM signal Pun is at a high level, the switching element S4 is turned on, and the switching element S1 and the switching elements S7, S8 are turned off, so that the U-phase output phase voltage is the potential at the point N (that is, the DC power supply 1 The potential on the negative electrode side is “0”). Further, when the PWM signal Puo is at a high level, the switching elements S7 and S8 are in the on state, and the switching elements S1 and S4 are in the off state. 1 between the positive electrode side and the negative electrode side ("(1/2) E"). As a result, the U-phase output phase voltage becomes a three-level potential of the positive potential “E”, the negative potential “0”, and the intermediate potential “(1/2) E” of the DC power supply 1.

  Similarly, the output phase voltages of the V phase and the W phase are also three-level potentials of the potential “E” on the positive side of the DC power supply 1, the potential “0” on the negative side, and the intermediate potential “(1/2) E”. It becomes. Further, the U-phase output line voltage with respect to the V-phase is the difference between the U-phase output phase voltage and the V-phase output phase voltage. Therefore, the U-phase output line voltage with respect to the V phase has five levels of potentials “−E”, “− (1/2) E”, “0”, “(1/2) E”, and “E”. It becomes. The same applies to the V-phase output line voltage for the W-phase and the W-phase output line voltage for the U-phase.

  In the period t1 in FIG. 14, the PWM signal Pup (waveform P1) is fixed at a high level, and the PWM signal Pun (waveform P2) and the PWM signal Puo (waveform P3) are fixed at a low level. In this case, the switching elements S1, S4, S7 and S8 to which the PWM signals Pup, Pun and Puo are respectively input stop switching. In the period t6, the PWM signal Pup (waveform P1) and the PWM signal Puo (waveform P3) are fixed at a low level, and the PWM signal Pun (waveform P2) is fixed at a high level. Also in this case, the switching elements S1, S4, S7 and S8 stop switching.

  Note that the configuration of the PWM signal generation unit 53 is not limited to that described above. Any other method may be used as long as it can generate PWM signals for driving the positive switch, the negative switch, and the intermediate switch from the command value signals Xu1, Xv1, and Xw1, respectively. For example, it may be configured to apply an instantaneous space vector selection method.

  The control circuit 5 may be realized as an analog circuit or a digital circuit. Further, the processing performed by each unit may be designed by a program, and the computer may function as the control circuit 5 by executing the program. The program may be recorded on a recording medium and read by a computer.

  Next, the waveform of the command value signals Xu1, Xv1, and Xw1 and the change waveform of the potential at the point O when the period or the duty ratio of the flag signal fg is changed will be described with reference to FIGS.

  When the intermediate side switch So (switching elements S7 to S12) of any phase is in the on state, the current flows into the point O when the positive side switch Sp (switching elements S1 to S3) of the other phase is in the on state. When the negative electrode side switch Sn (switching elements S4 to S6) of the current phase is turned on, current flows out from the point O. While the flag signal fg is “1”, any one of the command value signals Xu1, Xv1, Xw1 is fixed to “2”, and while the flag signal fg is “0”, any one of the command value signals Xu1, Xv1, Xw1 Is fixed to “0”. Therefore, while the flag signal fg is “1”, the ON state of any of the positive side switches Sp continues, so that the potential rises due to the current flowing into the point O, while the flag signal fg is “0”. Since any one of the negative-side switches Sn is continuously turned on, the electric potential flows down from the point O so that the potential drops. Therefore, when the cycle of the flag signal fg is shortened, the rise time and the fall time of the potential at the point O are shortened, so that the amplitude of the change in the potential at the point O becomes small. On the contrary, as the period of the flag signal fg becomes longer, the rise time and the fall time of the potential at the point O become longer, so that the amplitude of the change in the potential at the point O becomes larger. That is, the amplitude of the change in the potential at the point O changes according to the cycle of the flag signal fg.

  Further, when the duty ratio of the flag signal fg is “0.5”, the time when any of the positive-side switches Sp is turned on is equal to the time when any of the negative-side switches Sn is turned on. The current flowing into O and the current flowing out from point O are balanced, and the center potential of the change in potential at point O hardly changes. When the duty ratio of the flag signal fg is larger than “0.5”, the time during which the positive switch Sp is turned on is longer than the time during which the negative switch Sn is turned on, and the current flows into the point O. Since this is longer than the time for flowing out, the central potential of the change in potential at the point O becomes higher. When the potential at the point O rises, the current flowing into the point O decreases, so that the central potential of the change in the potential at the point O hardly changes at a constant potential. On the other hand, when the duty ratio of the flag signal fg is smaller than “0.5”, the time during which the positive switch Sp is turned on is shorter than the time during which the negative switch Sn is turned on. Since the flowing time becomes shorter than the flowing time, the central potential of the potential change at the point O becomes lower. When the potential at the point O decreases, the current flowing out from the point O becomes small, so that the central potential of the change in the potential at the point O hardly changes at a constant potential. That is, the center potential of the change in the potential at the point O is fixed at a constant potential that changes according to the duty ratio of the flag signal fg.

  15 to 23 are diagrams for explaining simulation results of the command value signals Xu1, Xv1, and Xw1. In these figures, the waveforms of the command value signals Xu1, Xv1, and Xw1, the waveform of the flag signal fg, the waveform of the output line voltage, and the potential at the point O when the cycle or the duty ratio of the flag signal fg is changed. The change waveform is shown. The simulation is for a case where the input voltage is 400 V and the voltage dividing capacitors C1 and C2 are 2200 μF.

  FIG. 15 shows a case where the period of the flag signal fg is 2T (= 1/30 [s]: frequency 30 Hz) and the duty ratio is “0.5”. The phase of the flag signal fg matches the phase θ of the phase voltage command value signal Xu (that is, the flag signal fg is switched to “1” when θ = 0) (FIG. 16). The same applies to FIG. 23). Since the conditions in this case are the same as those in FIG. 10, the waveforms of the command value signals Xu1, Xv1, and Xw1 and the waveform of the flag signal fg coincide with the waveforms shown in FIG. In this case, the potential at the point O changes between about 187 V and about 213 V, the amplitude of the change is about 26 V, and the center potential of the change is about 200 V.

  FIG. 16 shows a case where the cycle of the flag signal fg is half that of FIG. That is, the flag signal fg has a period T (= 1/60 [s]: frequency 60 Hz) and a duty ratio “0.5”. Each waveform of the command value signals Xu1, Xv1, and Xw1 includes a portion in the period of 0 ≦ θ ≦ π of the waveform of FIG. 8C and a portion of the waveform in FIG. 6C of π ≦ θ ≦ 2π. It is a combined waveform. In this case, when compared with the waveform of FIG. 15, the period in which the command value signal Xu1 is fixed to “0” and the period in which the command value signal Xu1 is fixed to “2” become longer, and the command value signals Xv1 and Xw1 have “0”. The period fixed to “2” and the period fixed to “2” are shortened. However, the period fixed to “0” and the period fixed to “2” in each command value signal Xu1, Xv1, Xw1 are the same. Also in this case, the time during which the positive electrode side switch Sp is in the on state is equal to the time during which the negative electrode side switch Sn is in the on state. In this case, the potential at the point O changes between about 195V and about 207V, the amplitude of the change is about 12V, and the center potential of the change is about 201V. Compared with the case of FIG. 15, the central potential of the change hardly changes, and the amplitude of the change is small.

  FIG. 17 shows a case where the cycle of the flag signal fg is ¼ that of FIG. In other words, the flag signal fg has a period of 0.5T (= 1/120 [s]: frequency 120 Hz) and a duty ratio of “0.5”. Each waveform of the command value signals Xu1, Xv1, and Xw1 is a portion of a period of 0 ≦ θ ≦ π / 2 of the waveform of FIG. 8C, and a period of π / 2 ≦ θ ≦ π of the waveform of FIG. 8c, the portion of the waveform in the period of π ≦ θ ≦ 3π / 2, and the portion of the waveform of FIG. 6C in the period of 3π / 2 ≦ θ ≦ 2π. ing. In this case, when compared with the waveform of FIG. 15, the period in which the command value signal Xu1 is fixed to “0” is the same as the period in which the command value signal Xu1 is fixed to “2”. The period fixed at “0” is different from the period fixed at “2”. Even in this case, the time during which any of the positive-side switches Sp is in the ON state is equal to the time during which any of the negative-side switches Sn is in the ON state. In this case, the potential at the point O changes between about 198V and about 205.5V, the amplitude of the change is about 7.5V, and the center potential of the change is about 201.75V. Compared to the case of FIG. 15, the central potential of the change hardly changes, and the amplitude of the change is greatly reduced.

  FIG. 18 shows a case where the cycle of the flag signal fg is 1.5 times that in the case of FIG. That is, the period of the flag signal fg is 3T (= 1/20 [s]: frequency 20 Hz) and the duty ratio is “0.5”. Each waveform of the command value signals Xu1, Xv1, and Xw1 includes a portion in the period of 0 ≦ θ ≦ 3π of the waveform of FIG. 8C and a portion of the waveform in FIG. 6C of π ≦ θ ≦ 4π. It is a combined waveform. In this case, the period fixed to “0” and the period fixed to “2” in the command value signals Xu1, Xv1, and Xw1 are the same. Also in this case, the time during which the positive electrode side switch Sp is in the on state is equal to the time during which the negative electrode side switch Sn is in the on state. In this case, the potential at the point O changes between about 183V and about 220V, the amplitude of the change is about 37V, and the center potential of the change is about 201.5V. Compared with the case of FIG. 15, the central potential of the change hardly changes and the amplitude of the change is large.

  FIG. 19 shows a case where the cycle of the flag signal fg is double that in the case of FIG. That is, the period of the flag signal fg is 4T (= 1/15 [s]: frequency 15 Hz) and the duty ratio is “0.5”. Each waveform of the command value signals Xu1, Xv1, and Xw1 includes a portion in the period of 0 ≦ θ ≦ 4π of the waveform in FIG. 8C and a portion of the waveform in FIG. 6C in the period of 0 ≦ θ ≦ 4π. It is a combined waveform. In this case, the period in which the command value signals Xu1, Xv1, and Xw1 are fixed to “0” and the period that is fixed to “2” are all 1/6 of one cycle. Therefore, the time during which the positive switch Sp is in the on state is equal to the time during which the negative switch Sn is in the on state. In this case, the potential at the point O changes between about 176 V and about 228 V, the amplitude of the change is about 52 V, and the center potential of the change is about 202. Compared to the case of FIG. 15, the central potential of the change hardly changes, and the amplitude of the change is greatly increased.

  As shown in FIGS. 15 to 19, the command value signals Xu1, Xv1, and Xw1 have different waveforms from each other. In particular, when the cycle is T (see FIG. 16), the difference between the waveforms is remarkable. When the command value signals Xu1, Xv1, and Xw1 have different waveforms, the influence of the error voltage due to the dead time inserted when generating the PWM signal may differ depending on the phase. In order to solve this problem, the command value signals Xu1, Xv1, and Xw1 may have the same waveform.

  20 and 21 are diagrams for explaining the case where the command value signals Xu1, Xv1, and Xw1 have the same waveform. In the figure, the phase of the flag signal fg is matched with the phase θ of the phase voltage command value signal Xu. Further, the duty ratio of the flag signal fg is set to “0.5”.

  When the cycle of the flag signal fg is 4T / 3 (= 1/45 [s]: frequency 45 Hz), the command value signals Xu1, Xv1, and Xw1 have the same waveform. FIG. 20 shows a waveform when the period of the flag signal fg is 4T / 3. The waveform corresponds to a portion of the waveform of FIG. 8C in the period of 0 ≦ θ ≦ 4π / 3, a portion of the waveform of FIG. 6C in the period of 4π / 3 ≦ θ ≦ 8π / 3, and FIG. ) Waveform portion of 2π / 3 ≦ θ ≦ 2π, FIG. 6C waveform portion of 0 ≦ θ ≦ 4π / 3, and FIG. 8C waveform portion of 4π / 3 ≦ θ ≦. The waveform is a combination of the 8π / 3 period portion and the 2π / 3 ≦ θ ≦ 2π period portion of the waveform of FIG. 6C. In this case, the command value signals Xu1, Xv1, and Xw1 have the same waveform. When the frequency of the flag signal fg is a multiple of 3 / 4T (45 Hz) (that is, 3 / 2T (90 Hz), 9 / 4T (135 Hz), 3 / T (180 Hz), etc.), the command value signals Xu1, Xv1, The waveform of Xw1 becomes the same waveform. FIG. 21 shows a waveform when the frequency of the flag signal fg is 3 / T.

  Note that the cycle of the flag signal fg is not limited to that described above. When the duty ratio is “0.5”, the waveform of the command value signals Xu1, Xv1, and Xw1 varies depending on the cycle of the flag signal fg, but the time when any positive switch Sp is turned on and any negative side This is equivalent to the time for which the switch Sn is turned on. Therefore, the center potential of the change in the potential at the point O is the same as in the case of FIG. On the other hand, the amplitude of the change in potential at the point O decreases as the period of the flag signal fg decreases, and increases as the period of the flag signal fg increases. In addition, the waveform of the command value signals Xu1, Xv1, and Xw1 varies depending on the phase of the flag signal fg, but when the duty ratio is “0.5”, the time when one of the positive side switches Sp is turned on and the time The time for which the negative electrode side switch Sn is turned on is equivalent. Therefore, the center potential of the change in the potential at the point O is the same as in the case of FIG.

  FIG. 22 shows a case where the duty ratio of the flag signal fg is made smaller than that in FIG. 15, the duty ratio is “0.45”, and the cycle is 2T. Each waveform of the command value signals Xu1, Xv1, and Xw1 is a portion of the period of 0 ≦ θ ≦ 1.8π (= 4π · 0.45) of the waveform of FIG. 8C and 1 of the waveform of FIG. The waveform is a combination of the period of 8π ≦ θ ≦ 4π. In this case, as compared with the waveform of FIG. 15, the period in which the command value signals Xu1 and Xv1 are fixed to “0” is longer, and the period in which the command value signal Xw1 is fixed to “2” is shorter. . Therefore, the period fixed to “0” in each of the command value signals Xu1, Xv1, and Xw1 is longer than the period fixed to “2”. In this case, the potential at the point O changes between about 164V and about 190V, the amplitude of the change is about 26V, and the center potential of the change is about 177V. Compared to the case of FIG. 15, the amplitude of the change hardly changes, and the central potential of the change is low.

  FIG. 23 shows a case where the duty ratio of the flag signal fg is made larger than that in FIG. 15, the duty ratio is “0.55”, and the cycle is 2T. Each waveform of the command value signals Xu1, Xv1, and Xw1 includes a portion of a period of 0 ≦ θ ≦ 2.2π (= 4π · 0.55) of the waveform of FIG. 8C and 2 of the waveform of FIG. 6C. The waveform is a combination of the period of 2π ≦ θ ≦ 4π. In this case, as compared with the waveform of FIG. 15, the period in which the command value signals Xu1 and Xw1 are fixed to “2” becomes longer, and the period in which the command value signal Xv1 is fixed to “0” becomes shorter. . Therefore, the period fixed to “0” in each command value signal Xu1, Xv1, Xw1 is shorter than the period fixed to “2”. In this case, the potential at the point O changes between about 211V and about 237V, the amplitude of the change is about 26V, and the center potential of the change is about 224V. Compared to the case of FIG. 15, the amplitude of the change hardly changes, and the central potential of the change is high.

  Note that the duty ratio of the flag signal fg is not limited to that described above. The command value signals Xu1, Xv1, and Xw1 have different waveforms depending on the duty ratio of the flag signal fg. As the duty ratio becomes smaller, the period in which the command value signals Xu1, Xv1, and Xw1 are fixed to “0” becomes longer than the period in which the instruction value signals Xu1, Xv1, and Xw1 are fixed to “2”. The potential is lowered. Further, as the duty ratio increases, the period in which the command value signals Xu1, Xv1, and Xw1 are fixed to “0” becomes shorter than the period in which the command value signals Xu1, Xv1, and Xw1 are fixed to “2”. The center potential of becomes higher. However, when the duty ratio is away from “0.5” and the central potential of the change in potential at the point O is away from the intermediate potential of the input voltage, the waveform of the output line voltage is disturbed (FIGS. 22 and 23). reference). Therefore, the duty ratio can be changed only within a range in which the output line voltage can be appropriately controlled. On the other hand, the amplitude of the change in potential at the point O is the same as in FIG. 15 regardless of the duty ratio.

  In the present embodiment, the command value signals Xu1, Xv1, and Xw1 are periodic signals, and are fixed to “0” in a predetermined period and fixed to “2” in another predetermined period (FIG. 10B). )reference). Therefore, in the PWM signals Pup, Pvp, Pwp generated by comparing the command value signals Xu1, Xv1, Xw1 and the P-side carrier signal, the command value signals Xu1, Xv1, Xw1 are fixed to “2”. The high level is continued during the period (see FIG. 12B). Further, in the PWM signals Pun, Pvn, Pwn generated by comparing the command value signals Xu1, Xv1, Xw1 and the N-side carrier signal, the command value signals Xu1, Xv1, Xw1 are fixed to “0”. The high level is continued during the period (see FIG. 12C). Furthermore, the PWM signals Pup, Pvo, and Pwo generated as the negative logical sums of the PWM signals Pup, Pvp, and Pwp and the PWM signals Pun, Pvn, and Pwn are periods in which the PWM signals Pup, Pvp, and Pwp continue to be at a high level. In addition, the PWM signal Pun, Pvn, Pwn is kept at the low level during the period in which the PWM signal is kept at the high level (see FIG. 14). Since the switching of the switching element is stopped in a period in which each PWM signal continues at the high level or the low level, the number of times of switching can be reduced, and the switching loss can be reduced.

  In the present embodiment, the center potential of the potential change at the point O (see FIG. 2) of the inverter circuit 2 changes according to the duty ratio of the flag signal fg. Therefore, a value for setting the center potential to a desired potential can be acquired and set in advance. As a result, the center potential of the potential change at the point O can be set to a desired potential. The amplitude of the change in potential at the point O of the inverter circuit 2 changes according to the cycle of the flag signal fg. Therefore, it is possible to acquire and set in advance a value for setting the amplitude to a desired amplitude. Thereby, the amplitude of the potential change at the point O can be set to a desired amplitude. Therefore, the potential at the point O can be controlled to an arbitrary potential.

  In the present embodiment, the voltage applied to the positive switch Sp and the voltage applied to the negative switch Sn can be made different by controlling the potential at the point O to a desired potential. For example, a switching element having a low withstand voltage is used for the positive switch Sp by controlling the potential at the point O so that the voltage applied to the positive switch Sp is low and the voltage applied to the negative switch Sn is high. be able to. In this case, for example, a MOSFET having a low withstand voltage but fast switching may be used for the positive switch Sp, and an IGBT having a slow but high withstand voltage may be used for the negative switch Sn.

  In the above embodiment, the case where the frequency of the P-side carrier signal and the frequency of the N-side carrier signal are the same has been described. However, the present invention is not limited to this, and the frequencies of both may be different. For example, when a MOSFET is used for the positive switch Sp and an IGBT is used for the negative switch Sn, the frequency of the P-side carrier signal may be higher than the frequency of the N-side carrier signal.

  Further, in the above embodiment, the capacitances of the voltage dividing capacitors C1 and C2 are the same, and the potential at the point O is set to the potential “(1/2) between the potential“ 0 ”at the point N and the potential“ E ”at the point P. ) E ”has been described, but is not limited thereto. For example, the ratio of the capacitance of the voltage dividing capacitor C1 and the capacitance of the voltage dividing capacitor C2 may be 2: 1, and the potential at the point O may be “(2/3) E”. In this case, the lower limit value of the P-side carrier signal and the upper limit value of the N-side carrier signal must be “4/3” (see FIG. 12A). In this case, when the duty ratio of the flag signal fg is “0.5”, the center potential of the potential change at the point O is “(2/3) E”. Therefore, when the duty ratio is increased within a range in which the output line voltage can be appropriately controlled, the center potential of the change in the potential at the point O can be set to a larger value. Moreover, since the voltage applied to the positive electrode side switch Sp can be made lower, a switching element with a low withstand voltage can be used by the positive electrode side switch Sp.

  In the above-described embodiment, the case where the upper limit value of the command value signals Xu1, Xv1, and Xw1 is “2” and the lower limit value is “0” has been described. For example, the command value signals Xu1, Xv1, and Xw1 may be generated so that the upper limit value is “1” and the lower limit value is “−1”. In this case, it is necessary to change the upper limit value and the lower limit value of the P-side carrier signal and the N-side carrier signal. That is, it is necessary to set the upper limit value of the P-side carrier signal to “1”, the lower limit value to “0”, the upper limit value of the N-side carrier signal to “0”, and the lower limit value to “−1”.

  In the above embodiment, the case where the negative electrode of the DC power supply 1 is grounded and the potential at the point N is “0” has been described, but the present invention is not limited to this. For example, the present invention can be applied even when the positive electrode of the DC power supply 1 is grounded and the potential at the point P is “0”, or when the potential at the point O is grounded and the potential at the point O is “0”. it can.

  The internal configuration of the inverter circuit is not limited to the inverter circuit 2 (see FIG. 2) of the above embodiment (hereinafter referred to as “first embodiment”). The present invention can be applied even when other types of three-level inverter circuits are used. Below, with reference to FIG. 24 and FIG. 25, the example at the time of using another kind of 3-level inverter circuit is demonstrated as 2nd Embodiment.

  FIG. 24 is a circuit diagram for explaining an internal configuration of the inverter circuit according to the second embodiment.

  The inverter circuit 2 'is a three-phase PWM control type inverter, and is a three-level inverter circuit in which the output phase voltage of each phase becomes a three-level potential. As shown in the figure, each phase arm of the inverter circuit 2 ′ has four switching elements connected in series (for example, switching elements S1, S1 ′, S4 ′, S4 in the case of a U-phase arm) and each switching element. It consists of four diodes connected in antiparallel to the element. In addition, between the point P connected to the positive electrode of the DC power source 1 and the point N connected to the negative electrode, two voltage dividing capacitors C1 and C2 having the same capacitance and connected in series are connected in parallel. The connection point of the two switching elements on the positive side of each arm (for example, switching elements S1 and S1 ′ in the case of the U-phase arm) is connected to the connection point O between the capacitor C1 and the capacitor C2 via the clamp diode Dc1. ing. Further, the connection point of two switching elements on the negative electrode side of each arm (for example, switching elements S4 'and S4 in the case of a U-phase arm) is connected to a connection point O via a clamp diode Dc2. An output line of the phase is connected to a connection point of two switching elements (for example, switching elements S1 'and S4' in the case of a U-phase arm) that are not connected to both poles of each arm.

  The U-phase output phase voltage of the inverter circuit 2 ′ becomes a three-level potential depending on the state of the switching element. When the negative electrode potential of the DC power supply 1 is “0” and the positive electrode potential is “E”, when the switching elements S1 and S1 ′ are in the on state and the switching elements S4 and S4 ′ are in the off state, the potential of the output line is “ E ”, when the switching elements S4 and S4 ′ are in the on state and the switching elements S1 and S1 ′ are in the off state, the potential of the output line is“ 0 ”, and the switching elements S1 ′ and S4 ′ are in the on state and the switching element S1 When S4 and S4 are off, the potential of the output line is “(1/2) E”.

  FIG. 25 is a block diagram for explaining an internal configuration of a PWM signal generation unit according to the second embodiment. In the figure, the same or similar elements as those of the PWM signal generation unit 53 shown in FIG.

  The PWM signal generation unit 53 ′ includes OR units 534 and 535, and generates a PWM signal to be input to the switching elements S1 ′ to S6 ′. Different.

  The OR unit 534 receives the PWM signals Pup, Pvp, Pwp from the first comparison unit 531, receives the PWM signals Puo, Pvo, Pwo from the NOR unit 533, and inputs them to the switching elements S1 ′ to S3 ′. A PWM signal is generated. The OR unit 534 calculates a logical sum of the PWM signal Pup and the PWM signal Puo, and generates a PWM signal to be input to the switching element S1 '. Therefore, the PWM signal to be input to the switching element S1 ′ is when the PWM signal Pup is at a high level or when the PWM signal Puo is at a high level (that is, when both the PWM signal Pup and the PWM signal Pun are at a low level). ) Becomes high level. Similarly, the OR unit 534 calculates a logical sum of the PWM signal Pvp and the PWM signal Pvo, and generates a PWM signal to be input to the switching element S2 '. Further, the logical sum of the PWM signal Pwp and the PWM signal Pwo is calculated to generate a PWM signal to be input to the switching element S3 '.

  The OR unit 535 receives the PWM signals Pun, Pvn, and Pwn from the second comparison unit 532, receives the PWM signals Puo, Pvo, and Pwo from the NOR unit 533, and inputs them to the switching elements S4 ′ to S6 ′. A PWM signal is generated. The OR unit 535 calculates a logical sum of the PWM signal Pun and the PWM signal Puo, and generates a PWM signal to be input to the switching element S4 '. Therefore, the PWM signal to be input to the switching element S4 ′ is when the PWM signal Pun is at a high level or when the PWM signal Puo is at a high level (that is, when both the PWM signal Pup and the PWM signal Pun are at a low level). ) Becomes high level. Similarly, the OR unit 535 calculates a logical sum of the PWM signal Pvn and the PWM signal Pvo, and generates a PWM signal to be input to the switching element S5 '. Further, a logical sum of the PWM signal Pwn and the PWM signal Pwo is calculated to generate a PWM signal to be input to the switching element S6 '.

  Note that the configuration of the PWM signal generation unit 53 ′ is not limited to that described above. Any other method may be used as long as it can generate a PWM signal for driving each switching element from the command value signals Xu1, Xv1, and Xw1.

  Also in the second embodiment, since the PWM signal generated based on the command value signals Xu1, Xv1, and Xw1 is input, the number of switching times of the switching element can be reduced, and the switching loss can be reduced. Further, the center potential and the amplitude of the potential change at the point O (see FIG. 24) of the inverter circuit 2 'also change according to the duty ratio and the period of the flag signal fg, respectively. Therefore, the potential at the point O can be controlled to an arbitrary potential.

  In the first and second embodiments, the case where the cycle and the duty ratio of the flag signal fg are set in advance has been described. However, the cycle or the duty ratio of the flag signal fg may be changed according to the situation. An example in which the duty ratio of the flag signal fg is changed according to the situation will be described as a third embodiment with reference to FIGS.

  FIG. 26 is a block diagram for explaining an inverter circuit and a DC power source according to the third embodiment. In the figure, the same or similar elements as those of the inverter circuit 2 shown in FIG.

  The inverter circuit 2 ″ divides the DC voltage input from the DC power supply 1 by the voltage dividing capacitors C1 and C2, so that the point O becomes an intermediate potential, and the two DC power supplies 1′a and 1′b are connected. This is different from the inverter circuit 2 (see FIG. 2) according to the first embodiment in that the point O, which is a connection point between them, is set to an intermediate potential, and the DC power supplies 1′a and 1′b are solar cells. It has.

  FIG. 27 is a block diagram for explaining a command value signal generation unit according to the third embodiment. In the figure, the same or similar elements as those in the command value signal generation unit 52 shown in FIG.

  The command value signal generation unit 52 ′ differs from the command value signal generation unit 52 (see FIG. 9) in that it includes a duty ratio change unit 527. The duty ratio changing unit 527 receives a target voltage for causing the outputs of the DC power supplies 1′a and 1′b to follow the maximum power, and sets the center potential of the change in the potential at the point O to an appropriate potential. The duty ratio (of the flag signal fg) is determined. The target voltage for maximum power tracking is calculated by well-known maximum power tracking control (detailed description is omitted). As described above, the center potential of the change of the potential at the point O changes according to the duty ratio of the flag signal fg. The duty ratio changing unit 527 has a target ratio R (= E2 / (E1 + E2)) that is a ratio of the target voltage E2 to the total value of the target voltage E1 of the DC power supply 1′a and the target voltage E2 of the DC power supply 1′b. The correspondence relationship with the duty ratio of the flag signal fg is stored, the target ratio R is calculated from the input target voltages E1 and E2, and the corresponding duty ratio is determined. For example, when E1 and E2 are equal, the duty ratio corresponding to the target ratio R (= 0.5) is set to “0.5”, and when E1> E2, the duty ratio is set to D ( <0.5). Duty ratio changing unit 527 outputs the determined duty ratio to duty ratio setting unit 524. The duty ratio setting unit 524 sets the input duty ratio to the duty ratio of the flag signal fg. Instead of storing the correspondence between the target ratio R and the duty ratio, feedback control is performed so that the ratio calculated from the output voltages of the DC power supply 1′a and the DC power supply 1′b is set as the target ratio R. You may do it.

  In the third embodiment, the same effects as in the first embodiment can be obtained. Further, by changing the duty ratio of the flag signal fg according to the situation, the outputs of the DC power supplies 1'a and 1'b can follow the maximum power, respectively.

  In the first to third embodiments, the case where the inverter circuit 2 (2 ′, 2 ″) is a three-level inverter circuit has been described, but the present invention is not limited to this. The inverter circuit 2 (2 ′, 2 ″) The present invention can also be applied to multi-level inverter circuits other than three levels. Even in this case, since the PWM signal generated based on the command value signals Xu1, Xv1, and Xw1 is input, the number of switching times of the switching element can be reduced, and the switching loss can be reduced. Further, the center potential and amplitude of the change in the intermediate potential of the phase voltage output from the inverter circuit (among other possible potentials other than the negative potential “0” and the positive potential “E”) can be arbitrarily set. The potential can be controlled.

  In the said 1st thru | or 3rd embodiment, although the inverter apparatus (inverter circuit and control circuit) of the grid connection inverter system was demonstrated, it is not restricted to this. The present invention can also be applied to inverter devices of other systems.

  The inverter device according to the present invention and the grid-connected inverter system including the inverter device are not limited to the above-described embodiments. The specific configuration of each part of the inverter device according to the present invention and the grid-connected inverter system including the inverter device can be varied in design in various ways.

A Grid-connected inverter system 1, 1'a, 1'b DC power source 2, 2 ', 2 "Inverter circuit S1-S12, S1'-S6' Switching element D1-D12 Free-wheeling diode Dc1, Dc2 Clamp diode C1, C2 Voltage dividing capacitor 3 Filter circuit 4 Transformer circuit 5 Control circuit 51 Feedback control unit 52, 52 ′ Command value signal generation unit 521 First signal generation unit 522 Second signal generation unit 523 Period setting unit 524 Duty ratio setting unit 525 Flag signal generation Unit 526 Signal combination unit 53, 53 ′ PWM signal generation unit 531 First comparison unit (first pulse generation unit)
532 Second comparison unit (second pulse generation means)
533 NOR unit (third pulse generating means)
534,535 OR part B Three-phase power system

Claims (12)

A multi-level inverter circuit;
A control circuit that generates a PWM signal such that the waveform of the AC phase voltage output from the multilevel inverter circuit is a combination of the first waveform and the second waveform, and inputs the PWM signal to the multilevel inverter circuit; ,
With
In the first waveform, a one-cycle waveform is a predetermined lower limit voltage value in a period of 1/3, and a waveform of a sine wave having a phase of 0 to 2π / 3 in a subsequent period of 1/3. The waveform is shifted upward by a predetermined lower limit voltage value, and the waveform of the sine wave having a phase of π / 3 to π is shifted upward by the predetermined lower limit voltage value in the remaining 1/3 period. Is a waveform,
In the second waveform, a one-cycle waveform has a predetermined upper limit voltage value in a period of 1/3, and a waveform of a sine wave having a phase of π to 5π / 3 in a subsequent 1/3 period. The waveform is shifted upward by a predetermined upper limit voltage value, and the waveform of the sine wave in the interval of 4π / 3 to 2π in the remaining 1/3 period is shifted upward by the predetermined upper limit voltage value. Is a waveform,
An inverter device characterized by that. The control circuit includes:
A first command value signal obtained by combining the first signal and the second signal, a signal delayed in phase by 2π / 3 with respect to the first signal, and a phase of 2π with respect to the second signal A second command value signal combined with a signal delayed by / 3, a signal delayed in phase by 4π / 3 with respect to the first signal, and a phase by 4π / 3 with respect to the second signal. Command value signal generating means for generating a third command value signal in combination with the delayed signal;
PWM signal generating means for generating a PWM signal based on each command value signal;
With
In the first signal, a waveform of one cycle has a predetermined lower limit value in a period of 1/3, and a waveform of a sine wave having a phase of 0 to 2π / 3 in a subsequent period of 1/3. Is a waveform obtained by shifting the sine wave waveform in the interval from π / 3 to π upward by the predetermined lower limit value in the remaining 1/3 period. ,
In the second signal, the waveform of one cycle has a predetermined upper limit value in a period of 1/3, and the waveform of a sine wave having a phase of π to 5π / 3 in the subsequent 1/3 period is the predetermined signal. Is a waveform obtained by shifting the sine wave waveform in the interval from 4π / 3 to 2π upward by the predetermined upper limit value in the remaining 1/3 period. ,
The inverter device according to claim 1. The command value signal generating means is
Generate a flag signal that repeats high level and low level at a predetermined cycle,
Based on the flag signal, the first command value signal is generated by switching between the first signal and the second signal.
The inverter device according to claim 2. The command value signal generating means includes three line voltages that are differential signals of the three phase voltage command value signals generated to command each of the waveforms of the three-phase AC phase voltages output from the multilevel inverter circuit. The inverter device according to claim 3, wherein the first to third command value signals are generated by using the command value signal and the flag signal by the following method.
(A) The three phases are a U phase, a V phase delayed by 2π / 3 from the U phase, and a W phase delayed by 4π / 3 from the U phase. The voltage command value signals are Xu, Xv, and Xw, respectively, the line voltage command value signal obtained by subtracting Xv from Xu, Xvw, the line voltage command value signal obtained by subtracting Xw from Xv, and the line obtained by subtracting Xu from Xw The inter-voltage command value signal is Xwu.
(B1) When the flag signal is at a low level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, the first command value signal Xu1 is set to Xuv. The second command value signal Xv1 is set to “0”, and the third command value signal Xw1 is set to a negative value of Xvw.
(C1) When the flag signal is at a low level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, Xu1 is set to “0” and Xv1 is set to Xuv Let it be a negative value, and let Xw1 be Xwu.
(D1) When the flag signal is at a low level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, Xu1 is set to a negative value of Xwu, and Xv1 is set to Xvw Xw1 is set to “0”.
(E1) When the flag signal is at a low level and the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu1 is set to Xuv and Xv1 is set to “0”. , Xw1 is a negative value of Xvw.
(F1) When the flag signal is at a low level and the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu1 is set to “0” and Xv1 is set to Xuv Let it be a negative value, and let Xw1 be Xwu.
(G1) When the flag signal is at a low level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu1 is set to a negative value of Xwu, and Xv1 is set to Xvw Xw1 is set to “0”.
(B2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a positive value, Xu1 is set to a predetermined value, and Xv1 is set to the predetermined value Xuv is subtracted from Xuv, and Xw1 is the value obtained by adding Xwu to the predetermined value.
(C2) When the flag signal is at a high level, the absolute value of Xuv is larger than the absolute value of Xvw and the absolute value of Xwu, and Xuv is a negative value, a value obtained by adding Xuv to the predetermined value and Xuv Xv1 is the predetermined value, and Xw1 is a value obtained by subtracting Xvw from the predetermined value.
(D2) When the flag signal is at a high level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a positive value, a value obtained by adding Xuv to the predetermined value and Xuv Xv1 is the predetermined value, and Xw1 is a value obtained by subtracting Xvw from the predetermined value.
(E2) When the flag signal is at a high level, the absolute value of Xvw is larger than the absolute value of Xuv and the absolute value of Xwu, and Xvw is a negative value, Xu1 is a value obtained by subtracting Xwu from the predetermined value Xv1 is a value obtained by adding Xvw to the predetermined value, and Xw1 is the predetermined value.
(F2) When the flag signal is at a high level, the absolute value of Xwu is greater than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a positive value, Xu1 is obtained by subtracting Xwu from the predetermined value Xv1 is a value obtained by adding Xvw to the predetermined value, and Xw1 is the predetermined value.
(G2) When the flag signal is at a high level, the absolute value of Xwu is larger than the absolute value of Xuv and the absolute value of Xvw, and Xwu is a negative value, Xu1 is set as the predetermined value, and Xv1 is set as the predetermined value. Xuv is subtracted from the value, and Xw1 is the value obtained by adding Xwu to the predetermined value. The command value signal generating means is
A period setting unit for setting the period of the flag signal;
A duty ratio setting unit that sets a duty ratio that is a ratio of a period that is a high level with respect to the cycle of the flag signal;
The inverter apparatus of Claim 3 or 4 provided.   The inverter apparatus according to claim 5, wherein the command value signal generating unit further includes a duty ratio changing unit that changes the duty ratio set by the duty ratio setting unit.   The inverter device according to claim 2, wherein the multilevel inverter circuit is a three-level inverter circuit. The PWM signal generating means includes
First carrier signal generation means for generating a first carrier signal that fluctuates between an intermediate value between the predetermined upper limit value and the predetermined lower limit value and the predetermined upper limit value;
Second carrier signal generating means for generating a second carrier signal that fluctuates between the intermediate value and the predetermined lower limit value;
First pulse generation means for comparing each command value signal with the first carrier signal to generate a first pulse signal;
A second pulse generating means for comparing each command value signal and the second carrier signal to generate a second pulse signal;
Third pulse generating means for generating a third pulse signal based on a negative OR of the first pulse signal and the second pulse signal;
With
Outputting the first pulse signal, the second pulse signal, and the third pulse signal as PWM signals;
The inverter device according to claim 7. The first carrier signal and the second carrier signal have the same frequency.
The inverter device according to claim 8. The multi-level inverter circuit is configured such that the voltage of each phase is a negative potential of the DC power source, a positive potential, and an intermediate potential between the negative potential and the positive potential. ,
The inverter device according to claim 7.   The inverter device according to claim 1, wherein a power source that supplies power to the multilevel inverter circuit includes a solar cell.   The grid connection inverter system provided with the inverter apparatus in any one of Claims 1 thru | or 11.

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