JP2011522413A5 - - Google Patents

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Publication number
JP2011522413A5
JP2011522413A5 JP2011511634A JP2011511634A JP2011522413A5 JP 2011522413 A5 JP2011522413 A5 JP 2011522413A5 JP 2011511634 A JP2011511634 A JP 2011511634A JP 2011511634 A JP2011511634 A JP 2011511634A JP 2011522413 A5 JP2011522413 A5 JP 2011522413A5
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JP
Japan
Prior art keywords
coupled
node
transistor
drain electrode
access transistor
Prior art date
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Application number
JP2011511634A
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English (en)
Japanese (ja)
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JP2011522413A (ja
JP5646464B2 (ja
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Publication date
Priority claimed from US12/128,901 external-priority patent/US7940560B2/en
Application filed filed Critical
Publication of JP2011522413A publication Critical patent/JP2011522413A/ja
Publication of JP2011522413A5 publication Critical patent/JP2011522413A5/ja
Application granted granted Critical
Publication of JP5646464B2 publication Critical patent/JP5646464B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2011511634A 2008-05-29 2009-05-28 別々の読み出し及び書き込みアクセストランジスタを有するゲート型横型サイリスタベースランダムアクセスメモリ（ｇｌｔｒａｍ）セル並びにそれを組み込んだメモリデバイス及び集積回路 Expired - Fee Related JP5646464B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/128,901 US7940560B2 (en) 2008-05-29 2008-05-29 Memory cells, memory devices and integrated circuits incorporating the same
US12/128,901 2008-05-29
PCT/US2009/003245 WO2009148532A1 (en) 2008-05-29 2009-05-28 Gated lateral thyristor-based random access memory (gltram) cells with separate read and write access transistors, memory devices and integrated circuits incorporating the same

Publications (3)

Publication Number Publication Date
JP2011522413A JP2011522413A (ja) 2011-07-28
JP2011522413A5 true JP2011522413A5 (cg-RX-API-DMAC7.html) 2012-07-12
JP5646464B2 JP5646464B2 (ja) 2014-12-24

Family

ID=41124091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011511634A Expired - Fee Related JP5646464B2 (ja) 2008-05-29 2009-05-28 別々の読み出し及び書き込みアクセストランジスタを有するゲート型横型サイリスタベースランダムアクセスメモリ（ｇｌｔｒａｍ）セル並びにそれを組み込んだメモリデバイス及び集積回路

Country Status (7)

Country Link
US (1) US7940560B2 (cg-RX-API-DMAC7.html)
EP (1) EP2297738A1 (cg-RX-API-DMAC7.html)
JP (1) JP5646464B2 (cg-RX-API-DMAC7.html)
KR (1) KR101519573B1 (cg-RX-API-DMAC7.html)
CN (1) CN102084427B (cg-RX-API-DMAC7.html)
TW (1) TWI502586B (cg-RX-API-DMAC7.html)
WO (1) WO2009148532A1 (cg-RX-API-DMAC7.html)

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Publication number Priority date Publication date Assignee Title
JP5151370B2 (ja) * 2007-09-28 2013-02-27 ソニー株式会社 半導体装置
US8767843B2 (en) * 2008-11-10 2014-07-01 Motorola Mobility Llc Employing cell-specific and user entity-specific reference symbols in an orthogonal frequency-division multiple access
US8797794B2 (en) 2012-06-27 2014-08-05 Micron Technology, Inc. Thyristor memory and methods of operation
JP6007396B2 (ja) * 2014-02-24 2016-10-12 正仁 櫨田 サイリスターを利用したｒａｍセル
US20150333068A1 (en) * 2014-05-14 2015-11-19 Globalfoundries Singapore Pte. Ltd. Thyristor random access memory
US9899390B2 (en) * 2016-02-08 2018-02-20 Kilopass Technology, Inc. Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes
US11211330B2 (en) * 2017-05-01 2021-12-28 Advanced Micro Devices, Inc. Standard cell layout architectures and drawing styles for 5nm and beyond
CN116209253B (zh) * 2022-09-23 2024-02-20 北京超弦存储器研究院 存储单元、动态存储器、其读取方法及电子设备
CN116209252B (zh) * 2022-09-23 2024-02-23 北京超弦存储器研究院 存储单元、动态存储器、其读取方法及电子设备

Family Cites Families (22)

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Publication number Priority date Publication date Assignee Title
US3918033A (en) * 1974-11-11 1975-11-04 Ibm SCR memory cell
US6229161B1 (en) * 1998-06-05 2001-05-08 Stanford University Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
US6448122B1 (en) * 2000-06-22 2002-09-10 Koninklijke Philips Electronics N.V. Method and device structure for enhanced ESD performance
KR100376126B1 (ko) * 2000-11-14 2003-03-15 삼성전자주식회사 반도체 메모리 장치의 센싱제어회로 및 레이아웃
US6713791B2 (en) * 2001-01-26 2004-03-30 Ibm Corporation T-RAM array having a planar cell structure and method for fabricating the same
US7491586B2 (en) * 2001-03-22 2009-02-17 T-Ram Semiconductor, Inc. Semiconductor device with leakage implant and method of fabrication
US6940772B1 (en) * 2002-03-18 2005-09-06 T-Ram, Inc Reference cells for TCCT based memory cells
US7042027B2 (en) * 2002-08-30 2006-05-09 Micron Technology, Inc. Gated lateral thyristor-based random access memory cell (GLTRAM)
US6703646B1 (en) * 2002-09-24 2004-03-09 T-Ram, Inc. Thyristor with lightly-doped emitter
US7125753B1 (en) * 2002-10-01 2006-10-24 T-Ram Semiconductor, Inc. Self-aligned thin capacitively-coupled thyristor structure
US6849481B1 (en) * 2003-07-28 2005-02-01 Chartered Semiconductor Manufacturing Ltd. Thyristor-based SRAM and method for the fabrication thereof
US7195959B1 (en) * 2004-10-04 2007-03-27 T-Ram Semiconductor, Inc. Thyristor-based semiconductor device and method of fabrication
US7224002B2 (en) 2004-05-06 2007-05-29 Micron Technology, Inc. Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer
US7106620B2 (en) * 2004-12-30 2006-09-12 International Business Machines Corporation Memory cell having improved read stability
US7136296B2 (en) * 2005-02-28 2006-11-14 International Business Machines Corporation Static random access memory utilizing gated diode technology
US7286437B2 (en) * 2005-06-17 2007-10-23 International Business Machines Corporation Three dimensional twisted bitline architecture for multi-port memory
JP4481895B2 (ja) * 2005-07-15 2010-06-16 株式会社東芝 半導体記憶装置
JP2007067133A (ja) * 2005-08-31 2007-03-15 Sony Corp 半導体装置
JP2007189193A (ja) * 2005-12-15 2007-07-26 Sony Corp 半導体装置および半導体装置の製造方法
TWI449137B (zh) 2006-03-23 2014-08-11 製陶技術創新製陶工程股份公司 構件或電路用的攜帶體
JP4434252B2 (ja) * 2007-09-27 2010-03-17 ソニー株式会社 半導体装置
JP5151370B2 (ja) * 2007-09-28 2013-02-27 ソニー株式会社 半導体装置

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