CN102084427B - 具有独立的读取和写入存取晶体管的栅极横向晶闸管随机存取存储器(gltram)单元及具有该gltram的存储器器件和集成电路 - Google Patents

具有独立的读取和写入存取晶体管的栅极横向晶闸管随机存取存储器(gltram)单元及具有该gltram的存储器器件和集成电路 Download PDF

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CN102084427B
CN102084427B CN2009801209702A CN200980120970A CN102084427B CN 102084427 B CN102084427 B CN 102084427B CN 2009801209702 A CN2009801209702 A CN 2009801209702A CN 200980120970 A CN200980120970 A CN 200980120970A CN 102084427 B CN102084427 B CN 102084427B
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coupled
write
node
access transistor
read
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CN2009801209702A
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Chinese (zh)
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CN102084427A (zh
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赵炫真
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/20—Subject matter not provided for in other groups of this subclass comprising memory cells having thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/676—Combinations of only thyristors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
CN2009801209702A 2008-05-29 2009-05-28 具有独立的读取和写入存取晶体管的栅极横向晶闸管随机存取存储器(gltram)单元及具有该gltram的存储器器件和集成电路 Expired - Fee Related CN102084427B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/128,901 US7940560B2 (en) 2008-05-29 2008-05-29 Memory cells, memory devices and integrated circuits incorporating the same
US12/128,901 2008-05-29
PCT/US2009/003245 WO2009148532A1 (en) 2008-05-29 2009-05-28 Gated lateral thyristor-based random access memory (gltram) cells with separate read and write access transistors, memory devices and integrated circuits incorporating the same

Publications (2)

Publication Number Publication Date
CN102084427A CN102084427A (zh) 2011-06-01
CN102084427B true CN102084427B (zh) 2013-10-16

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CN2009801209702A Expired - Fee Related CN102084427B (zh) 2008-05-29 2009-05-28 具有独立的读取和写入存取晶体管的栅极横向晶闸管随机存取存储器(gltram)单元及具有该gltram的存储器器件和集成电路

Country Status (7)

Country Link
US (1) US7940560B2 (cg-RX-API-DMAC7.html)
EP (1) EP2297738A1 (cg-RX-API-DMAC7.html)
JP (1) JP5646464B2 (cg-RX-API-DMAC7.html)
KR (1) KR101519573B1 (cg-RX-API-DMAC7.html)
CN (1) CN102084427B (cg-RX-API-DMAC7.html)
TW (1) TWI502586B (cg-RX-API-DMAC7.html)
WO (1) WO2009148532A1 (cg-RX-API-DMAC7.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5151370B2 (ja) * 2007-09-28 2013-02-27 ソニー株式会社 半導体装置
US8767843B2 (en) * 2008-11-10 2014-07-01 Motorola Mobility Llc Employing cell-specific and user entity-specific reference symbols in an orthogonal frequency-division multiple access
US8797794B2 (en) 2012-06-27 2014-08-05 Micron Technology, Inc. Thyristor memory and methods of operation
JP6007396B2 (ja) * 2014-02-24 2016-10-12 正仁 櫨田 サイリスターを利用したｒａｍセル
US20150333068A1 (en) * 2014-05-14 2015-11-19 Globalfoundries Singapore Pte. Ltd. Thyristor random access memory
US9899390B2 (en) * 2016-02-08 2018-02-20 Kilopass Technology, Inc. Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes
US11211330B2 (en) * 2017-05-01 2021-12-28 Advanced Micro Devices, Inc. Standard cell layout architectures and drawing styles for 5nm and beyond
CN116209253B (zh) * 2022-09-23 2024-02-20 北京超弦存储器研究院 存储单元、动态存储器、其读取方法及电子设备
CN116209252B (zh) * 2022-09-23 2024-02-23 北京超弦存储器研究院 存储单元、动态存储器、其读取方法及电子设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040041212A1 (en) * 2002-08-30 2004-03-04 Arup Bhattacharyya Gated lateral thyristor-based random access memory cell (GLTRAM)
US20060198181A1 (en) * 2005-02-28 2006-09-07 International Business Machines Corporation Static random access memory utilizing gated diode technology

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3918033A (en) * 1974-11-11 1975-11-04 Ibm SCR memory cell
US6229161B1 (en) * 1998-06-05 2001-05-08 Stanford University Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches
US6448122B1 (en) * 2000-06-22 2002-09-10 Koninklijke Philips Electronics N.V. Method and device structure for enhanced ESD performance
KR100376126B1 (ko) * 2000-11-14 2003-03-15 삼성전자주식회사 반도체 메모리 장치의 센싱제어회로 및 레이아웃
US6713791B2 (en) * 2001-01-26 2004-03-30 Ibm Corporation T-RAM array having a planar cell structure and method for fabricating the same
US7491586B2 (en) * 2001-03-22 2009-02-17 T-Ram Semiconductor, Inc. Semiconductor device with leakage implant and method of fabrication
US6940772B1 (en) * 2002-03-18 2005-09-06 T-Ram, Inc Reference cells for TCCT based memory cells
US6703646B1 (en) * 2002-09-24 2004-03-09 T-Ram, Inc. Thyristor with lightly-doped emitter
US7125753B1 (en) * 2002-10-01 2006-10-24 T-Ram Semiconductor, Inc. Self-aligned thin capacitively-coupled thyristor structure
US6849481B1 (en) * 2003-07-28 2005-02-01 Chartered Semiconductor Manufacturing Ltd. Thyristor-based SRAM and method for the fabrication thereof
US7195959B1 (en) * 2004-10-04 2007-03-27 T-Ram Semiconductor, Inc. Thyristor-based semiconductor device and method of fabrication
US7224002B2 (en) 2004-05-06 2007-05-29 Micron Technology, Inc. Silicon on insulator read-write non-volatile memory comprising lateral thyristor and trapping layer
US7106620B2 (en) * 2004-12-30 2006-09-12 International Business Machines Corporation Memory cell having improved read stability
US7286437B2 (en) * 2005-06-17 2007-10-23 International Business Machines Corporation Three dimensional twisted bitline architecture for multi-port memory
JP4481895B2 (ja) * 2005-07-15 2010-06-16 株式会社東芝 半導体記憶装置
JP2007067133A (ja) * 2005-08-31 2007-03-15 Sony Corp 半導体装置
JP2007189193A (ja) * 2005-12-15 2007-07-26 Sony Corp 半導体装置および半導体装置の製造方法
TWI449137B (zh) 2006-03-23 2014-08-11 製陶技術創新製陶工程股份公司 構件或電路用的攜帶體
JP4434252B2 (ja) * 2007-09-27 2010-03-17 ソニー株式会社 半導体装置
JP5151370B2 (ja) * 2007-09-28 2013-02-27 ソニー株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040041212A1 (en) * 2002-08-30 2004-03-04 Arup Bhattacharyya Gated lateral thyristor-based random access memory cell (GLTRAM)
US20060198181A1 (en) * 2005-02-28 2006-09-07 International Business Machines Corporation Static random access memory utilizing gated diode technology

Also Published As

Publication number Publication date
US20090296463A1 (en) 2009-12-03
CN102084427A (zh) 2011-06-01
US7940560B2 (en) 2011-05-10
KR101519573B1 (ko) 2015-05-12
JP2011522413A (ja) 2011-07-28
EP2297738A1 (en) 2011-03-23
TWI502586B (zh) 2015-10-01
JP5646464B2 (ja) 2014-12-24
WO2009148532A1 (en) 2009-12-10
TW201009834A (en) 2010-03-01
KR20110031439A (ko) 2011-03-28

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