JP2011522324A - メモリデバイストレーニングのために組み込まれたプログラム可能要素 - Google Patents

メモリデバイストレーニングのために組み込まれたプログラム可能要素 Download PDF

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Publication number
JP2011522324A
JP2011522324A JP2011511640A JP2011511640A JP2011522324A JP 2011522324 A JP2011522324 A JP 2011522324A JP 2011511640 A JP2011511640 A JP 2011511640A JP 2011511640 A JP2011511640 A JP 2011511640A JP 2011522324 A JP2011522324 A JP 2011522324A
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Japan
Prior art keywords
memory device
interface
programmable element
computer program
program product
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JP2011511640A
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English (en)
Japanese (ja)
Inventor
クルーガー ウォーレン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2011522324A publication Critical patent/JP2011522324A/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4403—Processor initialisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2011511640A 2008-05-29 2009-05-29 メモリデバイストレーニングのために組み込まれたプログラム可能要素 Pending JP2011522324A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US7198908P 2008-05-29 2008-05-29
US61/071,989 2008-05-29
PCT/US2009/003276 WO2009145903A1 (en) 2008-05-29 2009-05-29 Embedded programmable component for memory device training

Publications (1)

Publication Number Publication Date
JP2011522324A true JP2011522324A (ja) 2011-07-28

Family

ID=41377437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011511640A Pending JP2011522324A (ja) 2008-05-29 2009-05-29 メモリデバイストレーニングのために組み込まれたプログラム可能要素

Country Status (6)

Country Link
US (1) US20090300278A1 (zh)
EP (1) EP2288993A4 (zh)
JP (1) JP2011522324A (zh)
KR (1) KR20110010793A (zh)
CN (1) CN102047229A (zh)
WO (1) WO2009145903A1 (zh)

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KR20120095221A (ko) 2011-02-18 2012-08-28 삼성전자주식회사 메모리 소자 및 메모리 컨트롤 유닛
US8819316B2 (en) 2011-06-21 2014-08-26 Taejin Info Tech Co., Ltd. Two-way raid controller with programmable host interface for a semiconductor storage device
US9081666B2 (en) * 2013-02-15 2015-07-14 Seagate Technology Llc Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
KR20180007374A (ko) 2016-07-12 2018-01-23 삼성전자주식회사 메모리 채널의 소프트웨어 트레이닝을 수행하는 전자 장치 및 그것의 메모리 채널 트레이닝 방법
US10002651B2 (en) * 2016-10-06 2018-06-19 SK Hynix Inc. Semiconductor devices
US10628049B2 (en) 2017-07-12 2020-04-21 Sandisk Technologies Llc Systems and methods for on-die control of memory command, timing, and/or control signals
KR102433040B1 (ko) 2017-12-12 2022-08-18 삼성전자주식회사 메모리 모듈, 메모리 시스템 및 메모리 모듈의 동작 방법

Citations (1)

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US6513103B1 (en) * 1997-10-10 2003-01-28 Rambus Inc. Method and apparatus for adjusting the performance of a synchronous memory system
US6430696B1 (en) * 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
AU2001243463A1 (en) * 2000-03-10 2001-09-24 Arc International Plc Memory interface and method of interfacing between functional entities
US7571303B2 (en) * 2002-10-16 2009-08-04 Akya (Holdings) Limited Reconfigurable integrated circuit
US7246274B2 (en) * 2004-09-10 2007-07-17 Rambus Inc. Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER)
US20060164909A1 (en) * 2005-01-24 2006-07-27 International Business Machines Corporation System, method and storage medium for providing programmable delay chains for a memory system
KR101377305B1 (ko) * 2005-06-24 2014-03-25 구글 인코포레이티드 집적 메모리 코어 및 메모리 인터페이스 회로
US7225097B2 (en) * 2005-07-28 2007-05-29 International Business Machines Corporation Methods and apparatus for memory calibration
US8121237B2 (en) * 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
US7594055B2 (en) * 2006-05-24 2009-09-22 International Business Machines Corporation Systems and methods for providing distributed technology independent memory controllers
US7661010B2 (en) * 2006-05-31 2010-02-09 Mosaid Technologies Incorporated Apparatus and method for interfacing to a memory
US20080168298A1 (en) * 2007-01-05 2008-07-10 Mark David Bellows Methods and Apparatus for Calibrating Heterogeneous Memory Interfaces
DE102007010284A1 (de) * 2007-03-02 2008-09-04 Qimonda Ag Schnittstellenvorrichtung, Schaltungsmodul, Schaltungssystem, Vorrichtung für eine Datenkommunikation und Verfahren zum Kalibrieren eines Schaltungsmoduls
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US7991573B2 (en) * 2007-12-19 2011-08-02 Qimonda Ag Integrated circuit including calibration circuit

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2007524166A (ja) * 2004-01-28 2007-08-23 ラムバス・インコーポレーテッド 構成可能な相互接続トポロジを用いたｉ／ｏ帯域幅の適応割当て

Also Published As

Publication number Publication date
EP2288993A1 (en) 2011-03-02
US20090300278A1 (en) 2009-12-03
KR20110010793A (ko) 2011-02-07
WO2009145903A1 (en) 2009-12-03
EP2288993A4 (en) 2012-05-09
CN102047229A (zh) 2011-05-04

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