JP2011507073A5 - - Google Patents

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Publication number
JP2011507073A5
JP2011507073A5 JP2010536974A JP2010536974A JP2011507073A5 JP 2011507073 A5 JP2011507073 A5 JP 2011507073A5 JP 2010536974 A JP2010536974 A JP 2010536974A JP 2010536974 A JP2010536974 A JP 2010536974A JP 2011507073 A5 JP2011507073 A5 JP 2011507073A5
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JP
Japan
Prior art keywords
way
data
read address
processor
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010536974A
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English (en)
Japanese (ja)
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JP2011507073A (ja
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Publication date
Priority claimed from US11/951,924 external-priority patent/US7809980B2/en
Application filed filed Critical
Publication of JP2011507073A publication Critical patent/JP2011507073A/ja
Publication of JP2011507073A5 publication Critical patent/JP2011507073A5/ja
Pending legal-status Critical Current

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JP2010536974A 2007-12-06 2008-11-21 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 Pending JP2011507073A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/951,924 US7809980B2 (en) 2007-12-06 2007-12-06 Error detector in a cache memory using configurable way redundancy
PCT/US2008/084261 WO2009076033A2 (en) 2007-12-06 2008-11-21 Error detector in a cache memory using configurable way redundancy

Publications (2)

Publication Number Publication Date
JP2011507073A JP2011507073A (ja) 2011-03-03
JP2011507073A5 true JP2011507073A5 (enExample) 2012-01-19

Family

ID=40722926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010536974A Pending JP2011507073A (ja) 2007-12-06 2008-11-21 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器

Country Status (5)

Country Link
US (1) US7809980B2 (enExample)
EP (1) EP2240856B1 (enExample)
JP (1) JP2011507073A (enExample)
TW (1) TWI437436B (enExample)
WO (1) WO2009076033A2 (enExample)

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US9400711B2 (en) 2014-04-14 2016-07-26 Freescale Semiconductor, Inc. Content addressable memory with error detection
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