JP2011507073A - 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 - Google Patents

設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 Download PDF

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JP2011507073A
JP2011507073A JP2010536974A JP2010536974A JP2011507073A JP 2011507073 A JP2011507073 A JP 2011507073A JP 2010536974 A JP2010536974 A JP 2010536974A JP 2010536974 A JP2010536974 A JP 2010536974A JP 2011507073 A JP2011507073 A JP 2011507073A
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Prior art keywords
way
data
cache
processing system
data processing
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Japanese (ja)
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JP2011507073A5 (enExample
Inventor
ラファエリ、ジェホダ
ボーゲンベルガー、フロリアン
ビー. エイファート、ジェームズ
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NXP USA Inc
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NXP USA Inc
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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/126Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60Details of cache memory
    • G06F2212/601Reconfiguration of cache memory

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
JP2010536974A 2007-12-06 2008-11-21 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 Pending JP2011507073A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/951,924 US7809980B2 (en) 2007-12-06 2007-12-06 Error detector in a cache memory using configurable way redundancy
PCT/US2008/084261 WO2009076033A2 (en) 2007-12-06 2008-11-21 Error detector in a cache memory using configurable way redundancy

Publications (2)

Publication Number Publication Date
JP2011507073A true JP2011507073A (ja) 2011-03-03
JP2011507073A5 JP2011507073A5 (enExample) 2012-01-19

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JP2010536974A Pending JP2011507073A (ja) 2007-12-06 2008-11-21 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器

Country Status (5)

Country Link
US (1) US7809980B2 (enExample)
EP (1) EP2240856B1 (enExample)
JP (1) JP2011507073A (enExample)
TW (1) TWI437436B (enExample)
WO (1) WO2009076033A2 (enExample)

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JP2013120426A (ja) * 2011-12-06 2013-06-17 Hitachi Ltd ソフトエラー耐性調整機能を備えた電子システム装置及びソフトエラー耐性調整方法

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US8356239B2 (en) * 2008-09-05 2013-01-15 Freescale Semiconductor, Inc. Selective cache way mirroring
US9753858B2 (en) 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
US20130346695A1 (en) * 2012-06-25 2013-12-26 Advanced Micro Devices, Inc. Integrated circuit with high reliability cache controller and method therefor
US8984368B2 (en) 2012-10-11 2015-03-17 Advanced Micro Devices, Inc. High reliability memory controller
US9400711B2 (en) 2014-04-14 2016-07-26 Freescale Semiconductor, Inc. Content addressable memory with error detection
US10474526B2 (en) * 2016-09-30 2019-11-12 Intel Corporation System and method for granular in-field cache repair

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JPH03122739A (ja) * 1989-10-05 1991-05-24 Koufu Nippon Denki Kk キャッシュメモリ
JPH04243446A (ja) * 1991-01-17 1992-08-31 Koufu Nippon Denki Kk キャッシュ登録制御装置
JPH0644799A (ja) * 1992-04-30 1994-02-18 Internatl Business Mach Corp <Ibm> Pウェイ・セット・アソシエティブ・キャッシュ・メモリ構造
JPH07110788A (ja) * 1993-10-14 1995-04-25 Fujitsu Ltd ディスクキャッシュ装置
JP2001075865A (ja) * 1999-09-02 2001-03-23 Fujitsu Ltd キャッシュtag制御方法及びこの制御方法を用いた情報処理装置
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013120426A (ja) * 2011-12-06 2013-06-17 Hitachi Ltd ソフトエラー耐性調整機能を備えた電子システム装置及びソフトエラー耐性調整方法

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EP2240856A4 (en) 2012-08-08
US20090150720A1 (en) 2009-06-11
TW200931261A (en) 2009-07-16
EP2240856A2 (en) 2010-10-20
US7809980B2 (en) 2010-10-05
EP2240856B1 (en) 2019-04-17
WO2009076033A2 (en) 2009-06-18
TWI437436B (zh) 2014-05-11
WO2009076033A3 (en) 2009-08-27

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