JP2011507073A - 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 - Google Patents
設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 Download PDFInfo
- Publication number
- JP2011507073A JP2011507073A JP2010536974A JP2010536974A JP2011507073A JP 2011507073 A JP2011507073 A JP 2011507073A JP 2010536974 A JP2010536974 A JP 2010536974A JP 2010536974 A JP2010536974 A JP 2010536974A JP 2011507073 A JP2011507073 A JP 2011507073A
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- JP
- Japan
- Prior art keywords
- way
- data
- cache
- processing system
- data processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/601—Reconfiguration of cache memory
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/951,924 US7809980B2 (en) | 2007-12-06 | 2007-12-06 | Error detector in a cache memory using configurable way redundancy |
| PCT/US2008/084261 WO2009076033A2 (en) | 2007-12-06 | 2008-11-21 | Error detector in a cache memory using configurable way redundancy |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2011507073A true JP2011507073A (ja) | 2011-03-03 |
| JP2011507073A5 JP2011507073A5 (enExample) | 2012-01-19 |
Family
ID=40722926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010536974A Pending JP2011507073A (ja) | 2007-12-06 | 2008-11-21 | 設定可能なウェイの冗長を用いるキャッシュメモリのエラー検出器 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7809980B2 (enExample) |
| EP (1) | EP2240856B1 (enExample) |
| JP (1) | JP2011507073A (enExample) |
| TW (1) | TWI437436B (enExample) |
| WO (1) | WO2009076033A2 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013120426A (ja) * | 2011-12-06 | 2013-06-17 | Hitachi Ltd | ソフトエラー耐性調整機能を備えた電子システム装置及びソフトエラー耐性調整方法 |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8713254B1 (en) * | 2008-03-31 | 2014-04-29 | Emc Corporation | System and method for improving cache efficiency |
| US8291305B2 (en) * | 2008-09-05 | 2012-10-16 | Freescale Semiconductor, Inc. | Error detection schemes for a cache in a data processing system |
| US8356239B2 (en) * | 2008-09-05 | 2013-01-15 | Freescale Semiconductor, Inc. | Selective cache way mirroring |
| US9753858B2 (en) | 2011-11-30 | 2017-09-05 | Advanced Micro Devices, Inc. | DRAM cache with tags and data jointly stored in physical rows |
| US20130346695A1 (en) * | 2012-06-25 | 2013-12-26 | Advanced Micro Devices, Inc. | Integrated circuit with high reliability cache controller and method therefor |
| US8984368B2 (en) | 2012-10-11 | 2015-03-17 | Advanced Micro Devices, Inc. | High reliability memory controller |
| US9400711B2 (en) | 2014-04-14 | 2016-07-26 | Freescale Semiconductor, Inc. | Content addressable memory with error detection |
| US10474526B2 (en) * | 2016-09-30 | 2019-11-12 | Intel Corporation | System and method for granular in-field cache repair |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03122739A (ja) * | 1989-10-05 | 1991-05-24 | Koufu Nippon Denki Kk | キャッシュメモリ |
| JPH04243446A (ja) * | 1991-01-17 | 1992-08-31 | Koufu Nippon Denki Kk | キャッシュ登録制御装置 |
| JPH0644799A (ja) * | 1992-04-30 | 1994-02-18 | Internatl Business Mach Corp <Ibm> | Pウェイ・セット・アソシエティブ・キャッシュ・メモリ構造 |
| JPH07110788A (ja) * | 1993-10-14 | 1995-04-25 | Fujitsu Ltd | ディスクキャッシュ装置 |
| JP2001075865A (ja) * | 1999-09-02 | 2001-03-23 | Fujitsu Ltd | キャッシュtag制御方法及びこの制御方法を用いた情報処理装置 |
| US20030018936A1 (en) * | 2001-07-17 | 2003-01-23 | Bull Nh Information Systems Inc. | High integrity cache directory |
| JP2007041932A (ja) * | 2005-08-04 | 2007-02-15 | Fujitsu Ltd | キャッシュメモリ装置、半導体集積回路およびキャッシュ制御方法 |
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| CA2003338A1 (en) * | 1987-11-09 | 1990-06-09 | Richard W. Cutts, Jr. | Synchronization of fault-tolerant computer system having multiple processors |
| AU616213B2 (en) * | 1987-11-09 | 1991-10-24 | Tandem Computers Incorporated | Method and apparatus for synchronizing a plurality of processors |
| US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
| AU625293B2 (en) * | 1988-12-09 | 1992-07-09 | Tandem Computers Incorporated | Synchronization of fault-tolerant computer system having multiple processors |
| EP0401994A3 (en) | 1989-06-05 | 1991-10-23 | Hewlett-Packard Company | Method of implementing error corrected memory |
| US5295258A (en) * | 1989-12-22 | 1994-03-15 | Tandem Computers Incorporated | Fault-tolerant computer system with online recovery and reintegration of redundant components |
| US5313585A (en) * | 1991-12-17 | 1994-05-17 | Jeffries Kenneth L | Disk drive array with request fragmentation |
| US5473761A (en) * | 1991-12-17 | 1995-12-05 | Dell Usa, L.P. | Controller for receiving transfer requests for noncontiguous sectors and reading those sectors as a continuous block by interspersing no operation requests between transfer requests |
| US5506977A (en) * | 1991-12-17 | 1996-04-09 | Dell Usa, L.P. | Method and controller for minimizing reads during partial stripe write operations to a disk drive |
| US5313626A (en) * | 1991-12-17 | 1994-05-17 | Jones Craig S | Disk drive array with efficient background rebuilding |
| US5483641A (en) * | 1991-12-17 | 1996-01-09 | Dell Usa, L.P. | System for scheduling readahead operations if new request is within a proximity of N last read requests wherein N is dependent on independent activities |
| US5530960A (en) * | 1991-12-17 | 1996-06-25 | Dell Usa, L.P. | Disk drive controller accepting first commands for accessing composite drives and second commands for individual diagnostic drive control wherein commands are transparent to each other |
| US5974544A (en) * | 1991-12-17 | 1999-10-26 | Dell Usa, L.P. | Method and controller for defect tracking in a redundant array |
| DE69421379T2 (de) * | 1994-03-31 | 2000-05-11 | Stmicroelectronics, Inc. | Wiederverwendbarer Mehrwegsatz assoziativer Cache-Speicher |
| US6412051B1 (en) * | 1996-11-27 | 2002-06-25 | International Business Machines Corp. | System and method for controlling a memory array in an information handling system |
| US5883904A (en) * | 1997-04-14 | 1999-03-16 | International Business Machines Corporation | Method for recoverability via redundant cache arrays |
| JPH10334695A (ja) * | 1997-05-27 | 1998-12-18 | Toshiba Corp | キャッシュメモリ及び情報処理システム |
| US6625756B1 (en) * | 1997-12-19 | 2003-09-23 | Intel Corporation | Replay mechanism for soft error recovery |
| US6480975B1 (en) * | 1998-02-17 | 2002-11-12 | International Business Machines Corporation | ECC mechanism for set associative cache array |
| US6708294B1 (en) * | 1999-09-08 | 2004-03-16 | Fujitsu Limited | Cache memory apparatus and computer readable recording medium on which a program for controlling a cache memory is recorded |
| US6615366B1 (en) * | 1999-12-21 | 2003-09-02 | Intel Corporation | Microprocessor with dual execution core operable in high reliability mode |
| US6625749B1 (en) * | 1999-12-21 | 2003-09-23 | Intel Corporation | Firmware mechanism for correcting soft errors |
| US7010575B1 (en) * | 2000-03-31 | 2006-03-07 | Emc Corporation | Data storage system having separate data transfer section and message network having bus arbitration |
| US6668308B2 (en) * | 2000-06-10 | 2003-12-23 | Hewlett-Packard Development Company, L.P. | Scalable architecture based on single-chip multiprocessing |
| US6671822B1 (en) * | 2000-08-31 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache |
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| US6901468B1 (en) * | 2000-09-27 | 2005-05-31 | Emc Corporation | Data storage system having separate data transfer section and message network having bus arbitration |
| US6684268B1 (en) * | 2000-09-27 | 2004-01-27 | Emc Corporation | Data storage system having separate data transfer section and message network having CPU bus selector |
| US6609164B1 (en) * | 2000-10-05 | 2003-08-19 | Emc Corporation | Data storage system having separate data transfer section and message network with data pipe DMA |
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| GB2378277B (en) * | 2001-07-31 | 2003-06-25 | Sun Microsystems Inc | Multiple address translations |
| KR100481849B1 (ko) * | 2001-12-04 | 2005-04-11 | 삼성전자주식회사 | 용량 변경이 가능한 캐쉬 메모리 및 이를 구비한 프로세서칩 |
| JP3953903B2 (ja) * | 2002-06-28 | 2007-08-08 | 富士通株式会社 | キャッシュメモリ装置、及び、参照履歴のビット誤り検出方法 |
| US7181578B1 (en) * | 2002-09-12 | 2007-02-20 | Copan Systems, Inc. | Method and apparatus for efficient scalable storage management |
| US7278034B2 (en) * | 2002-12-02 | 2007-10-02 | Silverbrook Research Pty Ltd | Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor |
| CN1846278B (zh) * | 2003-09-04 | 2010-04-28 | Nxp股份有限公司 | 集成电路和高速缓冲存储器的重新映射方法 |
| US7502887B2 (en) * | 2003-11-12 | 2009-03-10 | Panasonic Corporation | N-way set associative cache memory and control method thereof |
| US7949841B2 (en) | 2006-12-08 | 2011-05-24 | Microsoft Corporation | Protection of critical memory using replication |
-
2007
- 2007-12-06 US US11/951,924 patent/US7809980B2/en active Active
-
2008
- 2008-11-21 WO PCT/US2008/084261 patent/WO2009076033A2/en not_active Ceased
- 2008-11-21 EP EP08858814.0A patent/EP2240856B1/en active Active
- 2008-11-21 JP JP2010536974A patent/JP2011507073A/ja active Pending
- 2008-12-05 TW TW097147540A patent/TWI437436B/zh active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03122739A (ja) * | 1989-10-05 | 1991-05-24 | Koufu Nippon Denki Kk | キャッシュメモリ |
| JPH04243446A (ja) * | 1991-01-17 | 1992-08-31 | Koufu Nippon Denki Kk | キャッシュ登録制御装置 |
| JPH0644799A (ja) * | 1992-04-30 | 1994-02-18 | Internatl Business Mach Corp <Ibm> | Pウェイ・セット・アソシエティブ・キャッシュ・メモリ構造 |
| JPH07110788A (ja) * | 1993-10-14 | 1995-04-25 | Fujitsu Ltd | ディスクキャッシュ装置 |
| JP2001075865A (ja) * | 1999-09-02 | 2001-03-23 | Fujitsu Ltd | キャッシュtag制御方法及びこの制御方法を用いた情報処理装置 |
| US20030018936A1 (en) * | 2001-07-17 | 2003-01-23 | Bull Nh Information Systems Inc. | High integrity cache directory |
| JP2007041932A (ja) * | 2005-08-04 | 2007-02-15 | Fujitsu Ltd | キャッシュメモリ装置、半導体集積回路およびキャッシュ制御方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013120426A (ja) * | 2011-12-06 | 2013-06-17 | Hitachi Ltd | ソフトエラー耐性調整機能を備えた電子システム装置及びソフトエラー耐性調整方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP2240856A4 (en) | 2012-08-08 |
| US20090150720A1 (en) | 2009-06-11 |
| TW200931261A (en) | 2009-07-16 |
| EP2240856A2 (en) | 2010-10-20 |
| US7809980B2 (en) | 2010-10-05 |
| EP2240856B1 (en) | 2019-04-17 |
| WO2009076033A2 (en) | 2009-06-18 |
| TWI437436B (zh) | 2014-05-11 |
| WO2009076033A3 (en) | 2009-08-27 |
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