JP2011228650A - 半導体基板の作製方法及び半導体装置の作製方法 - Google Patents

半導体基板の作製方法及び半導体装置の作製方法 Download PDF

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Publication number
JP2011228650A
JP2011228650A JP2011065142A JP2011065142A JP2011228650A JP 2011228650 A JP2011228650 A JP 2011228650A JP 2011065142 A JP2011065142 A JP 2011065142A JP 2011065142 A JP2011065142 A JP 2011065142A JP 2011228650 A JP2011228650 A JP 2011228650A
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Prior art keywords
single crystal
semiconductor substrate
crystal semiconductor
substrate
insulating layer
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JP2011065142A
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English (en)
Japanese (ja)
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JP2011228650A5 (https=
Inventor
Keiichi Sekiguchi
慶一 関口
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2011065142A priority Critical patent/JP2011228650A/ja
Publication of JP2011228650A publication Critical patent/JP2011228650A/ja
Publication of JP2011228650A5 publication Critical patent/JP2011228650A5/ja
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Thin Film Transistor (AREA)
JP2011065142A 2010-03-31 2011-03-24 半導体基板の作製方法及び半導体装置の作製方法 Withdrawn JP2011228650A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011065142A JP2011228650A (ja) 2010-03-31 2011-03-24 半導体基板の作製方法及び半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010083832 2010-03-31
JP2010083832 2010-03-31
JP2011065142A JP2011228650A (ja) 2010-03-31 2011-03-24 半導体基板の作製方法及び半導体装置の作製方法

Publications (2)

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JP2011228650A true JP2011228650A (ja) 2011-11-10
JP2011228650A5 JP2011228650A5 (https=) 2014-03-13

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US (1) US8445358B2 (https=)
JP (1) JP2011228650A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014011272A (ja) * 2012-06-28 2014-01-20 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法
KR101873203B1 (ko) * 2011-12-15 2018-07-03 신에쯔 한도타이 가부시키가이샤 Soi 웨이퍼의 제조방법

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2988516B1 (fr) * 2012-03-23 2014-03-07 Soitec Silicon On Insulator Procede d'implantation de fragilisation de substrats ameliore

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107017A (ja) * 1986-06-10 1988-05-12 Toshiba Corp 半導体装置の製造方法
JPH09260301A (ja) * 1996-03-26 1997-10-03 Sony Corp イオン注入方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
WO2001093334A1 (en) * 2000-05-30 2001-12-06 Shin-Etsu Handotai Co.,Ltd. Method for producing bonded wafer and bonded wafer

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5358879A (en) 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
US6773971B1 (en) 1994-07-14 2004-08-10 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having lightly-doped drain (LDD) regions
KR0132490B1 (ko) 1994-07-21 1998-04-16 문정환 박막트랜지스터 제조방법
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
JP2000294515A (ja) 1999-04-09 2000-10-20 Seiko Epson Corp イオン注入装置及びイオン注入方法
US7365361B2 (en) 2003-07-23 2008-04-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107017A (ja) * 1986-06-10 1988-05-12 Toshiba Corp 半導体装置の製造方法
JPH09260301A (ja) * 1996-03-26 1997-10-03 Sony Corp イオン注入方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
WO2001093334A1 (en) * 2000-05-30 2001-12-06 Shin-Etsu Handotai Co.,Ltd. Method for producing bonded wafer and bonded wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101873203B1 (ko) * 2011-12-15 2018-07-03 신에쯔 한도타이 가부시키가이샤 Soi 웨이퍼의 제조방법
JP2014011272A (ja) * 2012-06-28 2014-01-20 Shin Etsu Handotai Co Ltd 貼り合わせウェーハの製造方法

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US8445358B2 (en) 2013-05-21
US20110244653A1 (en) 2011-10-06

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