JP2011210771A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2011210771A JP2011210771A JP2010074442A JP2010074442A JP2011210771A JP 2011210771 A JP2011210771 A JP 2011210771A JP 2010074442 A JP2010074442 A JP 2010074442A JP 2010074442 A JP2010074442 A JP 2010074442A JP 2011210771 A JP2011210771 A JP 2011210771A
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- H01L2224/481—Disposition
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- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H01L2924/11—Device type
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Abstract
【解決手段】導電パターン付絶縁基板1に複数のIGBTチップ6が複数搭載されたモジュールにおいて、IGBTチップ6の表側のエミッタ電極7と導電パターン4とを接続するワイヤ13に環状磁性体12を挿入することで、スイッチング時にゲート電圧に重畳される高周波ノイズを抑制することができる。
【選択図】 図1
Description
まず、導電パターン付絶縁基板1の導電パターン4にIGBTチップ6のコレクタ電極とFWDチップ9のカソード電極を半田5を介して固着する。また、予め銅ブロック11に環状磁性体12を嵌合しておき、導電パターン4に半田5を介して銅ブロック11を固着する。ここで、環状磁性体12は、減衰したい高周波ノイズ、すなわち主電流の経路からゲート信号の回路への伝播を抑制したい高周波ノイズの周波数帯に応じてその材料を選択すればよい。この環状磁性体12は、例えば、パーマロイコアやフェライトコアである。
図3は、図1の半導体装置の等価回路である。3個のIGBT6(図1のIGBTチップと同一符号を付す)は並列接続され、それぞれのIGBT6にFWD9(図1のFWDチップと同一符号を付す)が逆並列に接続している。それぞれのIGBT6のエミッタに接続する配線には環状磁性体12が設置されている。
図4の試験回路において、IGBTをオンさせ、負荷のコイル(L負荷)に電流を流し、その後でIGBTをオフさせる。すると、コイルに流れている電流はFWDを通して還流電流となってFWDとコイルを循環する。つぎに、IGBTをオンさせると、FWDに流れる電流は減少し、逆回復電流が流れてFWDに流れる電流は零となり、還流電流はIGBTとコイルを通して流れるようになる。尚、点線で示したFWDはこの試験では利用しない。
ロック11とは絶縁されている。例えば、巻線15を環状磁性体12に予め巻き回しておき、その後銅ブロック11を嵌め込めばよい。この巻線15は全ての環状磁性体12に設けて各IGBTチップ6に流れる主電流を検出するようにした場合や代表して1個の環状磁性体12に設けてモジュールに流れる主電流を検出するようにした場合がある。この巻線15は電流センス部となる。図7のように、巻線15の両端を端子14へ接続して外部へ導出すればよい。
図1との違いは、IGBTチップ6のみ導電パターン付絶縁基板1に固着されている点である。この場合も環状磁性体12を設けることで、IGBTチップ6のスイッチング時にゲート電圧波形に重畳される高周波ノイズを抑制できる。
あるいは、IGBT6とFWD9の逆並列回路を直列に接続して、インバータや整流回路などの電力変換装置の1アームを構成した半導体装置に適用してもよい。
2 導電膜
3 絶縁基板
4 導電パターン
5 半田
6 IGBTチップ/IGBT
7 エミッタ電極
8 ゲート電極パッド
9 FWDチップ/FWD
10 アノード電極
11 銅ブロック
12 環状磁性体
13、a ワイヤ
14 配線導体
15 巻線
Claims (5)
- 導電パターン付絶縁基板と、該基板に裏側が固着するスイッチング素子からなる複数の半導体チップと、該半導体チップの表側の主電極と前記導電パターンとの間を結ぶ配線と、該配線が貫通する環状磁性体とを具備することを特徴とする半導体装置。
- 導電パターン付絶縁基板と、該基板に裏側が固着するスイッチング素子からなる複数の半導体チップと、前記導電パターンに固着する導体ブロックと、該導体ブロックを取り囲んで配置される環状磁性体と、前記半導体チップの表側の主電極と一方の端が接続し、他方の端が前記導体ブロックに接続するボンディングワイヤと、を具備することを特徴とする半導体装置。
- 前記スイッチング素子にダイオードが逆並列接続することを特徴とする請求項1または2に記載の半導体装置。
- 少なくとも前記スイッチング素子に流れる主電流を検出するために前記環状磁性体に1ターン以上の巻線を設け電流センス部とすることを特徴とする請求項1〜3のいずれか一項に記載の半導体装置。
- 前記環状磁性体が、パーマロイコアもしくはフェライトコアであることを特徴とする請求項1〜4のいずれか一項に記載の半導体装置。
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8823053B2 (en) | 2012-09-20 | 2014-09-02 | Kabushiki Kaisha Toshiba | Semiconductor device including a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency |
JP2014179547A (ja) * | 2013-03-15 | 2014-09-25 | Toshiba Corp | 半導体モジュール及びその製造方法 |
WO2017071976A1 (en) * | 2015-10-29 | 2017-05-04 | Abb Schweiz Ag | Semiconductor module |
US10032736B2 (en) | 2013-09-24 | 2018-07-24 | Renesas Electronics Corporation | Semiconductor device |
CN111987091A (zh) * | 2019-05-21 | 2020-11-24 | 三菱电机株式会社 | 半导体装置 |
DE102021126682A1 (de) | 2021-10-14 | 2023-04-20 | Bayerische Motoren Werke Aktiengesellschaft | Messaufbau für ein Leistungsmodul |
JP7447979B2 (ja) | 2019-02-18 | 2024-03-12 | 富士電機株式会社 | 半導体装置 |
Citations (4)
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---|---|---|---|---|
JPH04109639A (ja) * | 1990-08-30 | 1992-04-10 | Fujitsu Ltd | 半導体装置 |
JPH0661293A (ja) * | 1992-08-11 | 1994-03-04 | Nippon Steel Corp | 半導体装置 |
JP2000171491A (ja) * | 1998-12-03 | 2000-06-23 | Mitsubishi Electric Corp | パワー半導体モジュール |
JP2001185679A (ja) * | 1999-12-27 | 2001-07-06 | Mitsubishi Electric Corp | 半導体スイッチ装置 |
-
2010
- 2010-03-29 JP JP2010074442A patent/JP5293666B2/ja not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04109639A (ja) * | 1990-08-30 | 1992-04-10 | Fujitsu Ltd | 半導体装置 |
JPH0661293A (ja) * | 1992-08-11 | 1994-03-04 | Nippon Steel Corp | 半導体装置 |
JP2000171491A (ja) * | 1998-12-03 | 2000-06-23 | Mitsubishi Electric Corp | パワー半導体モジュール |
JP2001185679A (ja) * | 1999-12-27 | 2001-07-06 | Mitsubishi Electric Corp | 半導体スイッチ装置 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8823053B2 (en) | 2012-09-20 | 2014-09-02 | Kabushiki Kaisha Toshiba | Semiconductor device including a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency |
JP2014179547A (ja) * | 2013-03-15 | 2014-09-25 | Toshiba Corp | 半導体モジュール及びその製造方法 |
US10032736B2 (en) | 2013-09-24 | 2018-07-24 | Renesas Electronics Corporation | Semiconductor device |
WO2017071976A1 (en) * | 2015-10-29 | 2017-05-04 | Abb Schweiz Ag | Semiconductor module |
CN108475668A (zh) * | 2015-10-29 | 2018-08-31 | Abb瑞士股份有限公司 | 半导体模块 |
US10276552B2 (en) | 2015-10-29 | 2019-04-30 | Abb Schweiz Ag | Semiconductor module |
CN108475668B (zh) * | 2015-10-29 | 2019-09-27 | Abb瑞士股份有限公司 | 半导体模块 |
JP7447979B2 (ja) | 2019-02-18 | 2024-03-12 | 富士電機株式会社 | 半導体装置 |
CN111987091A (zh) * | 2019-05-21 | 2020-11-24 | 三菱电机株式会社 | 半导体装置 |
DE102021126682A1 (de) | 2021-10-14 | 2023-04-20 | Bayerische Motoren Werke Aktiengesellschaft | Messaufbau für ein Leistungsmodul |
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Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
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