JP2011129764A - Flip-chip light-emitting diode and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-chip light-emitting diode that is improved in yield and connection reliability by suppressing breaking of an electrode. <P>SOLUTION: The flip-chip light-emitting diode includes a semiconductor substrate 3, a compound semiconductor layer 2 of ≥3 μm in thickness, a first electrode 4 provided on a surface side of the compound semiconductor layer 2, a second electrode 5 provided in ohmic contact with a semiconductor layer 8 of a second conductivity type exposed by removing a part of the compound semiconductor layer 2, and an inter-electrode height adjustment portion 6 provided at a part of a surface of the semiconductor layer 8 of the second conductivity type exposed by removing the part of the compound semiconductor layer 2, wherein the second electrode 5 is formed continuously to the semiconductor layer 8 of the second conductivity type, and a side face 6a and an upper surface 6b of the inter-electrode height adjustment portion 6. The height of the first electrode 4 and the height of the second electrode 5 are substantially equal to each other, and the side face 6a of the inter-electrode height adjustment portion 6 is an inclined surface. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a flip-chip type light emitting diode and a manufacturing method thereof.

Formed as a light-emitting diode (LED, hereinafter also referred to as LED) that emits light from the green band to the red band by vapor-phase growth on an n-type or p-type gallium arsenide (GaAs) single crystal substrate An LED having a light emitting layer of an aluminum phosphide / gallium / indium mixed crystal (composition formula (Al _X Ga _1-X ) _Y In _1-YP : 0 ≦ X ≦ 1, 0 <Y ≦ 1) is known. (For example, refer nonpatent literature 1).

  In an LED in which a laminated structure is formed on a GaAs substrate by vapor phase epitaxy, the GaAs substrate is opaque to the emission wavelength, so that only light emitted from the upper surface of the LED is emitted from the light emitting layer. There was a problem that the light extraction efficiency to the outside was low because it could not be used.

Therefore, after bonding a transparent substrate with respect to the emission wavelength to the laminated structure formed on the GaAs substrate, the GaAs substrate used for vapor phase growth of the laminated structure is removed to manufacture an LED. A method has been proposed. In the LED obtained by this method, a substrate transparent to the emission wavelength is bonded, so that light can be emitted not only from the upper surface of the LED but also from the side surface and the lower surface, and excellent light extraction efficiency can be obtained. .
As a method for manufacturing such an LED, for example, a semiconductor substrate transparent to an emission wavelength such as GaP, zinc selenide (ZnSe), or silicon carbide (SiC) is bonded to a laminated structure including a light emitting layer. Techniques for manufacturing LEDs are known (for example, see Patent Documents 1 and 2).
Also disclosed is a technique for manufacturing an LED by bonding a GaP substrate transparent to the emission wavelength to a laminated structure via a light-transmitting conductive thin film such as indium / tin composite oxide film (ITO) (for example, And Patent Document 3).

  By the way, in an LED in which a laminated structure including a light emitting layer and a substrate transparent to the emission wavelength are joined, an electrode is provided on the surface opposite to the joint surface of the laminated structure with the transparent substrate. It is common. When the LED is mounted on the substrate, the transparent substrate side is mounted on the substrate with the transparent substrate side facing down, and the surface on which the electrode of the laminated structure is provided faces upward (face up). Wire bonding mounting in which the formed wiring is connected with a gold wire or the like can be applied.

  In contrast, in an LED in which a laminated structure including a light emitting layer and a substrate transparent to the emission wavelength are bonded, light can be emitted also from the transparent substrate side, so the transparent substrate side faces upward. In addition, flip chip mounting in which the laminated structure side is faced down (face down) and the LED electrode and the wiring on the substrate are directly connected via a gold bump or the like can be applied. As a result, it is possible to cope with downsizing of a package on which an LED is mounted.

  However, when mounting the LED face down on the substrate, the heights of the p-side and n-side electrodes provided on the same surface side of the laminated structure are not the same height from the surface of the substrate. Can not be bonded with the same pressure, causing problems of bonding failure and a decrease in bonding reliability.

  Therefore, Patent Documents 4 and 5 include LEDs in which the first conductivity type side electrode and the second conductivity type side electrode provided on the same surface side of the laminated structure have the same height from the surface of the substrate. It is disclosed. Specifically, as shown in FIG. 11, the LED 101 is connected to a substrate 103, a semiconductor laminated portion 102 connected to the substrate 103, and a first conductivity type layer on the surface side of the semiconductor laminated portion 102. A first conductivity type electrode 104 provided by being connected to a second conductivity type layer 108 exposed by removing a part of the semiconductor stacked portion 102 by etching, It has. Then, the second conductivity type electrode 105 is continuously formed on the exposed second conductivity type layer 108 and the portion 106 where the semiconductor stacked portion 102 remains without being etched, so that the first conductivity type side is formed. The second conductivity type side electrodes 104 and 105 are formed so as to have substantially the same height from the substrate 103. As a result, when the LED is mounted face-up on the substrate, both electrodes can be bonded with the same pressure, so that bonding failure does not occur and bonding reliability is improved. It is said that a semiconductor laser having a high characteristic can be obtained without causing an inclination when bonded.

Japanese Patent No. 3230638 JP 2001-244499 A Japanese Patent No. 2588849 Japanese Patent Laid-Open No. 10-223930 JP 2006-135313 A

Y. Hosokawa, “Journal of Crystal Growth” (Netherlands), 2000, Vol. 221, p. 652-656

  However, the LED disclosed in Patent Document 4 is gallium nitride (GaN). In the case of an LED, the film thickness of each layer required to obtain preferable LED light emission characteristics varies depending on the characteristics of the material of the light emitting layer used. Since the gallium nitride LED has a thin p-layer and light-emitting layer, the step of the laminated structure 102 provided to make the heights of the p-side and n-side electrodes equal is about 2 μm at most. On the other hand, since a step of about 5 μm is required for high-brightness aluminum phosphide / gallium / indium mixed crystal (AlGaInP), if the LED structure disclosed in Patent Document 4 is applied as it is, the size of the step becomes small. Due to the difference, it is difficult to form the electrode so as to cover the side surface of the step, and there is a problem that the electrode is frequently disconnected, resulting in a decrease in yield and reliability.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flip-chip light-emitting diode capable of suppressing the disconnection of electrodes and improving the yield and connection reliability. In particular, the present invention provides a light emitting diode having an aluminum phosphide / gallium / indium mixed crystal layer as a light emitting layer and a method for manufacturing the same.

That is, the present invention relates to the following.
[1] a substrate that is transparent to light emitted from the light emitting unit;
A compound semiconductor layer having a thickness of 3 μm or more having a light emitting portion of a pn junction structure made of AlGaInP or AlGaAs, which is bonded to the substrate;
A first electrode provided in ohmic contact with a first conductivity type semiconductor layer on a surface side of the compound semiconductor layer;
A second electrode provided in ohmic contact with a semiconductor layer of a second conductivity type exposed by removing a part of the compound semiconductor layer;
An inter-electrode height adjusting part provided on a part of the surface of the second conductivity type semiconductor layer exposed by removing a part of the compound semiconductor layer,
The second electrode is continuously formed on a second conductive type semiconductor layer exposed by removing a part of the compound semiconductor layer, and a side surface and an upper surface of the inter-electrode height adjusting unit, A flip-chip light emitting diode in which the height of the first electrode and the height of the second electrode are substantially the same,
A flip-chip type light emitting diode, wherein a side surface of the inter-electrode height adjusting portion is an inclined surface.
[2] The flip-chip type light emitting device according to [1], wherein the inter-electrode height adjusting part is a part of the compound semiconductor layer remaining when a part of the compound semiconductor layer is removed. diode.
[3] The cross section of the height adjustment portion between the electrodes in a direction perpendicular to the surface of the substrate is a tapered shape in which the width of the upper surface is narrower than the width of the bottom surface. Flip chip type light emitting diode.
[4] The cross-sectional shape in the vertical direction with respect to the surface of the substrate of the inter-electrode height adjusting portion is a stepped shape in which the width of the upper surface is narrower than the width of the bottom surface. Flip chip type light emitting diode.
[5] The flip-chip type light emitting diode according to any one of items 1 to 4, wherein the substrate is a GaP substrate.
[6] The flip chip according to any one of [1] to [5], wherein an area of a surface of the substrate opposite to a bonding surface with the compound semiconductor layer is smaller than an area of the light emitting portion. Type light emitting diode.
[7] The flip-chip light-emitting diode according to any one of [1] to [6], wherein a crystal orientation of a main surface of the compound semiconductor layer is within (100) ± 20 °.
[8] a first step of stacking and forming a compound semiconductor layer on a growth substrate;
A second step of bonding the compound semiconductor layer and the semiconductor substrate and removing the growth substrate;
A third step of removing a part of the compound semiconductor layer by etching to expose the second conductivity type semiconductor layer and leaving a part of the compound semiconductor layer to form an inter-electrode height adjusting portion;
A fourth step of forming a metal film by vapor deposition or sputtering and alloying by heat treatment to form first and second electrodes, and a method of manufacturing a flip chip type light emitting diode comprising:
In the third step, the height adjustment part between the electrodes is formed by a dry etching method using a resist shape or a difference in etching rate or a chemical etching method using a crystal orientation of a semiconductor layer. A method for manufacturing a flip chip type light emitting diode.

  According to the flip-chip type light emitting diode of the present invention, the second electrode includes the second conductive type semiconductor layer exposed by removing a part of the compound semiconductor layer, the side surface and the upper surface of the interelectrode height adjusting unit, In the flip chip type light emitting diode, the first electrode and the second electrode are substantially the same in height, and an inclined surface is provided on the side surface of the inter-electrode height adjusting portion. It is said that. As described above, since the side surface of the interelectrode height adjusting portion has a shape with a relaxed inclination, the thickness of the compound semiconductor layer made of an aluminum phosphide / gallium / indium mixed crystal (AlGaInP) layer is about 5 μm. However, the disconnection failure of the second electrode due to the height difference between the first electrode and the second electrode (that is, the height of the interelectrode height adjusting portion) can be reduced. Therefore, it is possible to improve the yield and connection reliability by suppressing the disconnection of the electrodes of the flip chip type light emitting diode.

  Further, according to the method of manufacturing a flip chip type light emitting diode of the present invention, the interelectrode height is increased by a dry etching method using a resist shape or a difference in etching rate or a chemical etching method using a crystal orientation of a semiconductor layer. Since the height adjusting portion is formed, the inter-electrode height adjusting portion in which the side surface inclination is relaxed can be formed.

It is a top view of the light emitting diode lamp using the flip chip type light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram along the A-A 'line | wire shown in FIG. 1 of the light emitting diode lamp using the flip chip type light emitting diode which is one Embodiment of this invention. It is a top view of the flip chip type light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram along the B-B 'line | wire shown in FIG. 3 of the flip chip type light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram of the epiwafer used for the flip chip type light emitting diode which is one Embodiment of this invention. It is a cross-sectional schematic diagram of the joining wafer used for the flip chip type light emitting diode which is one Embodiment of this invention. FIG. 4 shows a flip-chip light emitting diode according to another embodiment of the present invention, in which (a) is a plan view and (b) is a cross-sectional view taken along line C-C ′ shown in (a). FIG. 5 shows a flip-chip type light emitting diode according to another embodiment of the present invention, wherein (a) is a plan view and (b) is a cross-sectional view taken along line D-D ′ shown in (a). FIG. 4 shows a flip-chip light emitting diode according to another embodiment of the present invention, in which (a) is a plan view and (b) is a cross-sectional view taken along line E-E 'shown in (a). FIG. 4 shows a flip-chip light emitting diode according to another embodiment of the present invention, in which (a) is a plan view and (b) is a cross-sectional view taken along line F-F ′ shown in (a). It is a cross-sectional schematic diagram for demonstrating the structure of the conventional flip chip type light emitting diode.

  Hereinafter, a flip chip type light emitting diode which is an embodiment to which the present invention is applied will be described in detail with reference to the drawings together with a light emitting diode lamp using the flip chip type light emitting diode. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. Absent.

<Light emitting diode lamp>
1 and 2 are diagrams for explaining a light-emitting diode lamp using a flip-chip light-emitting diode, which is an embodiment to which the present invention is applied. FIG. 1 is a plan view, and FIG. It is sectional drawing along the AA 'line shown.

  As shown in FIGS. 1 and 2, a light-emitting diode lamp 41 using a flip-chip light-emitting diode (hereinafter simply referred to as “light-emitting diode”) 1 according to this embodiment includes one or more light-emitting diodes on the surface of a mount substrate 42. 1 is implemented. More specifically, an n electrode terminal 43 and a p electrode terminal 44 are provided on the surface of the mount substrate 42. Further, the n-type ohmic electrode 4 which is the first electrode of the light emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected using a gold bump 45 (flip chip bonding). On the other hand, the p-type ohmic electrode 5, which is the second electrode of the light emitting diode 1, and the p-electrode terminal 44 of the mount substrate 42 are connected using gold bumps 46. Further, as shown in FIG. 2, the light emitting diode 1 is fixed to the mount substrate 42 by connecting the n-type and p-type ohmic electrodes 4 and 5 of the light-emitting diode 1 and the gold bumps 45 and 46. . The surface of the mount substrate 42 on which the flip chip type light emitting diode 1 is mounted is sealed with a general sealing resin 47 such as silicon resin.

<Light emitting diode>
3 and 4 are diagrams for explaining a flip-chip type light emitting diode according to an embodiment to which the present invention is applied. FIG. 3 is a plan view, and FIG. 4 is a BB ′ line shown in FIG. FIG. As shown in FIGS. 3 and 4, the light-emitting diode 1 of the present embodiment is a flip-chip type light-emitting diode in which a compound semiconductor layer 2 and a semiconductor substrate (substrate) 3 are bonded. The light emitting diode 1 includes an n-type ohmic electrode (first electrode) 4 and a p-type ohmic electrode (second electrode) 5 provided on the side opposite to the main light extraction surface of the compound semiconductor layer 2. It is roughly structured. In addition, the main light extraction surface in this embodiment means the surface 3c on the opposite side to the bonding surface with the compound semiconductor layer 2 in the semiconductor substrate 3.

  More specifically, the inter-electrode height adjusting portion 6 is provided on a part of the surface 8a of the current diffusion layer 8 (second conductivity type semiconductor layer) exposed by removing a part of the compound semiconductor layer 2. It has been. Then, the p-type ohmic electrode 5 is continuously formed on the current diffusion layer 8 and the side surface 6a and the upper surface 6b of the interelectrode height adjusting unit 6. As a result, the light emitting diode 1 has substantially the same height from the semiconductor substrate 3 of the n-type ohmic electrode 4 and the p-type ohmic electrode 5.

Here, substantially the same height in the present specification means that when the light emitting diode 1 is bonded face-down, the n-type ohmic electrode 4 and the p-type ohmic electrode 5 do not cause an extreme step and are inclined during bonding. Does not occur, or the level difference is so small that there is no significant difference in bonding pressure conditions.
Also, the first conductivity type and the second conductivity type mean that when one of the n-type and p-type semiconductor polarities is the first conductivity type, the other p-type or n-type is the second conductivity type. It means that there is.

As shown in FIG. 4, the compound semiconductor layer (also referred to as an epitaxial growth layer) 2 is an aluminum phosphide / gallium / indium mixed crystal (composition formula (Al _X Ga _1-X ) _Y In _1-YP : 0 ≦ X ≦ 1 has a structure in which a pn junction type light-emitting portion 7 composed of 1 and 0 <Y ≦ 1) layers and a current diffusion layer 8 for planarly diffusing the element driving current over the entire light-emitting portion are sequentially stacked. ing. A known functional layer can be added to the structure of the compound semiconductor layer 2 as appropriate. For example, a known layer structure such as a contact layer for reducing the contact resistance of an ohmic electrode, a current blocking layer or a current confinement layer for limiting a region through which an element driving current flows can be provided. The compound semiconductor layer 2 is preferably formed by epitaxial growth on a GaAs substrate.

  As shown in FIG. 4, the light emitting unit 7 is configured by sequentially laminating at least a p-type lower cladding layer 9, a light emitting layer 10, and an n-type upper cladding layer 11 on a current diffusion layer 8. That is, the light emitting unit 7 includes a lower clad disposed on the lower side and the upper side of the light emitting layer 10 in order to “confine” the light emitting layer 10 with carriers (carriers) that cause radiative recombination. A so-called double hetero (English abbreviation: DH) structure including the layer 9 and the upper clad layer 11 is preferable in order to obtain high-intensity light emission.

Emitting layer 10 is composed of a semiconductor layer having the composition formula _{(Al X Ga 1-X)} Y In 1-Y P (0 ≦ X ≦ 1,0 <Y ≦ 1). The light emitting layer 10 may have a double hetero structure, a single quantum well (abbreviation: SQW) structure, or a multi quantum well (abbreviation: MQW) structure, but is monochromatic. In order to obtain excellent light emission, an MQW structure is preferable. In addition, a barrier layer and a well layer forming a quantum well (English abbreviation: QW) structure are formed (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1,0) The composition of Y ≦ 1) can be determined so that quantum levels resulting in the desired emission wavelength are formed in the well layer.

The layer thickness of the light emitting layer 10 is preferably in the range of 0.02 to 2 μm. Further, the conductivity type of the light emitting layer 10 is not particularly limited, and any of undoped, p-type and n-type can be selected. In order to increase the luminous efficiency, it is desirable that the crystallinity is undoped or the carrier concentration is less than 3 × 10 ¹⁷ cm ⁻³ .

  The lower clad layer 9 and the upper clad layer 11 are provided on the lower surface and the upper surface of the light emitting layer 10, respectively, as shown in FIG. Specifically, the lower cladding layer 9 is provided on the lower surface of the light emitting layer 10, and the upper cladding layer 11 is provided on the upper surface of the light emitting layer 10.

  The lower clad layer 9 and the upper clad layer 11 are configured to have different polarities. The carrier concentration and thickness of the lower clad layer 9 and the upper clad layer 11 can be in a known suitable range, and the conditions are preferably optimized so that the light emission efficiency of the light emitting layer 10 is increased.

Specifically, as the lower cladding layer 9, for example, Mg from the doped p-type _{(Al X Ga 1-X)} Y In 1-Y P (0.3 ≦ X ≦ 1,0 <Y ≦ 1) It is desirable to use a semiconductor material. The carrier concentration is preferably in the range of 2 × 10 ¹⁷ to 2 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.5 to 5 μm.

On the other hand, as the upper clad layer 11, for example, a semiconductor made of n-type (Al _X Ga _1-X ) _Y In _1-YP (0.3 ≦ X ≦ 1, 0 <Y ≦ 1) doped with Si. It is desirable to use materials. The carrier concentration is preferably in the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the layer thickness is preferably in the range of 0.5 to 2 μm.
The polarities of the lower clad layer 9 and the upper clad layer 11 can be appropriately selected in consideration of the element structure of the compound semiconductor layer 2.

  Band discontinuity between the lower cladding layer 9 and the light emitting layer 10, between the light emitting layer 10 and the upper cladding layer 11, and between the upper cladding layer 11 and the current spreading layer 8. An intermediate layer may be provided for gently changing the angle. In this case, each intermediate layer is preferably composed of a semiconductor material having a band gap between the two layers.

  Further, a contact layer for lowering the contact resistance of the ohmic electrode, a current blocking layer for limiting a region through which the element driving current flows, and a current constricting layer are known above the constituent layers of the light emitting unit 7. The layer structure can be provided. As the contact layer, for example, GaAs having a small band gap is generally used. On the other hand, it is desirable to use GaInP as the material of the contact layer that does not contain As.

  As shown in FIG. 4, the current diffusion layer 8 is provided below the light emitting unit 7 in order to diffuse the element driving current in a planar manner throughout the light emitting unit 7. Thereby, the light emitting diode 1 can emit light uniformly from the light emitting unit 7.

A material having a composition of (Al _X Ga _1-X ) _Y In _1- YP (0 ≦ X ≦ 0.7, 0 ≦ Y ≦ 1) can be applied as the current diffusion layer 8. X is 0.5 or less (Al concentration is about 12.5% or less) because a material having a low Al concentration is chemically stable although it depends on the element structure of the compound semiconductor layer 2. Is preferable, and 0 is more preferable. Y is preferably 1. That is, as the current spreading layer 8, the Al concentration is preferably 25% or less, more preferably 15% or less, and most preferably p-type GaP not containing Al.

  As shown in FIG. 4, the semiconductor substrate 3 is bonded to the current diffusion layer 8 side of the compound semiconductor layer 2. Then, as shown in FIG. 2, the semiconductor substrate 3 side is facing upward, the compound semiconductor layer 2 side is facing down (face down), and flip chip mounting is performed, whereby the semiconductor substrate 3 and the compound semiconductor layer 2 are The surface 3c opposite to the bonding surface is the main light extraction surface of the light emitting diode 1 (hereinafter referred to as the light extraction surface 3c).

The semiconductor substrate 3 is made of an optically transparent material that has sufficient strength to mechanically support the light emitting portion 7 and has a wide band gap that can transmit light emitted from the light emitting portion 7. Constitute. For example, III-V group compound semiconductor crystals such as gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), and gallium nitride (GaN), and II-VI such as zinc sulfide (ZnS) and zinc selenide (ZnSe). A group IV compound semiconductor crystal or a group IV semiconductor crystal such as hexagonal or cubic silicon carbide (SiC) can be used.
More specifically, a material that is chemically stable, has a high transmittance, and a refractive index close to that of the light emitting portion is desirable, and SiC, GaN, GaP, and the like are preferable examples.

Further, the semiconductor substrate 3 is preferably made of a material that can be easily processed. In order to support the light emitting portion 7 with sufficient mechanical strength, it is preferable to set the thickness to, for example, about 50 μm or more. Further, in order to facilitate the mechanical processing of the semiconductor substrate 3 after joining to the compound semiconductor layer 2, it is preferable that the thickness does not exceed about 300 μm. That is, in the light-emitting diode 1 of the present embodiment including the light-emitting layer 10 made of (Al _X Ga _1-X ) _Y In _1-YP (0 ≦ X ≦ 1, 0 <Y ≦ 1), the semiconductor substrate 3 is The n-type GaP substrate having a thickness of about 50 μm or more and about 300 μm or less is optimal.

  Further, as shown in FIG. 4, the side surface of the semiconductor substrate 3 is a vertical surface 3 a that is substantially perpendicular to the main light extraction surface 3 c on the side close to the compound semiconductor layer 2, and is far from the compound semiconductor layer 2. On the side, the inclined surface 3b is inclined inward with respect to the main light extraction surface 3c. Thereby, since the area of the surface opposite to the bonding surface of the semiconductor substrate 3 with the compound semiconductor layer 2 (that is, the light extraction surface 3c) is smaller than the area of the light emitting portion 7, the light emitting layer 10 side to the semiconductor substrate 3 side. It is possible to efficiently extract the light emitted to the outside. Further, part of the light emitted from the light emitting layer 10 toward the semiconductor substrate 3 is reflected by the vertical surface 3a and can be extracted by the inclined surface 3b. On the other hand, the light reflected by the inclined surface 3b can be extracted by the vertical surface 3a. Thus, the light extraction efficiency can be increased by the synergistic effect of the vertical surface 3a and the inclined surface 3b.

Moreover, in this embodiment, as shown in FIG. 4, it is preferable to make angle (alpha) which the inclined surface 3b and the surface parallel to a light emission surface make into the range of 55 degree | times-80 degree | times. By setting it as such a range, the light discharge | released from the light emitting layer 10 can be taken out outside efficiently.
Moreover, it is preferable to make the width | variety (thickness direction) of the vertical surface 3a into the range of 30 micrometers-100 micrometers. By setting the width of the vertical surface 3a within the above range, the light emitted from the light emitting layer 10 can be efficiently returned to the light emitting surface in the vertical surface 3a, and further, can be emitted from the main light extraction surface 3c. It becomes possible. For this reason, the light emission efficiency of the light emitting diode 1 can be improved.

  The inclined surface 3b and the light extraction surface 3c of the semiconductor substrate 3 are preferably roughened. By roughening the inclined surface 3b and the light extraction surface 3c, an effect of increasing the light extraction efficiency at the inclined surface 3b and the light extraction surface 3c can be obtained. That is, by roughening the inclined surface 3b and the light extraction surface 3c, total reflection on the inclined surface 3b can be suppressed and light extraction efficiency can be increased.

  The n-type ohmic electrode (first electrode) 4 and the p-type ohmic electrode (second electrode) 5 are low-resistance ohmic contact electrodes provided on the side opposite to the main light extraction surface of the compound semiconductor layer 2.

The n-type ohmic electrode 4 is provided above the upper clad layer 11, and for example, an alloy made of AuGe, Ni alloy / Au can be used.
Here, in the light emitting diode 1 of the present embodiment, as shown in FIG. 4, the n-type ohmic electrode 4 includes a linear electrode (linear electrode) 4a having a width of 10 μm or less and a pad-shaped electrode (pad electrode) 4b. It is preferable to comprise. The linear electrode 4a is preferably configured in a mesh shape such as a honeycomb or a lattice shape. The linear electrode can be a dot electrode. With such a configuration, an effect of reducing VF and an effect of improving reliability can be obtained. Moreover, by arranging uniformly, an electric current can be inject | poured into the light emitting layer 10 uniformly, As a result, the effect which improves a luminance characteristic and reliability is acquired.

  The pad electrode 4b is preferably configured to cover almost the entire surface of the compound semiconductor layer 2 on the n-type semiconductor layer. The interface between the pad electrode and the semiconductor is preferably made of a highly reflective material. For example, Au, Ag, Al, and alloy materials based on these materials. Au is a suitable material because it has a high reflectance with respect to red and can be used together with the pad electrode of the wiring. With such a configuration, the light from the light emitting layer 10 can be reflected to the light extraction surface 3c side, so that the luminance of the light emitting diode 1 can be increased. Further, by reducing the area of the linear electrode 4a, the reflection area of the pad electrode 4b can be increased, and high luminance can be achieved.

On the other hand, the p-type ohmic electrode 5 is provided on the current diffusion layer 8 exposed by removing a part of the compound semiconductor layer 2. For example, an alloy made of AuBe / Au can be used.
Here, in the light-emitting diode 1 of the present embodiment, as shown in FIG. 4, the p-type ohmic electrode 5 can be constituted by, for example, a linear electrode 5a having a width of 10 μm or less and a pad-shaped pad electrode 5b. preferable. The linear electrode 5 a is preferably formed on the current diffusion layer 8 exposed around the interelectrode height adjustment unit 6 so as to surround the interelectrode height adjustment unit 6. As described above, since the electrode composed of the linear electrode 5a and the pad electrode 5b constituting the p-type ohmic electrode 5 is formed on the current diffusion layer 8 composed of p-type GaP, a good ohmic contact can be obtained, so that the operating voltage can be obtained. Can be lowered. Furthermore, when the inter-electrode height adjustment unit 6 is a compound semiconductor layer, the area of the ohmic electrode portion that easily absorbs light at the interface is minimized, so that the reflectance of the light at the portion can be reduced to that of the entire ohmic electrode. It can be higher than the structure.

  The pad electrode 5b is continuously formed on the current diffusion layer 8 made of p-type GaP, which is exposed when a part of the compound semiconductor layer 2 is removed, and the side surface 6a and the upper surface 6b of the interelectrode height adjusting unit 6. Is formed. With this configuration, the pad electrode 4b of the n-type ohmic electrode 4 and the pad electrode 5b of the p-type ohmic electrode 5 are substantially the same height from the semiconductor substrate 3.

  In addition, in the light emitting diode 1 of this embodiment, as shown in FIG. 3, it is preferable to arrange | position so that the n-type ohmic electrode 4 and the p-type ohmic electrode 5 may become a diagonal position. The p-type ohmic electrode 5 is most preferably surrounded by the compound semiconductor layer 2. By setting it as such a structure, the effect of reducing an operating voltage is acquired. Further, by enclosing the four sides of the p-type ohmic electrode 5 with the n-type ohmic electrode 4, the current easily flows in the four directions, and as a result, the operating voltage decreases.

  The inter-electrode height adjusting unit 6 is configured so that the n-type ohmic electrode 4 (pad electrode 4b) and the p-type ohmic electrode 5 (pad electrode 5b) have substantially the same height from the semiconductor substrate 3. A member provided to absorb a step between the upper surface 2a of the compound semiconductor layer 2 provided with the type ohmic electrode 4 and the surface of the current diffusion layer 8 exposed by removing a part of the compound semiconductor layer 2; And on the exposed current diffusion layer 8. The interelectrode height adjusting unit 6 is provided such that the height of the upper surface 6b from the semiconductor substrate 3 is substantially equal to the height of the compound semiconductor layer 2 from the semiconductor substrate 3.

The material of the interelectrode height adjusting unit 6 is preferably a material capable of forming a pressure film, and is not particularly limited, but is not limited to an organic material such as polyimide, which is a heat-resistant resin, Au, Cu, Ni, Mo, Al , W, Ag, Ti and alloys thereof can be used. Metals to which the thick film plating method can be applied, for example, Au, Cu, Ni, etc. are suitable materials. These can be arbitrarily selected and used depending on the specifications of the light emitting diode 1 and bonding conditions.
From the viewpoint of heat dissipation, a metal material is preferable, and from the viewpoint of ease of processing, an organic material is preferable.

  Moreover, in the light emitting diode 1 of this embodiment, when the interelectrode height adjusting unit 6 removes a part of the compound semiconductor layer 2 in order to expose the surface of the current diffusion layer 8, It is preferable that a part is left. Specifically, as shown in FIG. 3, the compound semiconductor layer 2 is removed in an annular shape in a plan view, and the compound semiconductor layer 2 remaining in the center is used as the inter-electrode height adjusting unit 6. Thus, the upper surface 2a of the compound semiconductor layer 2 provided with the n-type ohmic electrode 4 and the upper surface 6b of the inter-electrode height adjusting unit 6 are essentially the same surface, and the distance from the semiconductor substrate 3 is equal. A step between the upper surface 2a of the compound semiconductor layer 2 provided with the n-type ohmic electrode 4 and the upper surface 8a of the current diffusion layer 8 exposed by removing a part of the compound semiconductor layer 2 can be easily eliminated. .

Further, as shown in FIG. 4, the inter-electrode height adjusting unit 6 is characterized in that the side surface 6 a is an inclined surface. Here, the “inclined surface” in this specification refers to the width of the bottom surface 6 c of the inter-electrode height adjusting unit 6 when the inter-electrode height adjusting unit 6 is viewed in a cross-section in a direction perpendicular to the surface of the semiconductor substrate 3. This also means that the width of the upper surface 6b is small and the width is reduced continuously or discontinuously from the bottom surface 6c to the upper surface 6b. That is, it is necessary not to provide a vertical surface on the side surface 6a of the inter-electrode height adjusting unit 6 or to prevent the vertical surface from becoming 3 μm or more.
Here, in the case of continuous reduction, the side surface 6a of the interelectrode height adjusting portion 6 has a tapered shape. On the other hand, in the case of discontinuous reduction, the side surface 6a is stepped.

With such a configuration, a step between the upper surface 2a of the compound semiconductor layer 2 provided with the n-type ohmic electrode 4 and the surface of the current diffusion layer 8 exposed by removing a part of the compound semiconductor layer 2 is provided. In addition, when the p-type ohmic electrode 5 is continuously formed, it is possible to easily form the electrode on the side surface 6a portion of the inter-electrode height adjusting portion 6. In addition, since the disconnection of the electrode on the side surface 6a of the inter-electrode height adjusting unit 6 can be suppressed during manufacturing or mounting, the yield and connection reliability can be improved.
In the present embodiment, as shown in FIG. 4, in the direction perpendicular to the surface of the semiconductor substrate 3, the cross-sectional shape of the inter-electrode height adjusting unit 6 gradually decreases in width from the bottom surface 6c toward the top surface 6b (continuously). Taper shape).

In the light emitting diode 1 of the present embodiment, the compound semiconductor layer 2 has a thickness of 3 μm or more, and the upper surface 2a of the compound semiconductor layer 2 provided with the n-type ohmic electrode 4 and a part of the compound semiconductor layer 2 are removed. The level difference from the exposed surface of the current diffusion layer 8 is about 3 to 8 μm. Therefore, the inclination angle of the electrode height adjusting unit 6 is preferably about 45 to 70 degrees.
Here, if it is less than 45 degrees, the area of the inclined portion increases, which is not preferable because the cost increases. On the other hand, exceeding 70 degrees is not preferable because the probability of disconnection increases.
On the other hand, the above range is preferable because of high yield and low cost.

<Method for manufacturing light-emitting diode>
Next, the manufacturing method of the light emitting diode 1 of this embodiment is demonstrated. FIG. 5 is a cross-sectional view of an epiwafer used for the light emitting diode 1 of the present embodiment. FIG. 6 is a cross-sectional view of a bonded wafer used for the light emitting diode 1 of the present embodiment.

(Formation process of compound semiconductor layer)
First, as shown in FIG. 5, the compound semiconductor layer 2 is produced. The compound semiconductor layer 2 includes a GaAs substrate 12, a buffer layer 13 made of GaAs, an etching stop layer (not shown) provided for selective etching, and a contact layer 14 made of n-type GaInP doped with Si. The n-type upper clad layer 11, the light emitting layer 10, the p-type lower clad layer 9, and the current diffusion layer 8 made of Mg-doped p-type GaP are sequentially laminated.

  As the GaAs substrate 12, a commercially available single crystal substrate manufactured by a known manufacturing method can be used. The surface of the GaAs substrate 12 on which the epitaxial growth is performed is desirably smooth. The surface orientation of the surface of the GaAs substrate 12 is easy to epi-grow, and from the (100) plane and (100) which are mass-produced, the substrate turned off within ± 20 ° is preferable from the standpoint of quality stability. Furthermore, the range of the plane orientation of the GaAs substrate 14 is more preferably 15 ° off ± 5 ° from the (100) direction to the (0-1-1) direction.

The dislocation density of the GaAs substrate 12 is desirably low in order to improve the crystallinity of the compound semiconductor layer 2. Specifically, for example, 10,000 pieces cm ⁻² or less, preferably 1,000 pieces cm ⁻² or less are suitable.

The GaAs substrate 12 may be n-type or p-type. The carrier concentration of the GaAs substrate 12 can be appropriately selected from desired electrical conductivity and element structure. For example, when the GaAs substrate 12 is a silicon-doped n-type, the carrier concentration is preferably in the range of 1 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ . On the other hand, when the GaAs substrate 12 is a p-type doped with zinc, the carrier concentration is preferably in the range of 2 × 10 ^{18 to} 5 × 10 ¹⁹ cm ⁻³ .

  The buffer layer (buffer) 13 is provided to alleviate lattice mismatch between the GaAs substrate 12 and the constituent layers of the light emitting unit 7. For this reason, the buffer layer 13 is not necessarily required if the quality of the substrate and the epitaxial growth conditions are selected. The buffer layer 13 is preferably made of the same material as that of the substrate to be epitaxially grown. Therefore, in the present embodiment, it is preferable to use GaAs for the buffer layer 13 as with the GaAs substrate 12. The buffer layer 13 may be a multilayer film made of a material different from that of the GaAs substrate 12 in order to reduce the propagation of defects. The thickness of the buffer layer 13 is preferably 0.1 μm or more, and more preferably 0.2 μm or more.

The contact layer 14 is provided to reduce the contact resistance with the electrode. The contact layer 14 is preferably made of a material that does not contain Al, such as GaAs, and is most preferably GaInP that does not contain As. Further, the lower limit value of the carrier concentration of the contact layer 14 is preferably 5 × 10 ¹⁷ cm ⁻³ or more and more preferably 1 × 10 ¹⁸ cm ⁻³ or more in order to reduce the contact resistance with the electrode. The upper limit value of the carrier concentration is desirably 2 × 10 ¹⁹ cm ⁻³ or less at which the crystallinity is likely to decrease. The thickness of the contact layer 14 is preferably 0.02 μm or more, and more preferably 0.05 μm or more.

  In the present embodiment, a known growth method such as a molecular beam epitaxial method (MBE) or a low pressure metal organic chemical vapor deposition method (MOCVD method) can be applied. Among these, it is desirable to apply the MOCVD method which is excellent in mass productivity. Specifically, the GaAs substrate 12 used for the epitaxial growth of the compound semiconductor layer 2 is preferably subjected to a pretreatment such as a cleaning process or a heat treatment before the growth to remove surface contamination or a natural oxide film.

When each layer of the compound semiconductor layer 2 is epitaxially grown, examples of the group III constituent material include trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ((CH ₃ ) ₃ In) can be used. Further, as a Mg doping raw material, for example, biscyclopentadienyl magnesium (bis- (C ₅ H ₅ ) ₂ Mg) or the like can be used. Further, as a Si doping material, for example, disilane (Si ₂ H ₆ ) or the like can be used. In addition, phosphine (PH ₃ ), arsine (AsH ₃ ), or the like can be used as a raw material for the group V constituent element. As the growth temperature of each layer, 720 to 770 ° C. can be applied when p-type GaP is used as the current diffusion layer 8, and 600 to 700 ° C. can be applied to the other layers. Furthermore, the carrier concentration, layer thickness, and temperature conditions of each layer can be selected as appropriate.

  The compound semiconductor layer 2 manufactured in this way can obtain a good surface state with few crystal defects. The compound semiconductor layer 2 may be subjected to surface processing such as polishing corresponding to the element structure.

(Transparent substrate bonding process)
Next, the compound semiconductor layer 2 and the semiconductor substrate 3 are bonded. In joining the compound semiconductor layer 2 and the semiconductor substrate 3, first, the surface of the current diffusion layer 8 constituting the compound semiconductor layer 2 is polished and mirror-finished. Next, the semiconductor substrate 3 to be attached to the mirror-polished surface of the current spreading layer 8 is prepared. The surface of the semiconductor substrate 3 is polished to a mirror surface before being bonded to the current diffusion layer 8. Next, the compound semiconductor layer 2 and the semiconductor substrate 3 are carried into a general semiconductor material pasting apparatus, and the neutralized (neutral) Ar beam is irradiated by colliding electrons with both surfaces mirror-polished in vacuum. To do. Then, it can join at room temperature by superimposing both surfaces in the sticking apparatus which maintained the vacuum, and applying a load (refer FIG. 6).

(Process for forming n-type and p-type electrodes and inter-electrode height adjustment section)
Next, the n-type ohmic electrode 4, the p-type ohmic electrode 5, and the interelectrode height adjustment unit 6 are formed. In the formation of the n-type ohmic electrode 4 and the p-type ohmic electrode 5, first, the GaAs substrate 12 and the GaAs buffer layer 13 are selectively removed from the compound semiconductor layer 2 bonded to the semiconductor substrate 3 with an ammonia-based etchant. Next, the n-type ohmic electrode 4 is formed on the exposed surface of the contact layer 14. Specifically, for example, patterning is performed using a general photolithography means, and AuGe and Ni alloy / Au are stacked by vacuum deposition so as to have an arbitrary thickness, and then the n-type ohmic electrode 4 is formed. Form a shape.

Next, the contact layer 14, the upper clad layer 11, the light emitting layer 10, and the lower clad layer 9 are selectively removed to expose the surface of the current diffusion layer 8, and a part of the compound semiconductor layer 2 is left to leave the electrode. The inter-height adjustment part 6 is formed.
Here, the inter-electrode height adjusting unit 6 is formed by setting the crystal orientation of the main surface of the compound semiconductor layer 2 within (100) ± 20 °, and using a chemical etching method such as acid or alkali. Thus, it is possible to form the interelectrode height adjusting portion 6 having the shape of the desired inclined side surface 6a reflecting the crystal orientation.
Further, the formation of the inter-electrode height adjusting portion 6 may be performed by a dry etching method using a resist shape and an etching rate difference. A dry etching method capable of selecting an inclination angle depending on process conditions is desirable.

  Next, the p-type ohmic electrode 5 is formed on the exposed upper surface 8 a of the current diffusion layer 8. Specifically, for example, patterning is performed using a general photolithography means, and AuBe / Au is laminated by vacuum deposition so as to have an arbitrary thickness, and then the shape of the p-type ohmic electrode 5 is formed. To do. Then, the low resistance n-type ohmic electrode 4 and p-type ohmic electrode 5 can be formed, for example by heat-processing on 400-500 degreeC and the conditions for 5 to 20 minutes, and alloying. At this time, an alloy layer is formed at the interface between the semiconductor and the electrode, and a good ohmic electrode is obtained.

(Semiconductor substrate processing process)
Next, the shape of the semiconductor substrate 3 is processed. In processing the semiconductor substrate 3, first, V-shaped grooving is performed on the surface opposite to the bonding surface with the compound semiconductor layer 2. At this time, the inner surface of the V-shaped groove on the light extraction surface 3c side becomes an inclined surface 3b having an angle α formed with a surface parallel to the light emitting surface. Next, dicing is performed from the compound semiconductor layer 2 side at predetermined intervals to form chips. Note that the vertical surface 3a of the semiconductor substrate 3 is formed by dicing at the time of chip formation.

  The formation method of the inclined surface 3b is not particularly limited, and conventional methods such as wet etching, dry etching, scribing, and laser processing can be used in combination, but the shape controllability and productivity can be improved. Most preferably, a high dicing method is applied. By applying the dicing method, the manufacturing yield can be improved.

  The method for forming the vertical surface 3a is not particularly limited, but it is preferably formed by a dicing method having excellent workability.

  Finally, if necessary, for example, in the case of a GaP substrate, a crushed layer and dirt due to dicing are removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. In this way, the light emitting diode 1 is manufactured.

<Method for manufacturing light-emitting diode lamp>
Next, a manufacturing method of the light emitting diode lamp 41 using the light emitting diode 1, that is, a mounting method of the light emitting diode 1 will be described.
As shown in FIGS. 1 and 2, a predetermined number of light emitting diodes 1 are mounted on the surface of the mount substrate 42. The mounting of the light emitting diode 1 is first performed by positioning the mount substrate 42 provided with the gold bumps 45 and 46 and the light emitting diode 1 with the semiconductor substrate 3 side facing up and the compound semiconductor layer 2 side facing down (face down). The light emitting diodes 1 are arranged at predetermined positions on the surface of the mount substrate 42. Next, the light emitting diode 1 is die-bonded to the surface of the mount substrate 42 by the gold bumps 45 and 46 provided on the mount substrate 42. At this time, the n-type ohmic electrode 4 of the light-emitting diode 1 and the n-electrode terminal 43 of the mount substrate 42 are connected by the gold bump 45, and at the same time, the p-type ohmic electrode 5 and the p-electrode terminal 44 of the mount substrate 42 are gold. They are connected by bumps 46. Finally, the surface of the mounting substrate 42 on which the light emitting diode 1 is mounted is sealed with a sealing agent 47 such as a general silicon resin (a general epoxy resin or the like). In this way, the light emitting diode lamp 41 using the light emitting diode 1 is manufactured.

  As described above, according to the flip-chip type light emitting diode 1 of the present embodiment, the p-type ohmic electrode (second electrode) 5 is formed from the p-type GaP exposed by removing a part of the compound semiconductor layer 2. The current diffusion layer (second conductivity type semiconductor layer) 8 and the side surface 6a and the upper surface 6b of the interelectrode height adjustment unit 6 are formed continuously, and the n-type and p-type ohmic electrodes 4 and 5 are high. In the flip-chip type light emitting diode 1 having substantially the same length, the side surface 6a of the interelectrode height adjusting portion 6 is a tapered inclined surface. Thus, since the inter-electrode height adjusting portion 6 has a shape in which the inclination of the side surface 6a is relaxed, the thickness of the compound semiconductor layer made of an aluminum phosphide / gallium / indium mixed crystal (AlGaInP) layer is about 5 μm. Even so, the disconnection failure of the p-type ohmic electrode 5 due to the height difference between the n-type ohmic electrode 4 and the p-type ohmic electrode 5 (that is, the height of the inter-electrode height adjusting portion 6) can be reduced. it can. Therefore, disconnection of the electrode 1 of the flip-chip type light emitting diode can be suppressed, and yield and connection reliability can be improved.

  Moreover, according to the manufacturing method of the flip-chip type light emitting diode 1 of the present embodiment, the electrode is formed by a dry etching method using a resist shape or an etching rate difference or a chemical etching method using a crystal orientation of a semiconductor layer. In order to form the inter-space height adjusting portion 6, the inter-electrode height adjusting portion 6 in which the inclination of the side surface 6a is relaxed can be formed.

  Note that the flip-chip type light emitting diode to which the present invention is applied is not necessarily limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. In the following description, the same parts as those of the light emitting diode 1 are not described and the same reference numerals are given in the drawings.

  For example, as shown in FIG. 7A, the inter-electrode height adjusting unit 6 removes a part of the compound semiconductor layer 2 so that the remaining portion of the compound semiconductor layer 2 becomes a quadrangle in a plan view, and FIG. As shown in FIG. 4, the side surface 26a may be a tapered inter-electrode height adjusting portion 26 in a sectional view.

  In addition, the inter-electrode height adjusting unit 6 is provided so that the remaining portion of the compound semiconductor layer 2 becomes any one of the four corners in a plan view as shown in FIG. 8A, for example. As shown in FIG. 8B, the inter-electrode height adjusting portion 36 may have a tapered side surface 36a in a cross-sectional view.

Furthermore, the inter-electrode height adjusting unit 6 is provided so that the remaining portion of the compound semiconductor layer 2 is in any one of the four corners in plan view, as shown in FIG. 9A, for example. As shown in FIG. 9B, the width of the inter-electrode height adjustment unit 46 may be discontinuously reduced from the bottom surface 46 c toward the top surface 46 b in a cross-sectional view. In other words, the cross-sectional shape of the inter-electrode height adjusting portion 46 may be a stepped shape in which the side surface 46a gradually decreases from the bottom surface 46c toward the top surface 46b in the direction perpendicular to the surface of the semiconductor substrate 3.
With such a configuration, p is formed at the level difference between the upper surface 2a of the compound semiconductor layer 2 where the n-type ohmic electrode 44 is provided and the surface of the current diffusion layer 8 exposed by removing a part of the compound semiconductor layer 2. When the type ohmic electrode 45 is continuously formed, disconnection of the electrode on the side surface 46a can be suppressed. Therefore, yield and connection reliability can be improved.

  Furthermore, the inter-electrode height adjusting unit 6 is provided so that the remaining portion of the compound semiconductor layer 2 becomes a central portion of the substrate in a plan view as shown in FIG. 10A, for example. ), The width of the inter-electrode height adjusting unit 56 may be reduced discontinuously from the bottom surface 56c toward the top surface 56b in a cross-sectional view.

  Moreover, the said linear electrode 4a can be made into the circular electrode 24a, for example, as shown to Fig.7 (a). By arranging the circular electrodes 24a evenly on the n-type semiconductor layer of the compound semiconductor layer 2, the light emission efficiency can be increased.

  Further, the linear electrode 5a can be a linear electrode 35a extended along two sides of the exposed upper surface of the current diffusion layer 8, as shown in FIG. 8A. With such a configuration, the side surface 35a of the p-type ohmic electrode 3 is not easily broken, and the light emission efficiency of the light emitting diode 31 can be increased.

  Hereinafter, the effect of the present invention will be specifically described with reference to examples. The present invention is not limited to these examples.

Example 1
In this example, an example in which a light-emitting diode according to the present invention is manufactured will be specifically described. In addition, the light emitting diode manufactured in this example is a red light emitting diode having an AlGaInP light emitting portion. In Example 1, the present invention is described in detail by taking as an example a case where a light emitting diode is manufactured by bonding an epitaxial multilayer structure (compound semiconductor layer) provided on a GaAs substrate and a GaP substrate (semiconductor substrate). I will explain it.

In the light-emitting diode of Example 1, first, an epitaxial wafer provided with semiconductor layers sequentially stacked on a semiconductor substrate made of GaAs single crystal having a surface inclined by 15 ° from an n-type (100) surface doped with Si is formed. Made using. The stacked semiconductor layers are a buffer layer made of n-type GaAs doped with Si, a contact layer made of n-type (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P doped with Si, Si-doped n-type (Al _0.7 Ga _0.3 ) _0.5 In _0.5 P upper cladding layer, undoped (Al _0.2 Ga _0.8 ) _0.5 In _0.5 P / A 1 _0.7 Ga _0.3 ) _0.5 In _0.5 P light-emitting layer consisting of 20 pairs, and Mg-doped p-type (Al _0.7 Ga _0.3 ) _0.5 In _{0 A} lower clad layer made of .5P, a thin film (Al _0.5 Ga _0.5 ), an intermediate layer made of _0.5 In _0.5 P, and a Mg-doped p-type GaP layer.

In this example, each of the semiconductor layers described above includes trimethylaluminum ((CH ₃ ) ₃ Al), trimethylgallium ((CH ₃ ) ₃ Ga), and trimethylindium ((CH ₃ ) ₃ In) as group III constituent elements. An epitaxial wafer was formed by stacking on a GaAs substrate by a low pressure metal organic chemical vapor deposition method (MOCVD method) used as a raw material. Biscyclopentadiethylmagnesium (bis- (C ₅ H ₅ ) ₂ Mg) was used as the Mg doping material. Disilane (Si ₂ H ₆ ) was used as a Si doping material. Further, phosphine (PH ₃ ) or arsine (AsH ₃ ) was used as a group V constituent element material. The GaP layer was grown at 750 ° C., and the other semiconductor layers were grown at 730 ° C.

The carrier concentration of the GaAs buffer layer was about 2 × 10 ¹⁸ cm ⁻³ and the layer thickness was about 0.2 μm. The contact layer was made of (Al _0.5 Ga _0.5 ) _0.5 In _0.5 P, the carrier concentration was about 2 × 10 ¹⁸ cm ⁻³ , and the layer thickness was about 1.5 μm. The carrier concentration of the upper clad layer was about 8 × 10 ¹⁷ cm ⁻³ and the layer thickness was about 1 μm. The light emitting layer was undoped 0.8 μm. The carrier concentration of the lower cladding layer was about 2 × 10 ¹⁷ cm ⁻³ and the layer thickness was 1 μm. The carrier concentration of the p-type GaP layer was about 3 × 10 ¹⁸ cm ⁻³ and the layer thickness was 9 μm.

Next, the p-type GaP layer (current diffusion layer) was mirror-polished by polishing a region extending from the surface to a depth of about 1 μm.
By this mirror finishing, the surface roughness of the p-type GaP layer was set to 0.18 nm. On the other hand, a semiconductor substrate made of n-type GaP to be attached to the mirror-polished surface of the p-type GaP layer was prepared. A single crystal having a plane orientation of (111) was used for the semiconductor substrate for pasting, to which Si was added so that the carrier concentration was about 2 × 10 ¹⁷ cm ⁻³ . The semiconductor substrate had a diameter of 50 millimeters (mm) and a thickness of 250 μm. The surface of the semiconductor substrate was polished to a mirror surface before being bonded to the p-type GaP layer, and finished to a square average square root value (rms) of 0.12 nm.

Next, the semiconductor substrate and the epitaxial wafer were carried into a general semiconductor material pasting apparatus, and the inside of the apparatus was evacuated to 3 × 10 ⁻⁵ Pa.

Next, the surfaces of both the semiconductor substrate and the current diffusion layer were irradiated with an Ar beam neutralized by colliding electrons for 3 minutes. Thereafter, the surfaces of the current diffusion substrate and the p-type GaP layer were superposed in a sticking apparatus maintained in a vacuum, a load was applied so that the pressure on each surface was 50 g / cm ^2, and both were bonded at room temperature. .

  Next, the GaAs substrate and the GaAs buffer layer were selectively removed from the bonded wafer with an ammonia-based etchant. Next, an n-type ohmic electrode was formed as a first electrode on the surface of the contact layer by vacuum deposition so that the thickness of AuGe and Ni alloy was 0.5 μm, Pt was 0.2 μm, and Au was 1 μm. . Thereafter, patterning was performed using a general photolithography means to form an n-type ohmic electrode.

Next, the epi layer in the region where the p-type ohmic electrode is to be formed as the second electrode is selectively removed to expose the current diffusion layer made of p-type GaP, and a part of the epi layer is left to leave the electrode. A height adjustment part was formed. Specifically, the photo-resist formation conditions were adjusted to make the cross-section trapezoidal, and the dry etching selectivity between the semiconductor and the resist was controlled. In the dry etching, the semiconductor is etched while etching the resist. Here, since the cross-sectional shape of the resist is trapezoidal, the etching of the resist starts from the periphery, and the semiconductor is also etched gradually toward the center. As a result, the inter-electrode height adjusting portion having a tapered side surface was formed.
The angle of the inclined surface was about 60 degrees. The etching depth was 5 μm, and a part of the GaP layer was etched.
In the case of forming an inclination using the mesa direction of the (100) plane, the shape is naturally controlled because the etching rate varies depending on the crystal orientation.

  Next, a p-type ohmic electrode was formed on the exposed surface of the current diffusion layer made of p-type GaP by vacuum deposition so that AuBe was 0.2 μm and Au was 1 μm. Furthermore, an annular linear electrode was formed on the p-type GaP current diffusion layer at the peripheral portion of the interelectrode height adjustment portion formed by leaving a part of the epi layer by photolithography. Thereafter, heat treatment was performed at 450 ° C. for 10 minutes to form an alloy, and low resistance p-type and n-type ohmic electrodes were formed.

  Next, a pad electrode for connecting the p-type and n-type ohmic electrodes was formed by laminating Au to 0.2 μm, Pt to 0.2 μm, and Au to 1.5 μm.

  Next, using a dicing saw, V-shaped grooving was performed on the back surface region of the semiconductor substrate so that the angle α of the inclined surface was 70 ° and the thickness of the vertical surface was 80 μm. Next, a dicing saw was used to cut from the compound semiconductor layer side at 350 μm intervals to form chips. The crushing layer and dirt by dicing were removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to produce a light emitting diode of Example 1.

  500 light emitting diode lamps in which the light emitting diode chip of Example 1 manufactured as described above was mounted face-down on a mounting substrate were mounted. In this light-emitting diode lamp, the mount is heated and supported (mounted) by a eutectic die bonder, and the n-type ohmic electrode of the light-emitting diode and the n-electrode terminal provided on the surface of the mount substrate are connected by gold bumps, and p After connecting the type ohmic electrode and the p-electrode terminal with a gold bump, it was sealed with a general epoxy resin.

  When 500 light emitting diode lamps were mounted, there was no defective mounting of the light emitting diode.

(Comparative Example 1)
A light emitting diode was fabricated in the same manner as in Example 1 except that the side surface of the interelectrode height adjusting portion was a vertical surface. As a result of mounting 500 light-emitting diode lamps in which the manufactured light-emitting diode chip of Comparative Example 1 was mounted face-down on the mount substrate, the number of defective mounting of the light-emitting diodes was 4 disconnection failures.

  The light-emitting diode of the present invention can be used for high-luminance displays, in-vehicle use, and illumination.

1. Light emitting diode (flip chip type light emitting diode)
2 ... Compound semiconductor layer 2a ... Upper surface 3 ... Semiconductor substrate 3a ... Vertical surface 3b ... Inclined surface 3c ... Bottom surface (light extraction surface)
4 ... n-type ohmic electrode (first electrode)
5 ... p-type ohmic electrode (second electrode)
6 ... Height adjustment part between electrodes 6a ... Side surface (inclined side surface)
DESCRIPTION OF SYMBOLS 7 ... Light emission part 8 ... Current spreading layer 8a ... Upper surface 9 ... Lower clad layer 10 ... Light emitting layer 11 ... Upper clad layer 11a ... Upper surface 12 ... GaAs substrate 13 ... buffer layer 14 ... contact layer 41 ... light emitting diode lamp 42 ... mount substrate 43 ... n electrode terminal 44 ... p electrode terminal 45, 46 ... gold bump 47 ... Sealing resin

Claims (8)

A substrate that is transparent to light emitted from the light emitting section;
A compound semiconductor layer having a thickness of 3 μm or more having a light emitting portion of a pn junction structure made of AlGaInP or AlGaAs, which is bonded to the substrate;
A first electrode provided in ohmic contact with a first conductivity type semiconductor layer on a surface side of the compound semiconductor layer;
A second electrode provided in ohmic contact with a semiconductor layer of a second conductivity type exposed by removing a part of the compound semiconductor layer;
An inter-electrode height adjusting portion provided on a part of the surface of the second conductivity type semiconductor layer exposed by removing a part of the compound semiconductor layer;
The second electrode is continuously formed on a second conductive type semiconductor layer exposed by removing a part of the compound semiconductor layer, and a side surface and an upper surface of the inter-electrode height adjusting unit, A flip-chip light emitting diode in which the height of the first electrode and the height of the second electrode are substantially the same,
A flip-chip type light emitting diode, wherein a side surface of the inter-electrode height adjusting portion is an inclined surface.   2. The flip-chip light emitting diode according to claim 1, wherein the inter-electrode height adjusting portion is a part of the compound semiconductor layer remaining when a part of the compound semiconductor layer is removed.   3. The flip chip according to claim 1, wherein a cross-sectional shape in a direction perpendicular to the surface of the substrate of the inter-electrode height adjusting portion is a tapered shape in which the width of the upper surface is narrower than the width of the bottom surface. Type light emitting diode.   3. The flip chip according to claim 1, wherein a cross-sectional shape of the inter-electrode height adjusting portion in a direction perpendicular to the surface of the substrate is a stepped shape having a top surface narrower than a bottom surface. Type light emitting diode.   The flip chip type light emitting diode according to any one of claims 1 to 4, wherein the substrate is a GaP substrate.   6. The flip-chip type light emission according to claim 1, wherein an area of a surface of the substrate opposite to a bonding surface with the compound semiconductor layer is smaller than an area of the light emitting portion. diode.   The flip-chip light-emitting diode according to claim 1, wherein a crystal orientation of a main surface of the compound semiconductor layer is within (100) ± 20 °. A first step of stacking and forming a compound semiconductor layer on a growth substrate;
A second step of bonding the compound semiconductor layer and the semiconductor substrate and removing the growth substrate;
A third step of removing a part of the compound semiconductor layer by etching to expose the second conductivity type semiconductor layer and leaving a part of the compound semiconductor layer to form an inter-electrode height adjusting portion;
A fourth step of forming a metal film by vapor deposition or sputtering and alloying by heat treatment to form first and second electrodes, and a method of manufacturing a flip chip type light emitting diode comprising:
In the third step, the height adjustment part between the electrodes is formed by a dry etching method using a resist shape or a difference in etching rate or a chemical etching method using a crystal orientation of a semiconductor layer. A method for manufacturing a flip chip type light emitting diode.

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