JP2011129563A - Multilayer wiring board, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board and a method of manufacturing the same such that an amount of warpage can be suppressed, and operability and a yield are satisfactory even for coreless technique employed in which wiring layers are stacked only on one side of a copper foil. <P>SOLUTION: This invention relates to: the multilayer wiring board that includes a first layer wiring pattern formed by circuit-processing a metal foil A, and at least one high layer-side wiring layer having an insulating resin layer disposed on the first layer wiring pattern and a wiring pattern disposed on the insulating resin layer, wherein a high layer-side wiring pattern is formed on the insulating resin layer by circuit-processing the metal foil and a conductor layer formed by plating, and a highest layer-side wiring pattern is larger in thickness than the first layer wiring pattern or larger in conductor layer remaining ratio than the first layer wiring pattern, or a highest layer-side insulating resin layer is smaller in thickness than the insulating resin layer on the first layer wiring pattern; and the method of manufacturing the same. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a multilayer wiring board used for a substrate on which an electronic component element such as a SAW (Surface Acoustic Wave) piezoelectric element or a semiconductor element is mounted, and a method for manufacturing the same.

  In recent years, electronic devices have been further reduced in size, weight, and functionality, and multilayer wiring boards used for these devices are required to have a thinner multilayer wiring board as well as multilayering and wiring miniaturization. Accordingly, in the manufacturing process of the multilayer wiring board, it is necessary to handle a thinner wiring board. That is, a conventional multilayer wiring board for mounting an electronic component element is manufactured by a so-called build-up method, which includes an insulating resin layer and a wiring pattern on both sides of a thin wiring board serving as a core board. This is because it is a manufacturing method in which wiring layers are stacked to manufacture a multilayer wiring board, and therefore, in a stage where the number of wiring layers is small, it is necessary to proceed with the manufacturing process with a thin wiring board having a thickness of 0.1 mm or less, for example. Thin wiring boards are difficult to handle because they are prone to warpage due to dimensional fluctuations, breakage, breakage, etc. due to catching in the manufacturing apparatus during the manufacturing process. As a method for facilitating the handling of such a thin wiring board, a method of attaching a jig or a supporting board for the purpose of giving mechanical strength to each of the wiring boards can be considered. However, this method has a problem that the number of man-hours is greatly increased and the cost is increased.

  As a method for avoiding such a problem, after preparing a support having laminated peelable copper foils on both sides and forming a multilayer wiring board on both sides of the support, the peeling action of the peelable copper foil is performed. A method of separating a multilayer wiring board and a support by using (Patent Document 1) A support having two substrates bonded together is prepared, a multilayer wiring substrate is formed on both sides, and then the bonded substrates are bonded together Is separated from the multilayer wiring board, and then the support is removed from the multilayer wiring board (Patent Document 2). A core substrate having copper foil on both sides is prepared as a support, and the copper substrate on both sides of the core substrate is prepared. By using the fact that a small copper foil A is directly stacked and wiring layers are stacked on the copper foil A to form a multilayer wiring board, the area where the copper foils are directly stacked is not bonded. , A method of separating a multilayer wiring board and a core board (patent Document 3) and the like are known. Unlike the conventional build-up method, these manufacturing methods do not require a core substrate as a support for the structure of the manufactured multilayer wiring board itself. For this reason, such a manufacturing method is hereinafter referred to as a coreless construction method in the present invention.

  According to these coreless construction methods, in addition to the mechanical strength of the support, the thickness of the wiring board is two, so the support and the wiring can be provided even in a thin wiring board with a small number of layers. Since the entire thickness including the substrate is increased and the rigidity is increased, it is possible to suppress breakage, breakage, and the like due to catching in the manufacturing facility. In addition, since the multilayer wiring board is formed on both sides of the support body in a symmetrical configuration, even if warpage due to dimensional variation occurs in the manufacturing process, the stress due to warpage is almost balanced on both sides of the support body. As a whole including the body and the multilayer wiring board, warpage can be suppressed. Furthermore, in the coreless construction method of Patent Document 3, the wiring layers are stacked only on one side of the copper foil A, instead of stacking the wiring layers on both sides of the core substrate that is the inner layer as in the conventional build-up method. For this reason, since one of the outermost conductor layers of the multilayer wiring board can be formed of only the copper foil A, it is advantageous for forming a fine wiring pattern. In addition, if the multilayer wiring boards formed on both sides of the support are viewed individually, the wiring layers are not stacked at the same time on one side of the core board, which is the inner layer, as in the conventional build-up method. However, the wiring layers are stacked only on one side, but since two sheets are stacked in one stacking process, productivity equivalent to that of the conventional build-up method can be maintained.

Japanese Patent No. 4273895 JP 2008-047936 A JP 2009-252827 A

  However, in general, when a high-layer wiring layer is stacked on top of a low-layer wiring layer by stacking an insulating resin layer and a conductor layer, the higher-layer side is newly stacked rather than the cured shrinkage of the already hardened low-layer wiring layer. Therefore, the multilayer wiring board warps in a state where the higher wiring layer is on the inner side. In the above conventional coreless construction method, it is possible to suppress warping or improve rigidity as a whole including the support and the multilayer wiring board, but warpage when the multilayer wiring board becomes a single body. Is not considered. In other words, in the coreless method, the wiring layer is not stacked on both sides of the core substrate that is the inner layer as in the conventional build-up method, but the wiring layer is stacked only on one side. In the multilayer wiring board, since the shrinkage of the insulating resin layer is caused to be biased to only one side of the multilayer wiring board, the warp tends to increase particularly when the number of wiring layers increases. On the other hand, the conductor layer on the side in contact with the support of the multilayer wiring board must be separated from the support before the manufacturing process after circuit formation can be performed. It is necessary to separate the multilayer wiring board and the support, and a manufacturing process performed by the multilayer wiring board alone remains. For this reason, when a support body is isolate | separated and it becomes a multilayer wiring board single-piece | unit, the point which generate | occur | produces curvature will be a problem.

  To solve this problem, before the number of wiring layers increases and warping expands, that is, before stacking up to the required number of wiring layers, the support is separated into a single multilayer wiring board, and then The conventional build-up method may be used to stack the necessary number of wiring layers on both sides of the separated multilayer wiring board. However, when using the conventional build-up method, when stacking the wiring layers on both sides, after laminating the insulating resin layer and copper foil on both sides of the separated multilayer wiring board, use the conformal method. A non-through hole is opened, plating for interlayer connection is performed, and then a wiring pattern is formed by etching. In this case, the first layer wiring pattern which will be the outermost layer finally has a copper foil and a plating layer formed by interlayer connection thereon. For this reason, there is a problem that the thickness of the first layer wiring pattern is increased, which is disadvantageous for forming a fine pattern. Moreover, since the plating layer produced by the interlayer connection formed on the copper foil is likely to generate protrusions, the unevenness is easily enlarged as compared with the case of the copper foil alone. Since the first layer wiring pattern which is the outermost layer is usually further subjected to protective plating on the surface, the unevenness is further enlarged.

  By the way, as a use of a multilayer wiring board on which electronic component elements are mounted, there is a use as a multilayer wiring board constituting a SAW (Surface Acoustic Wave) device. The vibration space formed in the gap between the active surface of the SAW piezoelectric element flip-chip connected down (surface acoustic wave vibration part) and the first layer wiring pattern on the surface of the multilayer wiring board is narrower (for example, about 10 μm). ) Tends to be designed to be. For this reason, if the surface unevenness of the first layer wiring pattern on the surface of the multilayer wiring board is large, there is a possibility that the wiring pattern and the active surface of the SAW piezoelectric element may come into contact with each other, and there is a problem that the function as a filter cannot be secured.

  The present invention has been made in view of the above problems, and even when using a coreless construction method in which wiring layers are stacked on only one side of a copper foil to form a multilayer, the amount of warpage can be suppressed, and multilayer wiring with good workability and yield. An object of the present invention is to provide a substrate and a manufacturing method thereof.

The present invention relates to the following.
1. A first layer wiring pattern formed by circuit processing of the metal foil A, an insulating resin layer disposed on the first layer wiring pattern, and at least one layer having a wiring pattern disposed on the insulating resin layer A wiring layer on the high layer side, wherein the wiring pattern on the high layer side is formed by circuit processing a conductor layer formed by plating a metal foil on the insulating resin layer, The wiring pattern on the highest layer side is thicker than the first layer wiring pattern, or the conductor layer remaining rate of the wiring pattern on the highest layer side is larger than that of the first layer wiring pattern, or the insulating resin on the first layer wiring pattern A multilayer wiring board formed such that the insulating resin layer on the highest layer side is thinner than the upper layer.
2. In the above 1, the multilayer wiring board is formed so that the wiring pattern is thicker, the conductor layer remaining rate of the wiring pattern is larger, or the insulating resin layer is thinner as going to the higher layer side.
3. 3. The multilayer wiring board according to 1 or 2, wherein a mechanical treatment is applied to the highest conductive layer so that the conductive layer extends in a planar direction.
4). On the metal foil of the core substrate, the metal foil A is directly stacked, and an insulating resin layer and at least one wiring layer on the upper layer side having a wiring pattern arranged on the insulating resin layer are formed thereon. Further, by laminating an insulating resin layer and a conductor layer for forming a wiring layer on the higher layer side, a metal foil A directly in contact with the metal foil of the core substrate, a wiring layer on the metal foil A, A step of forming a multilayer substrate having an insulating resin layer and a conductor layer formed on the wiring layer; and a step of separating the core substrate and the multilayer substrate at an interface between the metal foil and the metal foil A of the core substrate. Then, by processing the metal foil A and the conductor layer of the multilayer substrate, the first layer wiring pattern formed by processing the metal foil A on one side and the conductor layer on the other side are processed. A high-layer wiring pattern Forming a multilayer wiring board having a thickness higher than the first layer wiring pattern or higher than the first layer wiring pattern. A method for manufacturing a multilayer wiring board, wherein the conductor layer residual ratio of the wiring pattern on the side is large, or the insulating resin layer on the highest layer side is thinner than the insulating resin layer on the first layer wiring pattern.
5). On the metal foil of the core substrate, the metal foil A is directly stacked, and an insulating resin layer and at least one wiring layer on the upper layer side having a wiring pattern arranged on the insulating resin layer are formed thereon. A metal foil A that is in direct contact with the metal foil of the core substrate, a wiring layer on the metal foil A, and A step of forming a multilayer substrate having an insulating resin layer and a conductor layer formed on the wiring layer, a step of processing the conductor layer of the multilayer substrate, and an interface between the metal foil and the metal foil A of the core substrate Then, a step of separating the core substrate and the multilayer substrate, and a first layer wiring pattern formed by circuit processing of the metal foil A on one side by circuit processing of the metal foil A of the multilayer substrate And the other conductor layer is circuit processed Forming a multilayer wiring board having a high-layer side wiring pattern formed, wherein the thickness of the wiring layer on the highest layer side is thicker than the first layer wiring pattern, or The conductive layer remaining rate of the wiring layer on the highest layer side is larger than that of the first layer wiring pattern, or the insulating resin layer on the highest layer side is thinner than the insulating resin layer on the first layer wiring pattern. A method for manufacturing a multilayer wiring board.
6). In 4 or 5 above, the multilayer wiring board is formed such that the wiring pattern is thicker, the conductor layer remaining rate of the wiring pattern is larger, or the insulating resin layer is thinner as going to the higher layer side. .
7). 7. The method for producing a multilayer wiring board according to any one of 4 to 6, wherein the highest conductive layer is subjected to mechanical treatment so that the conductive layer extends in a planar direction.

  According to the present invention, it is possible to suppress the amount of warp even when using a coreless construction method in which wiring layers are stacked on only one side of a copper foil to form a multilayer, and to provide a multilayer wiring board with good workability and yield and a manufacturing method thereof. Can do.

Sectional drawing of the multilayer wiring board of this invention and an electronic component module produced using this is shown. 1 is a sectional view of a multilayer wiring board according to the present invention. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown. A part of manufacturing process of the multilayer wiring board of the present invention is shown.

  The multilayer wiring board of the present invention is a board for mounting electronic component elements. In the present invention, an electronic component element is a surface-mount type electronic component that is connected to a connection terminal on a wiring board by flip-chip connection or wire bond connection, such as a semiconductor element, SAW piezoelectric element, or PA (power amplifier) element. Refers to an element. There is no particular limitation as long as the electronic component element is mounted by flip chip connection or wire bond connection. For example, a SAW piezoelectric element or PA (power amplifier) element is mounted, so-called SAW filter package or PA module. As a member for forming a communication module such as a mobile phone, it is preferably used for a bare chip mounting application mainly in a communication module such as a mobile phone.

  As one form of the multilayer wiring board of the present invention, as shown in FIGS. 1 and 2, a first layer wiring pattern 8 formed by circuit processing of a metal foil A19, and on the first layer wiring pattern 8 are provided. A multilayer wiring board 1 having an arranged insulating resin layer and at least one high-layer wiring layer having a wiring pattern arranged on the insulating resin layer, wherein the high-layer wiring pattern includes: A conductive layer formed by metal foil and plating on the insulating resin layer is formed by circuit processing, and the wiring layer on the highest layer side is thicker than the first layer wiring pattern 8, or the first layer wiring pattern The multilayer wiring board is formed so that the conductor layer remaining rate of the wiring pattern on the highest layer side is higher than 8, or the insulating resin layer on the highest layer side is thinner than the insulating resin layer on the first layer wiring pattern 8. And the like.

  The embodiment of the multilayer wiring board according to the present invention will be described in more detail. In the example shown in FIGS. 1 and 2, the first layer wiring pattern 8 including the flip chip connection terminal 5 on one surface is a first insulating resin. The first filled via 10 formed in the layer 9 is used as an interlayer connection, and has a wiring structure electrically connected to the second layer wiring pattern 11, and further the second filled via 13 formed in the second insulating resin layer 12 is provided. It has a wiring structure electrically connected to the third layer wiring pattern 14 as an interlayer connection, and further includes a portion that becomes the back electrode 7 with the third filled via 16 formed in the third insulating resin layer 15 as an interlayer connection. The multilayer wiring board 1 includes a wiring structure electrically connected to the fourth layer wiring pattern 17. The first layer wiring pattern 8 is formed by processing the metal foil A19, and the wiring patterns on the higher layer side (the second layer wiring pattern 11, the third layer wiring pattern 14, and the fourth layer wiring pattern 17) are: A first layer conductor layer 30, a second layer conductor layer 33, and a third layer conductor layer 35 constituted by the metal foils B20, C23, D24 and a plating layer 31 formed at the time of interlayer connection formed on the metal foils B20, C23, D24. It is formed by forming a circuit. The first layer wiring pattern 8 and the fourth layer wiring pattern 17 which are the outermost layers are provided with protective plating 22 thereon, and a flip chip for mounting the electronic component element 3 immediately above the first filled via 10. A connection terminal 5 is provided. Although details of the thickness of each wiring pattern, the conductor layer remaining rate of each wiring pattern, and the thickness of each insulating resin layer are not shown, the thickness of the wiring patterns 11, 14, and 17 on the highest layer side of the first layer wiring pattern 8 is thicker. Alternatively, the conductor layer remaining rate of the wiring layers 11, 14, and 17 on the highest layer side than the first layer wiring pattern 8 is larger, or the insulating resin on the highest layer side than the first insulating resin layer 9 on the first layer wiring pattern 8 The layers 12 and 15 are formed to be thin.

  By increasing the thickness of the wiring pattern on the highest layer side from the first layer wiring pattern, curing shrinkage of the insulating resin layer on the highest layer side that occurs when the insulating resin layer on the highest layer side is stacked can be suppressed. . This is because the dimensional change of the wiring pattern is smaller than that of the insulating resin layer. Therefore, by increasing the thickness of the wiring pattern, the dimensional change of the insulating resin layer (in this case, the hardening) This is because the effect of suppressing (shrinkage) is increased. As a result, the difference in shrinkage rate from the cured shrinkage of the insulating resin layer on the lower layer side that has already been cured is reduced, so that the warpage of the entire multilayer wiring board can be suppressed.

  Suppressing the curing shrinkage of the insulating resin layer on the highest layer, which occurs when the insulating resin layer on the highest layer is stacked, by increasing the conductor layer remaining rate of the wiring layer on the highest layer side than the first layer wiring pattern. be able to. This is because the dimensional change of the wiring pattern is smaller than that of the insulating resin layer. By increasing the conductor layer residual rate of the wiring pattern, the dimensional change of the insulating resin layer ( In this case, the effect of suppressing curing shrinkage is increased. As a result, the difference in shrinkage rate from the cured shrinkage of the insulating resin layer on the lower layer side that has already been cured is reduced, so that the warpage of the entire multilayer wiring board can be suppressed.

  Curing shrinkage of the insulating resin layer on the highest layer that occurs when the insulating resin layer on the highest layer side is stacked by making the thickness of the insulating resin layer on the highest layer side thinner than the insulating resin layer on the first layer wiring pattern Can be suppressed. This is because the curing shrinkage of the insulating resin on the high layer side when the insulating resin layer on the high layer side is stacked is larger than the curing shrinkage of the insulating resin on the low layer side that has already been cured, but the thickness of the insulating resin on the highest layer side This is because the dimensional change of the insulating resin layer on the lower layer side becomes dominant due to the fact that is thinner than the lower layer side. Thereby, since the influence of the curing shrinkage of the insulating resin layer on the higher layer side is reduced, it is possible to suppress the warpage of the entire multilayer wiring board.

  It is desirable that the wiring pattern is thicker, the conductor layer remaining rate of the wiring pattern is larger, or the insulating resin layer is thinner as it goes to the higher layer side. Thereby, as described above, the effect by increasing the thickness of the wiring pattern, the effect by increasing the conductor layer residual rate of the wiring pattern, the effect by forming the insulating resin layer to be thin, Since it acts for each wiring layer to be stacked, warping can be suppressed while suppressing distortion inside the multilayer wiring board.

  It is desirable that a mechanical treatment is performed on the highest conductive layer so that the conductive layer extends in the planar direction. Thereby, even if a warp remains in the multilayer wiring board after being separated from the support, the conductor layer subjected to the mechanical treatment extends in the plane direction, so that the warp can be corrected. Examples of the mechanical treatment applied so that the conductor layer extends in the plane direction include buffing and belt sander.

  In the form shown in FIG. 1 and FIG. 2, the first layer wiring pattern 8 including the portion to be the flip chip connection terminal 5 is composed only of the metal foil A19, and an interlayer connection is formed on the upper portion thereof by filled via plating. Also when filled, filled via plating 21a, 21b, 21c is not formed. For this reason, the surface roughness and unevenness | corrugation of metal foil A19 do not expand by the plating layer 31 produced in the case of such an interlayer connection. Here, the plated layer 31 generated at the time of interlayer connection is, for example, when filled via plating for interlayer connection is performed in the via in the conformal method, filled via plating or the like is also formed on the metal foil on the surface. Although the thickness of the conductor layer on the surface increases, it means filled via plating or the like formed on the metal foil at this time. Further, since the thickness of the first conductor layer 30 (shown in FIG. 4) composed of the metal foil A19 is not increased by the plating layer 31 generated at the time of interlayer connection, even when a fine pattern is formed. The metal foil A19 having a thickness corresponding to that can be selected, and it is not necessary to perform half etching or buffing, so that the surface roughness of the metal foil A19 does not increase. Therefore, the surface smoothness of the metal foil A19 can be used almost as it is, and the first layer wiring pattern 8 having excellent surface smoothness can be formed. Even when the protective plating 22 is formed on the first layer wiring pattern including the portion to become the flip chip connection terminal 5, the surface of the first layer wiring pattern 8 is smooth, so the surface of the protective plating 22 formed thereon Can also maintain smoothness. For this reason, since the flip chip connection terminal 5 excellent in surface smoothness can be formed, the multilayer wiring board 1 excellent in flip chip connection can be provided. Moreover, when the flip chip connection terminal 5 is formed as a wire bond connection terminal, the multilayer wiring board 1 excellent in wire bond connectivity can be provided. Here, half-etching refers to a process for facilitating fine circuit processing by reducing the thickness of a conductor layer by etching before forming a wiring pattern by circuit processing.

  Furthermore, in the form shown in FIGS. 1 and 2, the surface of the protective plating 22 on the first layer wiring pattern 8 similarly has smoothness other than the portion that becomes the flip chip connection terminal 5. For this reason, even when the SAW piezoelectric element 3 is mounted as the electronic component element 3, even when the first layer wiring pattern 8 is formed in a region below the active surface 39 (vibration portion of the surface acoustic wave) of the SAW piezoelectric element 3. The filter function of the SAW piezoelectric element 3 can be ensured. For example, in a SAW device used in a high frequency region of 0.45 to 4.0 GHz, the lower surface (active surface 39) of the SAW piezoelectric element 3 mounted on the multilayer wiring board 1 and the multilayer wiring are required in order to reduce the size and thickness. In some cases, the gap (vibration space) provided between the substrate 1 and the protective plating 22 on the first layer wiring pattern 8 is designed to be about 10 μm. For this reason, if the surface unevenness of the protective plating 22 on the first layer wiring pattern 8 on the surface on which the SAW piezoelectric element 3 is mounted is adjusted to have a surface smoothness of less than 8 μm, it is about 0.45 to 4.0 GHz. When used as a substrate for a high-frequency SAW filter, it is effective to ensure the filter function.

  In the form shown in FIGS. 1 and 2, the first layer wiring pattern 8 can be formed only by processing the metal foil A19 by etching or the like. Therefore, if the thin metal foil A19 is used, the wiring pattern height increases. Densification can be achieved. Further, since the plating layer 31 generated at the time of interlayer connection is not formed on the first layer wiring pattern 8, even when a fine wiring pattern is formed, the conductor layer is formed by so-called half etching, buffing or the like. Since a process for reducing the thickness of the wiring board 1 is not required, the number of steps is not increased and the inexpensive multilayer wiring board 1 can be provided. In addition, when half etching or buffing is performed, the surface roughness of the conductor layer increases, so that these steps are not necessary, not only reducing man-hours, but also protecting the first layer wiring pattern 8 and the protection thereon. It has the effect of maintaining the surface smoothness of the surface of the plating 22. As described above, according to the present invention, the multilayer wiring board suitable for the electronic component element 3 mounting application, in which the surface smoothness of the protective plating 22 on the first layer wiring pattern 8 including the flip chip connection terminal 5 is particularly required. 1 can be provided.

  The multilayer wiring board of the present invention is a board on which electronic component elements are mounted. For example, a SAW piezoelectric element or a PA (power amplifier) element is mounted to form a communication module such as a so-called SAW filter package or PA module. It can be used as a member. It is mainly used for bare chip mounting applications in communication modules such as mobile phones. The first layer wiring pattern of the present invention has a high density, and the protective plating formed thereon has a smooth surface. This is desirable because it can be done.

  In the present invention, the conductor layer is a metal foil or a metal foil that is provided on the surface of the insulating resin layer and has a plating layer formed at the time of interlayer connection, or a state before circuit processing. . The conductor layer remaining rate is the ratio of the area of the wiring pattern remaining after circuit processing to the area of the conductor layer before circuit processing. The wiring pattern means a pattern in which wiring and connection terminals are formed by processing this conductor layer, and does not include, for example, a pattern in which an opening for a conformal mask is provided. For example, in the conformal method, the plated layer generated in the interlayer connection is a filled via plating or the like for the interlayer connection in the via, and the filled via plating or the like is also formed on the surface metal foil. Although the thickness of the layer is increased, it means filled via plating or the like formed on the metal foil at this time. Further, the first layer wiring pattern refers to a wiring pattern provided on the surface layer (first layer) on the side having a connection terminal with the electronic component element among the above wiring patterns. The wiring pattern of each layer is formed so as to include a position immediately above the interlayer connection formed by filled vias. The wiring layer refers to a single-layer wiring board having an insulating resin layer and a wiring pattern and constituting a multilayer wiring board.

  Of the wiring patterns located immediately above the interlayer connection formed by filled vias, the first layer wiring pattern is formed of metal foil A. That is, in the first layer wiring pattern, the plating layer generated at the time of interlayer connection is not formed on the upper part of the metal foil A before circuit processing, the metal foil A is exposed, and only the metal foil A is the first. A layer conductor layer is formed, and the first layer wiring pattern is formed by circuit processing of the first layer conductor layer. For this reason, the first layer wiring pattern can use the surface smoothness of the metal foil A almost as it is, and can have excellent surface smoothness. For this reason, the surface of the protective plating formed on the first layer wiring pattern is also smoothed. Further, since the first layer wiring pattern is processed by etching only the metal foil A, the conductor layer is thin, so that a fine wiring pattern can be formed. For this reason, the process of reducing the thickness of the conductor layer by half etching, buffing or the like before the circuit processing is unnecessary.

  As a circuit processing method for the wiring patterns of each layer excluding the first layer wiring pattern, a circuit forming method used for a general electronic component element mounting substrate can be used. Examples of such a circuit forming method include a subtractive method and a semi-additive method.

  As the metal foil A used in the present invention, those used for a general electronic component element mounting substrate can be used, and a copper foil is particularly desirable from the viewpoint of electrical characteristics, circuit workability, and the like. Examples of such a copper foil include 3EC-VLP-12 (trade name, manufactured by Mitsui Kinzoku Mining Co., Ltd.). In addition, the metal foil may be replaced with a metal foil made of aluminum, brass, nickel, iron or the like alone, an alloy or a composite foil, or a copper foil plated or evaporated with a metal such as aluminum, nickel, silver, or gold. it can.

  In the present invention, the interlayer connection refers to one that electrically connects the wiring patterns of each layer through interlayer connection holes provided in the insulating resin layer, and includes those formed by so-called filled via plating. Examples of the filled via plating include filled via plating using electrolytic copper plating used for a general electronic component element mounting substrate.

  In the present invention, the filled via is an interlayer connection formed by filled via plating, and the inside of the interlayer connection hole is filled with a metal formed by filled via plating. The filled via can be formed by processing the insulating resin layer with a laser or the like to form an interlayer connection hole having a diameter of about 1 μm to 300 μm and then filling the interlayer connection hole with filled via plating.

  The insulating resin layer used in the present invention is intended to electrically insulate the wiring patterns in each layer and in the same layer, as well as to bond the conductor layers of each layer, or to support the wiring pattern of each layer It is. The general thing used in manufacture of the board | substrate for a general electronic component element mounting can be used. For example, a thermosetting resin prepreg, a material mainly composed of a high molecular weight epoxy resin, or a thermosetting liquid or sheet-like insulating resin layer mainly composed of BT resin can be used. As thermosetting resin prepregs, GEA-679FG (trade name, manufactured by Hitachi Chemical Co., Ltd.) mainly composed of high molecular weight epoxy resin and GHPL-830NX Type A (Mitsubishi Gas Chemical Co., Ltd.) mainly composed of BT resin. SFX513 (trade name, manufactured by Shin-Etsu Chemical Co., Ltd.) and the like as the liquid adhesive, and AS-3000 and AS2600W (both manufactured by Hitachi Chemical Co., Ltd.) as the sheet adhesive. ) (Trade name), high-performance adhesive sheet for electronic parts TAS (trade name, manufactured by Toray Industries, Inc.) and the like, but are not limited thereto. One type of insulating resin layer may be used alone, or two or more types of insulating resin layers may be stacked, and liquid types may be mixed and used.

  Only on one surface of the metal foil A, an insulating resin layer, wiring patterns, and interlayer connections for connecting the respective wiring patterns are stacked and formed, and the first layer wiring pattern is formed by processing the metal foil A. To do. That is, multilayering is performed only on one surface of the metal foil A, and circuit processing is performed on the other surface of the metal foil A as it is without multilayering. On the other surface of the metal foil A, the insulating resin layer and the wiring pattern are not formed, and the initial surface state of the metal foil A is maintained. By processing this metal foil A, the first layer wiring pattern is formed of the metal foil A among the wiring patterns located immediately above the interlayer connection. Thereby, the 1st layer wiring pattern can use the surface smoothness of metal foil A as it is, and can be provided with the outstanding surface smoothness. For this reason, the surface smoothness of the protective plating formed on the first layer wiring pattern is also excellent. Further, since the first layer wiring pattern is processed by etching only the metal foil A, the conductor layer is thin, so that a fine wiring pattern can be formed. For this reason, the process of reducing the thickness of the conductor layer by half etching, buffing or the like before the circuit processing is unnecessary.

  It is desirable to have nickel plating or nickel plating and gold plating as protective plating on the first layer wiring pattern including the portion to be the connection terminal. It is more desirable to perform gold plating after performing palladium plating on nickel plating in terms of improving the connection reliability with the electronic component element. Silver plating may be used instead of gold plating. As these plating methods, electroless plating, electroplating, or displacement plating used for an electronic component element mounting substrate can be used. In addition, protective plating means the plating layer provided in the upper part of the wiring pattern after circuit formation, in order to protect a wiring pattern and to provide flip chip connectivity and wire bond connectivity.

  The metal foil A constituting the first layer wiring pattern is desirably a copper foil having a thickness of 1 to 18 μm. In the multilayer wiring board of the present invention, since the first layer wiring pattern is formed by processing the metal foil A, an appropriate thickness of the metal foil A can be selected, but the metal foil A has a thickness of 1 With a copper foil of ˜18 μm, for example, it is easy to form a high-density wiring pattern with a line / space of 30 μm / 30 μm or less.

  It is desirable that the first layer wiring pattern located immediately above the interlayer connection forms a flip chip connection terminal or a wire bond connection terminal. In the multilayer wiring board of the present invention, since the first layer wiring pattern is formed by processing the metal foil A, the surface state of the metal foil A is maintained, so that the surface smoothness of the metal foil A is maintained as it is. Can be used. For this reason, since the wiring pattern formed with this metal foil A is formed as a flip chip connection terminal or a wire bond connection terminal, the surface smoothness of the protective plating formed on the wiring pattern is excellent. It is possible to provide a multilayer wiring board having excellent properties and wire bond connectivity.

  In the present invention, the connection terminal is a terminal for making an electrical connection with the electronic component element by bumps or wire bonds, similar to those used in a general electronic component element mounting substrate. The connection terminal is formed by covering the surface of the first layer wiring pattern formed of the metal foil A with a protective plating such as gold or silver, so that workability and reliability when connecting with bumps, wire bonds, or solder are used. It is preferable in terms of properties.

  The protective plating surface provided on the upper part of the connection terminal is preferably gold plating. Thereby, when using a gold bump as a bump used for flip chip connection, the connection between the connection terminal and the bump can be strengthened. Similarly, when a gold wire is used for wire bond connection, the connection between the connection terminal and the gold wire can be strengthened. Furthermore, solder wettability at the time of soldering can be ensured. Moreover, it is desirable to provide nickel plating as a base for gold plating, and it is desirable to perform gold plating after providing palladium plating on the nickel plating. In the present invention, the first layer wiring pattern including a portion to be a connection terminal is formed using a metal foil A such as a copper foil. However, by providing nickel plating as a base for gold plating, copper is a gold plating surface. It can be suppressed that the connection reliability with the bump is lowered.

  The thickness of the gold plating is desirably 0.01 to 3 μm. Thereby, the gold plating can ensure the bonding strength with the bumps, and can prevent oxidation of the underlying nickel plating. The thickness of the underlying nickel plating is preferably 1 to 20 μm. Furthermore, the thickness of the palladium plating provided on the nickel plating is preferably 0.01 to 1 μm. Thereby, since nickel plating suppresses the spreading | diffusion to the gold plating surface of copper, the reliability of bump connection is securable.

  In the present invention, the back electrode refers to an electrode provided on the surface (one surface) opposite to the surface (one surface) on which the connection terminal of the multilayer wiring board is provided, and is produced using the multilayer wiring board of the present invention. When a communication module or the like is mounted on another substrate, it is used to connect with a mounting terminal on the other substrate. The connection between the back electrode and the mounting terminal of another substrate can be performed by pressure bonding using a conductive adhesive or soldering.

  As one form of the manufacturing method of the multilayer wiring board of this invention, metal foil A is directly piled up on the metal foil of a core board | substrate, and it has the wiring pattern arrange | positioned on this on the insulating resin layer and this insulating resin layer. At least one high-layer wiring layer was formed, and an insulating resin layer and a conductor layer for forming a high-layer wiring layer were further laminated thereon, thereby directly contacting the metal foil of the core substrate. Forming a metal foil A, a wiring layer on the metal foil A, a multilayer substrate having an insulating resin layer and a conductor layer formed on the wiring layer, the metal foil of the core substrate and the metal foil A, A step of separating the core substrate and the multi-layer substrate at the interface, and by processing the metal foil A and the conductor layer of the multi-layer substrate, the metal foil A is formed on one side by circuit processing. One layer wiring pattern, the other conductor layer Forming a multilayer wiring board having a wiring pattern on the higher layer side formed by circuit processing, the method of manufacturing a multilayer wiring board having a thickness of the wiring layer on the highest layer side than the first layer wiring pattern. Is thicker, or the conductor layer remaining rate of the wiring layer on the highest layer side than the first layer wiring pattern is large, or the thickness of the insulating resin layer on the highest layer side becomes thinner than the insulating resin layer on the first layer wiring pattern. The manufacturing method of the multilayer wiring board formed in this way is mentioned. Here, the circuit processing of the conductor layer formed on one surface of the multilayer substrate may be performed before the step of separating the core substrate and the multilayer substrate. In the present invention, the multilayer substrate refers to a substrate having a metal foil A on one surface, a conductor layer on the other surface, and at least one wiring layer inside.

  One form of the manufacturing method of the multilayer wiring board of this invention is demonstrated more concretely using figures. First, as shown in FIG. 3, a core substrate 25 having a metal foil 38 on both sides and a metal foil A19 to be a first layer conductor layer 30 (shown in FIG. 4) are prepared (step (1)). Then, the metal foil A19 to be the first conductor layer 30 as the surface layer is directly overlaid on the metal foil 38 of the core substrate 25. As the metal foil A19, one having a size slightly smaller than the metal foil 38 of the core substrate 25 is used. Thereafter, the first insulating resin layer 9 and the metal foil B20 are laminated on one surface of the metal foil A19 (step (2)). The first insulating resin layer 9 has a size that is slightly larger than the metal foil A19. In such a laminated state, the other surface of the metal foil A19 and the metal foil 38 of the core substrate 25 are in contact with each other and are not bonded to each other. The protruding first insulating resin layer 9 and the metal foil 38 of the core substrate 25 are bonded. For this reason, since the other surface of the metal foil A19 (the surface of the core substrate 25 on the metal foil 25 side) is protected by the metal foil 38 of the core substrate 25, in the subsequent manufacturing process of the multilayer wiring substrate 1 However, the other surface of the metal foil A19 is maintained in its original state. In the embodiment of FIG. 3, the surface of the metal foil A19 is protected by the metal foil 38 of the core substrate 25. However, if the surface of the metal foil A19 can be protected and can be peeled off, the material / The method is not particularly limited, and a resin film or the like can also be used. In the embodiment of FIG. 3, the metal foil A19 is overlapped on the metal foils 38 on both surfaces of the core substrate 25 to perform the multilayering process. In this case, only one multilayering process is performed, and two sheets are formed. The multilayer wiring board 1 can be manufactured, and the production efficiency is good. In addition, since the multi-layer process is performed on both the upper and lower sides of the core substrate 25, warpage hardly occurs and trouble in the manufacturing process hardly occurs. Furthermore, since the core substrate 25 serves as a support, even in the case of the thin multilayer wiring substrate 1, handling in the manufacturing process is easy and workability is improved. In addition, when the rigidity of the core board | substrate 25 used as a support body is large, the metal foil A19 can be piled up only on one metal foil 38 of the core board | substrate 25, and a multilayering process can also be performed.

  Next, as shown in FIG. 4, a first interlayer connection hole 29 extending from the metal foil B20 to the first conductor layer 30 is formed in the first insulating resin layer 9 (step (3)). The first interlayer connection hole 29 is formed by forming an opening in the metal foil B20 by etching and irradiating the opening with a carbon dioxide gas laser or the like, or directly irradiating a UV laser or the like without forming an opening in the metal foil B20. The direct laser method can be used.

  Next, as shown in FIG. 4, filled via plating 21a for electrically connecting the first layer conductor layer 30 and the metal foil B20 is performed in the first interlayer connection hole 29 and on the metal foil B20 (step). (4)). A first filled via 10 is formed in the first interlayer connection hole 29, and a plating layer 31 generated at the time of interlayer connection is formed on the metal foil B20. Further, the second conductor layer 33 is formed by both the metal foil B20 and the plating layer 31 generated at the time of interlayer connection.

  Next, as shown in FIG. 5, the second layer conductor layer 33 (shown in FIG. 4) after filled via plating is processed to form the second layer wiring pattern 11 (step (5)). Since the thickness of the plated layer 31 generated at the time of interlayer connection is added to the thickness of the copper foil B20, the second layer conductor layer 33 after filled via plating has a circuit with respect to the conductor layer having a thickness obtained by combining these two. Processing is required. When it is necessary to reduce the thickness of the second conductor layer 33, half etching, buffing or the like is performed before circuit processing.

  Next, steps (2) to (5) are repeated as many times as necessary on the second layer wiring pattern 11 (step (6)). Specifically, in this step (6), as shown in FIG. 5, the second insulating resin layer 12 and the metal foil C23 are laminated on the second-layer wiring pattern 11 (step (2)). As shown in FIG. 6, a second interlayer connection hole 32 extending from the metal foil C23 to the second conductor layer 33 is formed in the second insulating resin layer 12 (step (3)), and the second interlayer connection hole is formed. Filled via plating 21b for electrically connecting the second layer conductor layer 33 (shown in FIG. 4) and the metal foil C23 is performed inside and on the metal foil C23, and the second filled via 13 and the third layer conductor. Next, as shown in FIG. 7, the third-layer conductor layer 35 (shown in FIG. 6) after filled via plating is subjected to circuit processing to form a third-layer wiring. After the pattern 14 is formed (step (5)), the third insulating resin layer 1 is further formed on the third layer wiring pattern 14. And the metal foil D24 are laminated (step (2)), and the third interlayer connection hole 34 extending from the metal foil D24 to the third conductor layer 35 is formed in the third insulating resin layer 15 (step (3)). The filled via plating 21c for electrically connecting the third layer conductor layer 35 and the metal foil D24 is performed in the third interlayer connection hole 34 and on the metal foil D24, and the third filled via 16 and the fourth layer conductor layer are formed. 37 (step (4)). Next, the fourth layer conductor layer 37 after filled via plating is processed to form a fourth layer wiring pattern 17 (shown in FIG. 9) (step (5)). The circuit processing of the fourth conductor layer 37 in this step (5) may be performed before the core substrate 25 and the multilayer substrate 40 are separated, or these are separated as shown in FIG. It may be performed later or may be performed simultaneously with the circuit processing of the first conductor layer 30 described later.

  Next, as shown in FIG. 8, the core substrate 25 and the multilayer substrate 40 are separated, and as shown in FIG. 9, the metal foil A <b> 19 that is the first layer conductor layer 30 is processed into a first layer wiring. By forming the pattern 8, the connection terminal 5 is formed immediately above the first interlayer connection hole 29 subjected to filled via plating (step (7)). On the metal foil A19, which is the first layer conductor layer 30, the plating layer 31 generated during the interlayer connection does not occur even during the interlayer connection. Therefore, the thickness of the first layer conductor layer 30 is the metal foil A19. It becomes the thickness itself. For this reason, circuit processing of the first conductor layer 30 can be performed only by etching the metal foil A19. Therefore, if the thickness of the metal foil A19 is set to 1 μm to 18 μm, a high-density wiring pattern is formed. It becomes possible. For this reason, it is not necessary to perform half etching or buffing on the first conductor layer 30, so that the surface smoothness is maintained. The circuit processing of the first conductor layer 30 in the step (7) may be performed simultaneously with the circuit processing of the fourth conductor layer 37 in the step (5). Although details of the thickness of each wiring pattern, the conductor layer remaining rate of each wiring pattern, and the thickness of each insulating resin layer are not shown, the thickness of the wiring patterns 11, 14, and 17 on the highest layer side of the first layer wiring pattern 8 is not shown. Is thicker or the conductor layer remaining rate of the wiring patterns 11, 14, and 17 on the highest layer side than the first layer wiring pattern 8 is larger, or on the highest layer side than the first insulating resin layer 9 on the first layer wiring pattern 8. The insulating resin layers 12 and 15 are formed to be thin.

  Next, as shown in FIG. 9, the protective plating 22 is formed on the connection terminals 5 formed immediately above the first interlayer connection holes 29. As the protective plating 22, it is desirable to have nickel plating or nickel plating and gold plating. Thereby, the 1st wiring pattern 8 can be protected and flip chip connectivity and wire bond connectivity can be provided. Further, it is more desirable to form palladium plating between nickel plating and gold plating because the connection reliability with the electronic component element 3 is improved. Silver plating can also be used instead of gold plating.

  Hereinafter, examples of the present invention will be described with reference to FIGS. 3 to 9, but the present invention is not limited to these examples.

Example 1
As shown in FIG. 3, a double-sided copper-clad laminate (MCL-E679FG manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 18 μm and a thickness of 0.20 mm was prepared as the core substrate 25 serving as a support. Next, a copper foil (3EC-VLP-12 manufactured by Mitsui Kinzoku Co., Ltd.) having a size slightly smaller than the core substrate 25 and having a thickness of 12 μm as metal foil A19 is formed on both sides of the core substrate 25 in plan view. The copper foil glossy surface was disposed on the core substrate 25 evenly on the left and right sides. Next, a prepreg having a thickness of 0.03 mm (a prepreg made of glass cloth as a base material and impregnated with an epoxy resin, GEA-679FG) as a first insulating resin layer 9, and a metal foil A structure in which a copper foil having a thickness of 5 μm (MT18SDH5 manufactured by Mitsui Kinzoku Co., Ltd.) was sequentially stacked as B20 was produced. These were laminated by heat and pressure treatment (185 ° C., 3 MPa, press molding treatment for 90 minutes) to produce a laminate a26.

  An etching resist was laminated on the laminate a26, a negative mask having a desired pattern was applied, and a circuit pattern was printed by a parallel exposure machine. Thereafter, development was performed with an aqueous sodium carbonate solution, and unnecessary copper foil was removed by etching with an aqueous ferric chloride solution. Thereafter, the etching resist is removed with an aqueous sodium hydroxide solution, and a conformal mask and a laser are formed on a portion where the first interlayer connection hole 29 for connection with the metal foil A19 to be the first conductor layer 30 is installed. A position recognition pattern during processing was formed.

  As shown in FIG. 4, the first interlayer connection hole 29 is formed on the laminated plate a26 using a carbon dioxide gas laser under the conditions of a beam irradiation diameter of 0.2 mm, a frequency of 500 Hz, a pulse width of 10 μs, and the number of irradiations of 3 shots. Was processed. Thereafter, desmear treatment was performed using a sodium permanganate aqueous solution having a temperature of 80 ± 5 ° C. and a concentration of 55 ± 10 g / L, and after plating with a thickness of 0.4 to 7.0 μm by electroless copper plating, The surface was hand-polished using abrasive paper # 1200, and filled via plating 21a was formed on the first interlayer connection hole 29 and the surface by electrolytic copper plating. By these electroless copper plating and electrolytic copper plating, plating with a thickness of 15 to 30 μm (plating layer 31 generated at the time of interlayer connection) was formed on the surface of the metal foil B20. Thereafter, soft etching was performed to a copper thickness of 12 μm using a soft etching solution (MEC Power Etch HE-7002A manufactured by MEC Co., Ltd., sulfuric acid, hydrogen peroxide) to form the second layer conductor layer 33.

  As shown in FIGS. 4 and 5, an etching resist was laminated on the second conductor layer 33, a negative mask having a desired pattern was applied, and a circuit pattern was printed by a parallel exposure machine. Thereafter, development was performed with an aqueous sodium carbonate solution, and unnecessary copper foil was removed by etching with an aqueous ferric chloride solution. Thereafter, the etching resist was removed with an aqueous sodium hydroxide solution to form a second layer wiring pattern 11 serving as an inner layer pattern. The conductor layer remaining rate of the second layer wiring pattern 11 was 20%. Then, it roughens using a copper surface roughening liquid (Mc bond mid Co., Ltd. multibond MB-100), and the 0.03 mm-thick prepreg (Hitachi Chemical Industry Co., Ltd. GEA-) used as the 2nd insulating resin layer 12 679FG) and a copper foil (MT18SDH5 manufactured by Mitsui Kinzoku Co., Ltd.) having a thickness of 5 μm to be the metal foil C23 were sequentially stacked. These were laminated by heat and pressure treatment (185 ° C., 3 MPa, press molding treatment for 90 minutes) to produce a laminate b27.

  As shown in FIG. 6, a conformal mask and a position recognition pattern at the time of laser processing were formed on the laminate b27 in the same manner as for the laminate a26. Next, as in the case of the laminated plate a26, the second interlayer connection hole 32 is processed, and after desmear treatment, electroless copper plating, and manual surface polishing, the second interlayer connection is performed by electrolytic copper plating. Filled via plating 21b was formed on the hole 32 and the surface, and then soft etching was performed to a copper thickness of 12 μm to form a third layer conductor layer 35.

  As shown in FIGS. 6 and 7, the third-layer wiring pattern 14 serving as the inner layer pattern was formed on the third-layer conductor layer 35 in the same manner as for the second-layer conductor layer 33. The 14 conductor layer remaining rate of the third layer wiring pattern was 20%. Thereafter, roughening is performed in the same manner as in the case of the second layer wiring pattern 11, and a prepreg (GEA-679FG manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 0.03 mm to be the third insulating resin layer 15, and a metal foil The structure which laminated | stacked the copper foil (Mitsui Metals Co., Ltd. MT18SDH5) of thickness 5micrometer used as D24 one by one was produced, and these were laminated | stacked by heat-pressing process (185 degreeC, 3 Mpa, 90 minutes press molding process). Thus, a laminated plate c36 was produced.

  As shown in FIG. 7, a conformal mask and a position recognition pattern at the time of laser processing were formed on the laminate c36 in the same manner as for the laminate a26 and the laminate b27. Next, in the same manner as for the laminated plate a26 and the laminated plate b27, the third interlayer connection hole 34 is processed, and after desmear treatment, electroless copper plating, and hand surface polishing, by electrolytic copper plating, Filled via plating 21c was formed on the third interlayer connection hole 34 and the surface, and then soft etching was performed to each copper thickness of 15 μm, 20 μm, and 25 μm to form a fourth layer conductor layer 37. In this example, the multilayer substrate 40 having up to the fourth layer conductor layer 37 was produced. However, by changing the number of wiring layers to be stacked, a substrate having a three-layer structure, a four-layer structure,. Is possible.

  As shown in FIG. 8, the laminated board c36 on which the fourth layer conductor layer 37 is formed is cut by a router processing machine within the range where the metal foil A19 is disposed. Thereby, the multilayer substrate 40 as a product is separated from the core substrate 25.

  The first layer wiring pattern 8 and the fourth layer wiring pattern 17 were formed on the metal foil A19 (first layer conductor layer 30) and the fourth layer conductor layer 37 of the multilayer substrate 40 after the separation, respectively. The conductor layer remaining rates of the first layer wiring pattern 8 and the fourth layer wiring pattern 17 were both 20%. Next, the solder resist 18 was formed, and the nickel / gold plating that was the protective plating 22 was performed. Finally, the multilayer wiring board 1 having the product size was formed by subjecting the multilayer wiring board 1 to which the protective plating 22 was applied to the outer shape to the product size.

(Comparative example)
In the same manner as in Example 1, the third interlayer connection hole 34 is processed in the third-layer conductor layer 35, desmear treatment, electroless copper plating, and surface manual polishing are performed. Filled via plating 21c was formed on the interlayer connection hole 34 and the surface. Then, unlike Example 1, soft etching was performed to the copper thickness of 12 micrometers about the 2nd layer conductor layer-the 4th layer conductor layer. Thereafter, a multilayer wiring board was produced in the same manner as in Example 1. That is, the first embodiment is different from the first embodiment in that the thickness of the first layer wiring pattern is equal to the thickness of all the wiring patterns on the highest layer side.

(Summary of Example 1 and Comparative Example)
For Example 1 and Comparative Example, the multilayer wiring board immediately after separation from the core substrate, the multilayer wiring board after solder resist formation (both board sizes 500 × 500 mm), and the multilayer wiring board after external processing (product size 100 × Table 1 shows the measurement results of the respective warpage amounts of 100 mm). In any step from Table 1, when the thickness of the fourth-layer wiring pattern on the highest layer side is thick, the warpage amount becomes smaller than that of Comparative Example 1, and the warpage amount increases as the thickness of the fourth-layer wiring pattern increases. The effect of decreasing was great. Further, when the thickness of the wiring pattern is increased as it goes to the higher layer side, the amount of warpage is further small.

(Example 2)
A multilayer wiring board was produced in the same manner as in Example 1. However, in Example 2, the total thickness from the first layer wiring pattern to the fourth layer wiring pattern is 12 μm, and the conductor layer remaining rate of the fourth layer wiring pattern is 30%, 50%, 70%, 90%. This is different from the first embodiment.

(Summary of Example 2 and Comparative Example)
For Example 2 and Comparative Example, the multilayer wiring board immediately after separation from the core substrate, the multilayer wiring board after forming the solder resist (both board sizes of 500 × 500 mm), and the multilayer wiring board after external processing (product size of 100 × Table 2 shows the measurement results of the respective warpage amounts of 100 mm). From Table 2, the amount of substrate warpage when the conductor layer residual ratio of the fourth-layer wiring pattern was increased was reduced. Moreover, when the conductor layer residual ratio of the wiring pattern was increased as it went to the higher layer side, the amount of warpage was even smaller.

(Example 3)
A multilayer wiring board was produced in the same manner as in Example 1. However, in Example 3, all the thicknesses from the wiring pattern to the fourth layer wiring pattern were set to 12 μm, and the thickness of the fourth insulating resin layer was made thinner than that of the first insulating resin layer. Is different.

(Summary of Example 3 and Comparative Example)
For Example 3 and Comparative Example, the multilayer wiring board immediately after separation from the core substrate, the multilayer wiring board after forming the solder resist (both board sizes 500 × 500 mm), and the multilayer wiring board after external processing (product size 100 × Table 3 shows the measurement results of the respective warpage amounts of 100 mm). From Table 3, the amount of substrate warpage when the thickness of the prepreg used for the third insulating resin layer was made thinner than that of the first insulating resin layer was reduced. In addition, the amount of warpage was reduced when the thick prepreg was formed in order from the first insulating resin layer.

Example 4
After hand polishing after electroless copper plating to the first interlayer connection hole 29, or after hand polishing after electroless copper plating to the second layer interlayer connection hole 32, or after electroless copper plating to the third interlayer connection hole 34 Instead of the manual polishing, mechanical polishing (Vabro Industry V3 # 600) was performed with the combinations shown in Table 4 on the surface after electroless copper plating on each interlayer connection hole. The total thickness from the first layer wiring pattern to the fourth layer wiring pattern was 12 μm. Otherwise, a multilayer wiring board was produced in the same manner as in Example 1.

(Summary of Example 4 and Comparative Example)
From Table 4, the amount of substrate warpage when mechanical polishing was applied was lower than that during manual polishing. Further, the amount of warpage of the substrate when all the layers after the second layer were mechanically polished was further improved.

DESCRIPTION OF SYMBOLS 1 ... Multilayer wiring board, 2 ... Communication module, 3 ... Electronic component element or SAW piezoelectric element, 4 ... (For flip chip connection) Bump, 5 ... (Flip chip) connection terminal, 6 ... Resin for molding, 7 ... Back surface Electrode, 8 ... 1st layer wiring pattern, 9 ... 1st insulating resin layer, 10 ... 1st filled via, 11 ... 2nd layer wiring pattern, 12 ... 2nd insulating resin layer, 13 ... 2nd filled via, 14 ... 3rd Layer wiring pattern, 15 ... third insulating resin layer, 16 ... third filled via, 17 ... fourth layer wiring pattern, 18 ... solder resist, 19 ... metal foil A, 20 ... metal foil B, 21a, 21b, 21c ... filled via Plating, 22 ... Protective plating, 23 ... Metal foil C, 24 ... Metal foil D, 25 ... Copper-clad laminate or core substrate, 26 ... Laminated plate a, 27 ... Laminated plate b, 28 ... Cutting part, 29 ... First Interlayer connection , 30... First layer conductor layer, 31... Plating layer generated during interlayer connection, 32... Second interlayer connection hole, 33... Second layer conductor layer, 34. Layers 36 ... Laminated plate c 37 ... Fourth layer conductor layer 38 ... Metal foil (of core substrate) 39 ... Active surface of SAW piezoelectric element 40 ... Multilayer substrate

Claims (7)

A first layer wiring pattern formed by circuit processing of the metal foil A, an insulating resin layer disposed on the first layer wiring pattern, and at least one layer having a wiring pattern disposed on the insulating resin layer A multilayer wiring board having a wiring layer on a higher layer side,
The high-layer wiring pattern is formed by circuit processing a conductor layer formed by plating a metal foil on the insulating resin layer,
The wiring pattern on the highest layer side is thicker than the first layer wiring pattern, or the conductor layer remaining rate of the wiring pattern on the highest layer side is larger than the first layer wiring pattern, or the insulation on the first layer wiring pattern A multilayer wiring board formed such that the insulating resin layer on the highest layer side is thinner than the resin layer. In claim 1,
A multilayer wiring board formed so that the wiring pattern is thicker, the conductor layer remaining rate of the wiring pattern is larger, or the insulating resin layer is thinner as it goes to the higher layer side. In claim 1 or 2,
A multilayer wiring board in which a mechanical treatment is applied to the highest conductive layer so that the conductive layer extends in a planar direction. On the metal foil of the core substrate, the metal foil A is directly stacked, and an insulating resin layer and at least one wiring layer on the upper layer side having a wiring pattern arranged on the insulating resin layer are formed thereon. Further, by laminating an insulating resin layer and a conductor layer for forming a wiring layer on the higher layer side, a metal foil A directly in contact with the metal foil of the core substrate, a wiring layer on the metal foil A, Forming a multilayer substrate having an insulating resin layer and a conductor layer formed on the wiring layer;
Separating the core substrate and the multilayer substrate at the interface between the metal foil of the core substrate and the metal foil A;
By processing the metal foil A and the conductor layer of the multilayer substrate, the first layer wiring pattern formed by circuit processing of the metal foil A is formed on one side, and the conductor layer is formed on the other side by circuit processing. Forming a multilayer wiring board having a wiring pattern on the higher layer side,
A method for manufacturing a multilayer wiring board having
The wiring pattern on the highest layer side is thicker than the first layer wiring pattern, or the conductor layer remaining rate of the wiring pattern on the highest layer side is larger than the first layer wiring pattern, or the insulation on the first layer wiring pattern A method for manufacturing a multilayer wiring board, wherein the insulating resin layer on the highest layer side is thinner than the resin layer. On the metal foil of the core substrate, the metal foil A is directly stacked, and an insulating resin layer and at least one wiring layer on the upper layer side having a wiring pattern arranged on the insulating resin layer are formed thereon. A metal foil A that is in direct contact with the metal foil of the core substrate, a wiring layer on the metal foil A, and a metal layer A by overlapping an insulating resin layer and a conductor layer for forming a higher wiring layer on Forming a multilayer substrate having an insulating resin layer and a conductor layer formed on the wiring layer;
Circuit processing the conductor layer of the multilayer substrate;
Separating the core substrate and the multilayer substrate at the interface between the metal foil and the metal foil A of the core substrate;
By processing the metal foil A of the multilayer substrate, a first layer wiring pattern formed by processing the metal foil A on one side and a high layer formed by processing the conductor layer on the other side Forming a multilayer wiring board having a wiring pattern on the side;
A method for manufacturing a multilayer wiring board having
The wiring pattern on the highest layer side is thicker than the first layer wiring pattern, or the conductor layer remaining rate of the wiring pattern on the highest layer side is larger than that on the first layer wiring pattern, or the insulation on the first layer wiring pattern is A method for manufacturing a multilayer wiring board, wherein the insulating resin layer on the highest layer side is thinner than the resin layer. In claim 4 or 5,
A method for manufacturing a multilayer wiring board, wherein the wiring pattern is formed such that the thickness of the wiring pattern increases, the conductor layer remaining rate of the wiring pattern increases, or the thickness of the insulating resin layer decreases as the height increases. In any of claims 4 to 6,
A method of manufacturing a multilayer wiring board, wherein a mechanical treatment is applied to the highest conductor layer so that the conductor layer extends in a planar direction.

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