JP2011077381A - Iii族窒化物半導体基板、エピタキシャル基板及び半導体デバイス - Google Patents
Iii族窒化物半導体基板、エピタキシャル基板及び半導体デバイス Download PDFInfo
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- JP2011077381A JP2011077381A JP2009228598A JP2009228598A JP2011077381A JP 2011077381 A JP2011077381 A JP 2011077381A JP 2009228598 A JP2009228598 A JP 2009228598A JP 2009228598 A JP2009228598 A JP 2009228598A JP 2011077381 A JP2011077381 A JP 2011077381A
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- semiconductor substrate
- group iii
- nitride semiconductor
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
- C30B23/02—Epitaxial-layer growth
- C30B23/025—Epitaxial-layer growth characterised by the substrate
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Abstract
【解決手段】半導体デバイス100では、S換算で30×1010個/cm2〜2000×1010個/cm2の硫化物、及び、O換算で2at%〜20at%の酸化物が表面層12に存在することにより、エピタキシャル層22とIII族窒化物半導体基板10との界面においてCがパイルアップすることを抑制できる。このようにCのパイルアップを抑制することで、エピタキシャル層22とIII族窒化物半導体基板10との界面における高抵抗層の形成が抑制される。これにより、エピタキシャル層22とIII族窒化物半導体基板10との界面の電気抵抗を低減することができると共に、エピタキシャル層22の結晶品質を向上させることができる。したがって、半導体デバイス100の発光強度及び歩留を向上させることができる。
【選択図】図9
Description
図1は、第1実施形態に係るIII族窒化物半導体基板10を示す概略断面図である。III族窒化物半導体基板10(以下、「窒化物基板10」という)は、図1に示すように、互いに対向する表面10a及び裏面10bを有しており、表面10aには、表面層12が形成されている。
0.05≦PV/Q≦3.0 …(1)
PV/Qが0.05よりも小さい場合には、表面粗さが増加する傾向がある。PV/Qが3.0よりも大きい場合には、表面改質の効果が小さくなる傾向がある。
−50x+1400≦y≦−50x+1900 …(2)
yが式(2)の上限値を超えると、ポリシングパッドや研磨設備への腐食作用が強くなり、安定した状態で研磨することが困難となる傾向があると共に、基板表面の酸化が過度に進行する傾向がある。yが式(2)の下限値未満であると、基板表面の酸化作用が弱くなり易く、研磨レートが低下する傾向がある。
図4は、第1実施形態に係るエピタキシャル基板20を示す概略断面図である。エピタキシャル基板20は、図4に示すように、ベース基板としての上記窒化物基板10と、窒化物基板10の表面10a上に積層されたエピタキシャル層22とを有している。
図9は、第1実施形態に係る半導体デバイス100を示す概略断面図である。半導体デバイス100は、図9に示すように、エピタキシャル基板20と、エピタキシャル層22の表面23全体を覆って形成された電極90Aと、窒化物基板10の裏面10b全体を覆って形成された電極90Bとを有する。電極90A,90Bは、例えば金属蒸着により形成される。電極90A,90Bの形成位置は、必要に応じて適宜変更可能であり、電極90Bが窒化物基板10に電気的に接続されており、電極90Aがエピタキシャル層22に電気的に接続されていればよい。
まず、n型GaN結晶(ドーパント:O)をHVPE法によりc軸方向に成長させた。次に、GaN結晶をc軸に垂直にスライスし、表面が(0001)面である直径50mm×厚さ0.5mmのGaN基板を得た。
GaN基板の裏面((000−1)面)をセラミックス製の結晶ホルダにワックスで貼り付けた。ラップ装置に直径380mmの定盤を設置し、ダイヤモンドの砥粒が分散されたスラリーをスラリー供給口から定盤に供給しながら、定盤をその回転軸を中心にして回転させた。次に、結晶ホルダ上に重りを載せることによりGaN基板を定盤に押し付けながら、GaN基板を結晶ホルダの回転軸を中心にして回転させることにより、n型GaN結晶の表面のラッピングを行った。
図3と同様の構成を有するポリシング装置を用いて、GaN基板の表面のCMPを行った。CMPは以下の条件で行った。ポリシングパッドとしては、ポリウレタンのスウェードパッド(ニッタ・ハース株式会社製、Supreme RN-R)を用いた。定盤としては、直径380mmの円形のステンレス鋼定盤を用いた。GaN基板とポリシングパッドとの接触係数Cは、1.0×10−6m〜2.0×10−6mとした。ポリシング圧力は10kPa〜80kPaとし、GaN基板及びポリシングパッドの回転数はいずれも30回/min〜120回/minとした。スラリー(CMP溶液)には、砥粒として粒径200nmのシリカ粒子を水に20質量%分散させた。スラリーにはpH調整剤として、クエン酸、H2SO4を添加し、酸化剤としてジクロロイソシアヌル酸ナトリウムを添加して、スラリーのpH及び酸化還元電位を下記式(3)の範囲に調整した(x:pH、y:酸化還元電位(mV))。
−50x+1400≦y≦−50x+1900 …(3)
GaN基板をMOCVD装置内に配置して、MOCVD法により、厚さ1μmのn型GaN層(ドーパント:Si)、厚さ150nmのn型Al0.1Ga0.9N層(ドーパント:Si)、活性層、厚さ20nmのp型Al0.2Ga0.8N層(ドーパント:Mg)、及び、厚さ150nmのp型GaN層(ドーパント:Mg)をGaN基板の表面側に順次形成して、GaN基板上にエピタキシャル層を形成した。ここで、活性層は、4層の障壁層と3層の井戸層とを有しており、障壁層及び井戸層が交互に積層された多重量子井戸構造とした。障壁層は厚さ10nmのGaN層とし、井戸層は厚さ3nmのGa0.85In0.15N層とした。
Claims (14)
- 半導体デバイスに用いられるIII族窒化物半導体基板であって、
前記III族窒化物半導体基板の表面に表面層を有し、
前記表面層が、S換算で30×1010個/cm2〜2000×1010個/cm2の硫化物、及び、O換算で2at%〜20at%の酸化物を含む、III族窒化物半導体基板。 - 前記表面層がS換算で40×1010個/cm2〜1500×1010個/cm2の前記硫化物を含む、請求項1に記載のIII族窒化物半導体基板。
- 前記表面層がO換算で3at%〜16at%の前記酸化物を含む、請求項1又は2に記載のIII族窒化物半導体基板。
- 前記表面層がCl換算で120×1010個/cm2〜15000×1010個/cm2の塩化物を含む、請求項1〜3のいずれか一項に記載のIII族窒化物半導体基板。
- 前記表面層がSi換算で100×1010個/cm2〜12000×1010個/cm2のシリコン化合物を含む、請求項1〜4のいずれか一項に記載のIII族窒化物半導体基板。
- 前記表面層における炭素化合物の含有量がC換算で22at%以下である、請求項1〜5のいずれか一項に記載のIII族窒化物半導体基板。
- 前記表面層における銅化合物の含有量がCu換算で150×1010個/cm2以下である、請求項1〜6のいずれか一項に記載のIII族窒化物半導体基板。
- 前記表面層の表面粗さがRMS基準で5nm以下である、請求項1〜7のいずれか一項に記載のIII族窒化物半導体基板。
- 前記表面層の転位密度が1×106個/cm2以下である、請求項1〜8のいずれか一項に記載のIII族窒化物半導体基板。
- c軸に対する前記表面の法線軸の傾斜角度が10°〜81°である、請求項1〜9のいずれか一項に記載のIII族窒化物半導体基板。
- 前記表面の面方位が、{20−21}面、{10−11}面、{20−2−1}面、{10−1−1}面、{11−22}面、{22−43}面、{11−21}面、{11−2−2}面、{22−4−3}面、及び{11−2−1}面のいずれかである、請求項1〜10のいずれか一項に記載のIII族窒化物半導体基板。
- 請求項1〜11のいずれか一項に記載のIII族窒化物半導体基板と、前記III族窒化物半導体基板の前記表面層上に形成されたエピタキシャル層とを有し、前記エピタキシャル層がIII族窒化物半導体を含む、エピタキシャル基板。
- 前記エピタキシャル層が量子井戸構造を有する活性層を有し、
前記活性層が波長430nm〜550nmの光を発生するように設けられている、請求項12に記載のエピタキシャル基板。 - 請求項12又は13に記載のエピタキシャル基板を備える、半導体デバイス。
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US9437690B2 (en) | 2012-04-02 | 2016-09-06 | Sumitomo Electric Industries, Ltd. | Silicon carbide substrate, semiconductor device, and methods for manufacturing them |
JP2020169108A (ja) * | 2019-04-05 | 2020-10-15 | 国立大学法人京都工芸繊維大学 | 薄膜、薄膜付き基板および半導体装置 |
JP7290217B2 (ja) | 2019-04-05 | 2023-06-13 | 国立大学法人京都工芸繊維大学 | 薄膜、薄膜付き基板および半導体装置 |
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CN102471931A (zh) | 2012-05-23 |
US20150137319A1 (en) | 2015-05-21 |
US20120104558A1 (en) | 2012-05-03 |
EP2484818A1 (en) | 2012-08-08 |
CN102471931B (zh) | 2015-07-29 |
JP5365454B2 (ja) | 2013-12-11 |
US9299890B2 (en) | 2016-03-29 |
WO2011040108A1 (ja) | 2011-04-07 |
EP2484818B1 (en) | 2020-04-29 |
US8952494B2 (en) | 2015-02-10 |
EP2484818A4 (en) | 2015-02-11 |
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