JP2011029523A - 電子部品収納用パッケージおよび電子装置 - Google Patents
電子部品収納用パッケージおよび電子装置 Download PDFInfo
- Publication number
- JP2011029523A JP2011029523A JP2009176064A JP2009176064A JP2011029523A JP 2011029523 A JP2011029523 A JP 2011029523A JP 2009176064 A JP2009176064 A JP 2009176064A JP 2009176064 A JP2009176064 A JP 2009176064A JP 2011029523 A JP2011029523 A JP 2011029523A
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- Japan
- Prior art keywords
- electronic component
- component storage
- hole
- storage package
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
【解決手段】 凹部2を有する絶縁基体1と、凹部2の底面に配置された複数の配線導体3と、凹部2の周囲の側壁部のうち、少なくとも対向する一対の側壁部の上面にそれぞれ形成された複数の穴4とを備えている電子部品収納用パッケージである。電子部品収納用パッケージの絶縁基体1の凹部2の周囲の側壁部の上面に蓋体を樹脂からなる接合剤を介して接合する際に、電子部品収納用パッケージと接合剤との接合面積を広くすることができ、電子部品収納用パッケージと蓋体との接合強度を向上させることができる。
【選択図】 図1
Description
2:凹部
3:配線導体
4:穴
5:電子部品
6:接続部材
7:接合剤
8:蓋体
11:母基板
11a:電子部品収納用パッケージ領域
11b:ダミー領域
11c:ダミー穴
12:分割予定線
12a:分割溝
Claims (4)
- 凹部を有する絶縁基体と、前記凹部の底面に配置された複数の配線導体と、前記凹部の周囲の側壁部のうち、少なくとも対向する一対の側壁部の上面にそれぞれ形成された複数の穴とを備えていることを特徴とする電子部品収納用パッケージ。
- 前記穴は、開口よりも底面の方が大きいことを特徴とする請求項1に記載の電子部品収納用パッケージ。
- 前記穴は、前記開口から前記底面に向かって徐々に大きくなっていることを特徴とする請求項2に記載の電子部品収納用パッケージ。
- 請求項1乃至請求項3のいずれかに記載の電子部品収納用パッケージの前記凹部の前記底面に電子部品が搭載され、前記凹部を覆うように配置された蓋体が前記側壁部の上面および前記穴に付与された樹脂からなる接合剤を介して接合されていることを特徴とする電子装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009176064A JP5312250B2 (ja) | 2009-07-29 | 2009-07-29 | 電子部品収納用パッケージおよび電子装置 |
Applications Claiming Priority (1)
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JP2009176064A JP5312250B2 (ja) | 2009-07-29 | 2009-07-29 | 電子部品収納用パッケージおよび電子装置 |
Publications (2)
Publication Number | Publication Date |
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JP2011029523A true JP2011029523A (ja) | 2011-02-10 |
JP5312250B2 JP5312250B2 (ja) | 2013-10-09 |
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JP2009176064A Active JP5312250B2 (ja) | 2009-07-29 | 2009-07-29 | 電子部品収納用パッケージおよび電子装置 |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018088443A (ja) * | 2016-11-28 | 2018-06-07 | 京セラ株式会社 | 電子素子実装用基板および電子装置 |
CN110444512A (zh) * | 2018-05-02 | 2019-11-12 | 海成帝爱斯株式会社 | 传感器封装及包括所述传感器封装的传感器封装模块 |
WO2024053466A1 (ja) * | 2022-09-09 | 2024-03-14 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置および電子機器 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61296742A (ja) * | 1985-06-26 | 1986-12-27 | Oki Electric Ind Co Ltd | 樹脂シ−ルパツケ−ジ |
JP2004146392A (ja) * | 2002-08-30 | 2004-05-20 | Kyocera Corp | 半導体素子収納用パッケージおよび半導体装置 |
WO2007108419A1 (ja) * | 2006-03-22 | 2007-09-27 | Murata Manufacturing Co., Ltd. | 赤外線センサおよび赤外線センサの製造方法 |
JP2007335423A (ja) * | 2006-06-12 | 2007-12-27 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2009105224A (ja) * | 2007-10-23 | 2009-05-14 | Yamaha Corp | 半導体装置 |
-
2009
- 2009-07-29 JP JP2009176064A patent/JP5312250B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61296742A (ja) * | 1985-06-26 | 1986-12-27 | Oki Electric Ind Co Ltd | 樹脂シ−ルパツケ−ジ |
JP2004146392A (ja) * | 2002-08-30 | 2004-05-20 | Kyocera Corp | 半導体素子収納用パッケージおよび半導体装置 |
WO2007108419A1 (ja) * | 2006-03-22 | 2007-09-27 | Murata Manufacturing Co., Ltd. | 赤外線センサおよび赤外線センサの製造方法 |
JP2007335423A (ja) * | 2006-06-12 | 2007-12-27 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2009105224A (ja) * | 2007-10-23 | 2009-05-14 | Yamaha Corp | 半導体装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018088443A (ja) * | 2016-11-28 | 2018-06-07 | 京セラ株式会社 | 電子素子実装用基板および電子装置 |
CN110444512A (zh) * | 2018-05-02 | 2019-11-12 | 海成帝爱斯株式会社 | 传感器封装及包括所述传感器封装的传感器封装模块 |
CN110444512B (zh) * | 2018-05-02 | 2023-05-02 | 海成帝爱斯株式会社 | 传感器封装及包括所述传感器封装的传感器封装模块 |
WO2024053466A1 (ja) * | 2022-09-09 | 2024-03-14 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置および電子機器 |
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