JP2011003825A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress degradation of element characteristics which is caused by a defect present in a semiconductor substrate, relating to a semiconductor device.SOLUTION: A silicon carbide semiconductor device includes a semiconductor substrate 101, an epitaxial layer 102 formed on the surface of the semiconductor substrate 101, a gate insulating film 111 formed on the epitaxial layer 102, and a gate electrode 113 which is insulated from the epitaxial layer 102 by the gate insulating film 111. A defect propagation suppressing layer 116 whose defect density is lower than well region is provided between a well region 105 and a channel layer 115. By converting the substrate surface transition from the semiconductor substrate 101 to a blade-like transition by using the defect propagation suppressing layer 116, the defect density in the channel layer 115 directly under the gate insulating film 111 comes to be 50% or less of the defect density of the well region 105.

Description

  The present invention relates to a semiconductor device using silicon carbide and a method for manufacturing the same.

  Silicon carbide (silicon carbide: SiC) is a semiconductor that is expected to be applied to the next generation of low-loss power devices because it has a larger band gap and higher dielectric breakdown field strength than silicon (Si). Material. Silicon carbide has many polytypes such as cubic 3C—SiC and hexagonal 6H—SiC and 4H—SiC. Among these, 4H-SiC is a polytype generally used for producing a practical silicon carbide semiconductor element.

When a silicon carbide semiconductor element such as a MOSFET is manufactured, a 4H—SiC substrate having a surface substantially coincident with the (0001) Si surface perpendicular to the c-axis crystal axis is usually used. On the 4H—SiC substrate (hereinafter simply referred to as “SiC substrate”), an epitaxial growth layer serving as an active region of the silicon carbide semiconductor element is formed. In a selected region of the epitaxial growth layer, an impurity doped layer whose conductivity type and carrier concentration are controlled according to the type of semiconductor element to be manufactured is formed. For example, in the MOSFET, the impurity doped layer functions as a p-type well region or an n ⁺ source region.

  FIG. 7 illustrates a conventional MOSFET having a SiC channel structure. MOSFET 300 having a conventional structure has n-type drift layer 302 formed by epitaxial growth while supplying a dopant showing n-type conductivity on silicon carbide substrate 301. A p-type well region 305 is formed by ion-implanting an impurity serving as a p-type dopant, for example, aluminum (Al) into a part of the drift layer. Further, an impurity (for example, nitrogen) and a p-type impurity (for example, Al) serving as an n-type dopant are ion-implanted into a part of the well region, thereby forming a source region 308 and a contact region 309, respectively. Further, an n-type channel layer 307 is formed on at least the well region 305 by ion implantation of n-type impurities or epitaxial growth while supplying an n-type dopant. A gate insulating film 311 is formed on the channel layer 307 by, for example, thermal oxidation, and a gate electrode 313 is formed on the gate insulating film 311. Further, source electrode 312 is formed so as to be in contact with source region 308 and contact region 309, and drain electrode 314 is provided on the back surface of silicon carbide substrate 301.

  It is known that a SiC substrate has crystal defects due to the crystal growth mechanism and the like. As a typical crystal defect that greatly affects the characteristics of the SiC power device, there is a micropipe that is a defect penetrating the substrate. In this manner, in addition to the defects existing in the SiC substrate in advance, defects are generated in the ion implantation region of the SiC epitaxial growth layer in the ion implantation process in the MOSFET manufacturing process. The defects generated in the ion implantation region are recovered to some extent by performing the activation annealing process at a high temperature of 1600 ° C. or higher, but it is difficult to completely recover the SiC crystal. Defects remain. Hereinafter, problems due to defects generated by ion implantation will be described.

  FIG. 3 is a view obtained by observing a cross section in which the implantation layer 11 is formed in the epitaxial layer 10 by ion implantation using a transmission electron microscope (TEM). In FIG. 3, the region where defects are generated and the crystal is disturbed has a black mottled pattern. By implanting ions into the epitaxial layer 10 in this manner, a defect region (black mottled region) 12 is generated. Such a defect region is formed by cutting the bond between silicon and carbon in the SiC crystal when the implanted ions are incident on the epitaxial layer 10 or by replacing the implanted species with silicon or carbon sites. It is generated when silicon or carbon is ejected.

  When the channel layer is formed by epitaxial growth on the ion-implanted layer having defects thus formed by the conventional growth method, the defects in the ion-implanted layer are inherited by the channel layer and are also formed in the channel layer. Defects occur.

  As a result of studies by the present inventors, it has been found that such a channel layer defect has a large influence on the characteristics of the semiconductor element. In particular, it has been found that carriers flowing in the channel layer are scattered in the vicinity of the defect, thereby reducing the carrier mobility and reducing the reliability of the gate insulating film formed on the surface of the channel layer. It was also found that dislocations existing in parallel to the basal plane ((0001) plane) in the SiC crystal, called basal plane dislocations, deteriorate the reliability of the gate insulating film. For this reason, when a semiconductor element is formed using a channel layer having such a defect, there is a problem that a silicon carbide semiconductor element having the electrical characteristics expected from the excellent physical properties of SiC cannot be obtained.

  On the other hand, in order to avoid deterioration of device characteristics due to defects caused by ion implantation, Patent Document 1 and Patent Document 2 describe that a part of the well region of the MOSFET is formed by epitaxial growth instead of ion implantation. Disclosure.

JP 2008-210848 A JP 2004-31471 A

  By forming the well region of the MOSFET by epitaxial growth using the methods of Patent Document 1 and Patent Document 2, it is possible to avoid the occurrence of defects that occur in the well region due to ion implantation. However, it is very difficult to form a local well region by epitaxial growth, and this method has a problem that a MOSFET manufacturing process and its structure are complicated. For this reason, Patent Document 1 and Patent Document 2 cannot be applied to manufacture a MOSFET having a general structure that can be mass-produced.

  The present invention has been made in view of such conventional problems, and an object of the present invention is to suppress deterioration in element characteristics due to defects in a silicon carbide semiconductor element using a SiC substrate.

  A silicon carbide semiconductor element of the present invention includes a first conductivity type first silicon carbide layer formed on a main surface of a semiconductor substrate, and a second conductivity type impurity formed in the first silicon carbide layer. A well region including a source region including a first conductivity type impurity formed in the well region, a contact region including a second conductivity type impurity formed in the well region, and the well region A gate insulating film provided at a position facing the surface, a channel layer made of a third silicon carbide layer formed between the well region and the gate insulating film, and formed on the gate insulating film A gate electrode; a source electrode formed at a position in contact with the source region; a drain electrode formed on a surface facing the main surface of the semiconductor substrate; and the well region and the channel layer between Compared to well region Defect density Te is provided with lower and second silicon carbide layer.

  It is preferable that the defect density of the channel layer immediately below the gate insulating film is 50% or less of the defect density of the well region.

  The basal plane dislocation density of the channel layer immediately below the gate insulating film is preferably 50% or less of the basal plane dislocation density of the well region.

  The channel layer preferably includes a first conductivity type impurity.

  The first conductivity type impurity concentration contained in the second silicon carbide layer is preferably lower than the first conductivity type impurity concentration contained in the first silicon carbide layer.

  The semiconductor substrate is preferably a silicon carbide substrate whose main surface is a surface inclined by a predetermined angle from a (0001) Si surface.

The method for producing a silicon carbide semiconductor element of the present invention comprises:
(A) forming a first conductivity type first silicon carbide layer by first epitaxial growth on a main surface of a semiconductor substrate having a predetermined off angle;
(B) forming a well region containing a second conductivity type impurity in the first silicon carbide layer by ion implantation;
(C) forming a second silicon carbide layer by second epitaxial growth on the well region and the first silicon carbide layer;
(D) forming a channel layer made of a third silicon carbide layer containing a first conductivity type impurity on the second silicon carbide layer,
In the step (C), at the start of the second epitaxial growth on the well region, a carbon source is supplied to the surface of the well region before the silicon source to perform the second epitaxial growth (C1). including.

  The ratio of carbon content to silicon content (C / Si) in the step (C1) is preferably larger than the ratio of carbon content to silicon content when forming the channel layer.

  Moreover, it is preferable to form a layer having a lower defect density than the well region between the well region and the channel layer by performing the step (C1).

  Preferably, aluminum is used as the second conductivity type impurity, and the well region is formed by ion implantation of the aluminum.

Moreover, the method for manufacturing the silicon carbide semiconductor element of the present invention further includes:
(E) forming a source region containing a first conductivity type impurity in the well region;
(F) forming a contact region containing a second conductivity type impurity in the well region;
(G) forming a gate insulating film on the surface of the channel layer;
(H) forming a gate electrode on the gate insulating film;
(I) forming a source electrode at a position in contact with the source region;
(J) forming a drain electrode on the back surface facing the main surface of the semiconductor substrate;
It is preferable to contain.

  According to the silicon carbide semiconductor element of the present invention, since the density of defects in the channel layer on the well region formed by ion implantation is reduced, there is no decrease in carrier mobility caused by the defect in the channel layer. The deterioration of the reliability of the oxide film formed thereon is also suppressed. Further, according to the manufacturing method of the present invention, since only one process is added compared to the conventional process, the semiconductor element can be manufactured without complicating the process.

1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention. (A)-(f) is process sectional drawing for demonstrating the manufacturing method of the semiconductor element which concerns on 1st Embodiment by this invention. The figure which observed the section which formed the injection layer in the epitaxial layer by ion implantation with the transmission electron microscope (TEM) (A) (b) is sectional drawing for demonstrating the mode of propagation to the epitaxial layer of the substrate surface dislocation in this invention Sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention. (A)-(f) is process sectional drawing for demonstrating the manufacturing method of the semiconductor element which concerns on 2nd Embodiment by this invention. Cross-sectional schematic diagram of a conventional semiconductor device The figure which observed the section which formed the channel layer by epitaxial growth on the injection layer by the method of the present invention with the transmission electron microscope (TEM) (A) is a schematic diagram for explaining the mechanism of epitaxial growth, and (b) and (c) are for explaining the state of propagation of substrate plane dislocations to the epitaxial layer in the embodiment of the present invention and the conventional one, respectively. Cross section

  In the semiconductor device of the present invention, an implantation in a well region is performed between a well region formed by implantation (hereinafter also referred to as an implantation well region) and a channel layer formed by epitaxial growth (hereinafter also referred to as a channel epi layer). A defect propagation suppressing layer having a function of suppressing the propagation of defects to the upper channel layer is provided. The defect propagation suppressing layer functions as a suppressing layer that suppresses the injection defects formed in the well region, so that the injection defects are not propagated to the upper channel layer.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. The semiconductor element of this embodiment is characterized in that a defect propagation suppression layer is formed between the well region and the channel epilayer. A MOSFET having such a defect propagation suppression layer will be described.

  Semiconductor device 100 shown in FIG. 1 includes low-resistance n-type silicon carbide substrate 101, silicon carbide layer 104 formed on the main surface of silicon carbide substrate 101, source electrode 112 formed on silicon carbide layer 104, and Gate electrode 113, gate insulating film 111 provided between gate electrode 113 and silicon carbide layer 104, and drain electrode 114 formed on the back surface of silicon carbide substrate 101 are included.

The silicon carbide substrate 101 is a silicon carbide substrate having a (0001) Si surface as a main surface, and is made of, for example, 4H—SiC, and is inclined by several degrees (for example, an off angle of 4 to 8 degrees) from the (0001) Si surface. An off-cut substrate having a surface with increased step density. The defect in silicon carbide substrate 101 is, for example, 10 ⁴ cm ⁻² or more (in this embodiment, about 3 × 10 ⁴ cm ⁻² ).

  Silicon carbide layer 104 has a plurality of p-type well regions 105 and drift regions 107 formed in epitaxial layer 102 (see FIG. 2). Drift region 107 is a silicon carbide layer containing n-type impurities at a lower concentration than silicon carbide substrate 101. Inside the well region 105, an n-type source region 108 containing an n-type impurity at a high concentration and a contact region 109 containing a p-type impurity at a high concentration are formed. A part of the source region 108 is in ohmic contact with the source electrode 112.

  Silicon carbide layer 104 has channel layer 115 containing an n-type impurity between well region 105 and gate insulating film 111. Between the well region 105 and the channel layer 115, there is a defect propagation suppressing layer 116 that suppresses the propagation of the crystal defect region formed by ion implantation in the well region to the channel layer 115. Due to the effect of the layer, the defect density on the upper side of the defect propagation suppression layer 116, that is, on the channel layer 115 is about an order of magnitude smaller than the defect density on the lower surface of the defect propagation suppression layer 116. As a result, since the crystallinity of the channel layer 115 is improved as compared with the conventional case, the scattering of electrons due to the defects present in the crystal is suppressed, the channel current density flowing during the ON operation of the MOSFET is increased, and the on-resistance of the MOSFET is greatly increased. It becomes possible to reduce it.

<The manufacturing method of the semiconductor element of this embodiment>
Hereinafter, an example of a method for manufacturing the semiconductor element 100 of the present embodiment will be described with reference to the drawings.

First, as shown in FIG. 2A, an epitaxial layer (first silicon carbide layer) 102 of silicon carbide is formed on the main surface of silicon carbide substrate 101 by epitaxial growth. As the silicon carbide substrate 101, for example, a 4H—SiC substrate having a diameter of 50 mm and having an off angle of 8 degrees in the [11-20] (112 bar 0) direction from the (0001) Si surface is used. The substrate 101 is n-type, and the impurity concentration in the substrate 101 is, for example, 8 × 10 ¹⁸ cm ⁻³ . The epitaxial layer 102 is formed by, for example, thermal CVD using silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases, hydrogen (H ₂ ) as a carrier gas, and nitrogen (N ₂ ) gas as a dopant gas. Can be formed by Here, epitaxial layer 102 made of n-type silicon carbide having an impurity concentration lower than that of silicon carbide substrate 101 is formed. Although the impurity concentration and thickness of the epitaxial layer 102 vary depending on the specifications required for the MOSFET, for example, when manufacturing a MOSFET with a breakdown voltage of 600 V, the impurity concentration of the epitaxial layer 102 is 1 × 10 ¹⁵ cm ⁻³ or more and 5 ×. It is desirable that the thickness is 10 ¹⁶ cm ⁻³ or less and the thickness is 5 μm or more. Thus, epitaxial substrate 103 including silicon carbide substrate 101 and epitaxial layer 102 formed on silicon carbide substrate 101 is obtained.

Subsequently, as shown in FIG. 2B, impurity ions are implanted into a selected region of the epitaxial layer 102 of the epitaxial substrate 103 to form a well region 105. Specifically, a mask 106 made of a silicon oxide film (SiO ₂ ) is formed on a predetermined position of the epitaxial layer 102, and p-type impurity (eg, Al) ions are implanted into a region where the mask 106 is not formed. To do. The thickness of the mask 106 is determined by its material and implantation conditions, but is preferably set sufficiently larger than the implantation range.

Further, as shown in FIG. 2C, a defect propagation suppressing layer (second silicon carbide layer) 116 and an n-type channel layer (third silicon carbide layer) 115 are deposited on the surface of the epitaxial layer 102, Silicon carbide layer 104 is formed. When forming the defect propagation suppression layer 116, the propane gas as the carbon source was supplied before the silane gas as the silicon source without supplying the dopant gas, and the film thickness was set to 30 nm. Further, when forming the channel layer 115, nitrogen is supplied as a dopant gas to form a doped layer having an n-type concentration of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 10 nm. An undoped layer which is not supplied was formed with a film thickness of 100 nm. When the channel layer 115 is formed, the ratio C / Si of the carbon content to the silicon content in the source gas to be supplied is smaller than the C / Si ratio when the defect propagation suppression layer 116 is formed. Set to be.

Thereafter, as shown in FIG. 2D, a silicon oxide film (SiO ₂ ) as a mask is formed (not shown) as a mask at a predetermined position on the channel layer 115 using, for example, a plasma CVD apparatus. N-type impurity (for example, nitrogen) ions are implanted into the opening (a part of the well region 105).

  Further, in the same manner as described above, p-type impurity (for example, aluminum) ions are implanted into a part of the well region 105 using a predetermined mask. A carbon cap layer is formed on the surface of the epitaxial substrate 103 subjected to these ion implantation processes, and activation annealing (about 1100 ° C.) is performed to form a source region 108 and a contact region 109 in the well region.

Further, as shown in FIG. 2E, a gate insulating film 111 is formed. The gate insulating film 111 is a SiO ₂ film having a thickness of about 50 nm, and can be formed by thermally oxidizing the surface of the epitaxial layer 102 at a temperature of about 1100 ° C.

  Finally, as shown in FIG. 2F, a gate electrode 113, a source electrode 112, and a drain electrode 114 are formed. The source electrode 112 and the drain electrode 114 are each formed by depositing Ni on the source region 108 and the back surface of the silicon carbide substrate 101 using an electron beam (EB) deposition apparatus, and subsequently heating at 1000 ° C. using a heating furnace. Formed by. Source electrode 112 forms an ohmic junction with source region 108, and drain electrode 114 forms an ohmic junction with silicon carbide substrate 101. The gate electrode 113 can be formed by depositing a phosphorus-doped poly-Si film on the gate insulating film 111 using an LPCVD apparatus. Thereby, the semiconductor element 100 is obtained.

In addition, the manufacturing method of the semiconductor element of this embodiment is not limited to the said method. For example, a substrate made of a polytype other than 4H—SiC may be used as the silicon carbide substrate 101. In the above method, the gate insulating film 111 is a thermally oxidized (SiO ₂ ) film formed by thermally oxidizing the silicon carbide layer 104, but the SiO deposited on the silicon carbide layer 104 by the CVD method. _Two films may be used.

<Measurement of channel layer defect density>
FIG. 8 is a view of a cross section in which the defect propagation suppression layer 23 is formed on the ion implantation layer 21 formed in the epitaxial layer 20 by the method described in the present embodiment, which is observed with a transmission electron microscope (TEM). In FIG. 8, as in FIG. 3, the defect region 22 has a black mottled pattern. On the other hand, the black mottled pattern is not observed in the channel layer 24 formed on the defect propagation suppressing layer 23, and it can be seen that the same crystalline epitaxial layer as the epitaxial layer 20 is formed. As described above, according to the method of the present embodiment, it has been clarified that the channel layer 24 with good crystallinity can be formed by epitaxial growth without being affected by the defect region 22 of the ion implantation layer 21.

  Next, since the defect density in the channel layer 115 of the epitaxial substrate 103 was measured, the method and result will be described.

The epitaxial substrate surface was subjected to KOH etching by immersing the epitaxial substrate 103 in potassium hydroxide (KOH) melted by heating to 500 ° C. for 5 minutes. Next, the etched surface was observed with a microscope to examine the defect density. The types of defects and dislocations were distinguished by the shape of the etch pit. The defect density on the surface of the epitaxial layer of the substrate was about 10 ³ cm ⁻² . Among these defects, the density of basal plane dislocations was about 10 ² cm ⁻² .

In order to compare with the above results, an epitaxial substrate was prepared as a comparative sample substrate by a conventional method, and the defect density was measured by the same method as described above. The comparative sample substrate had the same structure as that of the epitaxial substrate 103 of this embodiment except that the channel layer was formed by simultaneously supplying silicon and carbon instead of forming the defect propagation suppressing layer 116. When KOH etching was performed on the surface of the obtained comparative sample substrate and then the surface was observed, defects were observed at a higher density than the epi substrate 103 of the present embodiment. The defect density was about 10 ⁵ cm ⁻² , a defect density almost equivalent to that of the ion implantation layer in the well region, and higher than that of the silicon carbide substrate 101. Among these defects, the density of basal plane dislocations was about 10 ³ cm ⁻² .

<Study on the principle of reducing defect density>
Next, the principle that the present embodiment can reduce the defect density due to ion implantation in the well region will be described with reference to the drawings.

  FIG. 4 is a schematic diagram of a mechanism in which epitaxial growth proceeds from a (0001) Si plane to a step surface having an off angle in the [11-20] (112 bar 0) direction in the present embodiment. This step structure has a step surface perpendicular to the (0001) plane and a terrace surface parallel to this surface, and a region called a kink having a dangling bond exists on the step surface. According to the method of this embodiment, as shown in FIG. 4A, since silicon carbide is epitaxially grown on the step structure surface 50 of silicon carbide constituting the epitaxial layer, the silicon carbide is laterally moved from each step (FIG. 4A). In the X direction). In the epitaxial growth step for forming the defect propagation suppressing layer, carbon is first bonded to the dangling bonds present on the terrace surface near the step of the defect region by supplying carbon to the substrate surface before silicon. Subsequently, this carbon is bonded to the dangling bonds on the step surface above the terrace surface, and thereafter, epitaxial growth proceeds while propagating information on the step surface without being affected by the defect region on the terrace surface. For this reason, it becomes possible to form a channel layer in which the defect density is suppressed without propagating the defects present mainly on the terrace surface of the ion implantation layer.

  Next, the principle that basal plane dislocations can be reduced by this embodiment will be described.

  FIG. 4B is a partially enlarged view for explaining the growth of the defect propagation suppressing layer in FIG. As shown in FIG. 4B, in the epitaxial growth process for forming the defect propagation suppressing layer, by supplying carbon to the substrate surface before silicon, first, the slip surface of the defect region in the surface step is formed. Epitaxial growth proceeds while carbon bonds to dangling bonds and then bonds to dangling bonds at the end of the step surface above the slip surface. Thus, when an epitaxial layer is formed in a region where defects are filled with kinks at the end of the step surface using the sliding surface as a template, an epitaxial layer having a low defect density is grown thereafter.

  As described above, in this embodiment, the basal plane dislocations are reduced in the channel layer because the dislocation lines from the substrate surface are stepped by supplying carbon earlier than silicon at the start of growth. This is considered to be because the basal plane dislocation existing in the implantation defect region is converted into the threading edge dislocation by 90 ° conversion in the direction parallel to the c-axis of the crystal orientation by flow growth. This will be described with reference to FIG.

  FIG. 9A is a schematic diagram of the mechanism of epitaxial growth in the present embodiment. As shown in FIG. 9A, the epitaxial layer 34 is formed by epitaxially growing silicon carbide on the step structure surface of the ion implantation layer 32. Silicon carbide grows laterally (in the direction of the arrow in FIG. 9A) from each step 61 of the epitaxial growth layer 34. In the epitaxial growth step for forming the defect propagation suppressing layer 33, if carbon is supplied earlier than silicon, the carbon vacancies are reduced as a result by the principle described with reference to FIG. Into the silicon (anti-site). Thereby, the defect dislocation 30 from the substrate surface stops propagating in the lateral direction, and the antisite is propagated upward. In this way, the substrate surface defect dislocation changes to a threading edge dislocation extending upward (c-axis direction) perpendicular to the (0001) plane.

  In order to explain the state of dislocation change in the defect propagation suppressing layer, FIG. 9B shows a cross-sectional view of the epitaxial layer 34 epitaxially grown on the ion implantation layer 32 in this embodiment. As shown in FIG. 9B, the substrate plane dislocation 30 in the ion implantation layer 32 changes to the edge dislocation 31 in the defect propagation suppression layer 33. Once changed to the edge dislocation 31, the edge dislocation 31 is propagated and reaches the surface of the epitaxial layer 34.

  On the other hand, in the epitaxial layer formed by the conventional method, as shown in FIG. 9 (c), the defects in the ion implantation layer are epitaxially grown as they are because the unbonded hands of the step of the ion implantation layer 32 exist. Layer 34 takes over as a defect. Further, the basal plane dislocations in the ion implanted layer are inherited and propagated in the epitaxial layer 34 as they are. Even when the channel layer is epitaxially grown by the conventional method, some of the defects disappear during the growth of the channel layer, but the rate is considered to be extremely smaller than the rate of change when grown by the method of this embodiment. It is done.

<Characteristics of semiconductor elements>
Next, since the characteristics of the semiconductor element in this embodiment were examined, the results will be described.

  First, the MOSFET of the example was manufactured by the same method as that described with reference to FIG. As a comparative example, the conventional channel structure MOSFET 300 (MOSFET of the comparative example) shown in FIG. 7 was fabricated.

  The MOSFET 300 of the comparative example is manufactured by the method described above with reference to FIG. 7, and the channel layer 307 is formed by epitaxial growth while supplying an n-type dopant.

  Next, the current-voltage characteristics in the MOSFETs of the example and the comparative example were respectively measured and the measurement results were compared. As a result, it was found that the on-resistance was reduced by 30% in the MOSFET of the example compared to the MOSFET of the comparative example. It was.

The reason is considered as follows. In the MOSFET of the comparative example, the defect density on the surface of the silicon carbide channel layer is as high as the density in the well region (about 10 ⁵ cm ⁻² ), so that the channel resistance formed on the silicon carbide channel layer is greatly increased. . On the other hand, in the MOSFET of the embodiment, the defects that increase the channel resistance are greatly reduced by the defect propagation suppressing layer, and the defect density on the epitaxial layer surface is reduced to about 10 ³ cm ⁻² . Therefore, the on-resistance can be reduced as compared with the MOSFET of the comparative example.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. The semiconductor element of the present embodiment is characterized in that the channel layer formed on the well region also has a function of a defect propagation suppression layer. The MOSFET having the above will be described.

  Semiconductor device 200 shown in FIG. 5 includes low resistance n-type silicon carbide substrate 201, silicon carbide layer 204 formed on the main surface of silicon carbide substrate 201, source electrode 212 formed on silicon carbide layer 204, and It has a gate electrode 213, a gate insulating film 211 provided between the gate electrode 213 and the silicon carbide layer 204, and a drain electrode 214 formed on the back surface of the silicon carbide substrate 201.

The silicon carbide substrate 201 is a silicon carbide substrate having a (0001) Si surface as a main surface, and is made of, for example, 4H—SiC, and is inclined by several degrees (for example, an off angle of 4 to 8 degrees) from the (0001) Si surface. An off-cut substrate having a surface with increased step density. The defect in the silicon carbide substrate 201 is, for example, 10 ⁴ cm ⁻² or more (in this embodiment, about 3 × 10 ⁴ cm ⁻² ).

  Silicon carbide layer 204 has a plurality of p-type well regions 205 and drift regions 207 formed in epitaxial layer 202 (see FIG. 6). Drift region 207 is a silicon carbide layer containing n-type impurities at a lower concentration than silicon carbide substrate 201. Inside the well region 205, an n-type source region 208 containing an n-type impurity at a high concentration and a contact region 209 containing a p-type impurity at a high concentration are formed. A part of the source region 208 and the contact region 209 forms an ohmic contact with the source electrode 212.

Silicon carbide layer 204 has channel layer 215 containing an n-type impurity between well region 205 and gate insulating film 211. Here, since the channel layer is formed by epitaxial growth by supplying propane gas as a carbon source before silane gas as a silicon source, the channel layer acts as a defect propagation suppressing layer in which defects disappear in the channel layer. The density of defects in is about one order of magnitude less than the density of defects in the well region, and is about 3 × 10 ² cm ⁻² . As a result, the crystallinity of the channel layer is improved, and the on-resistance of the MOSFET can be reduced as compared with the conventional case.

<The manufacturing method of the semiconductor element of this embodiment>
Hereinafter, an example of a method for manufacturing the semiconductor element 200 of the present embodiment will be described with reference to the drawings.

First, as shown in FIG. 6A, a silicon carbide epitaxial layer (first silicon carbide layer) 202 is formed on the main surface of a silicon carbide substrate 201 by epitaxial growth. As the silicon carbide substrate 201, for example, a 4H—SiC substrate having a diameter of 50 mm and having an off angle of 8 degrees in the [11-20] (112 bar 0) direction from the (0001) Si surface is used. The substrate 201 is n-type, and the impurity concentration in the substrate 201 is, for example, 8 × 10 ¹⁸ cm ⁻³ . Epitaxial layer 202 forms n-type drift layer 10 μm on silicon carbide substrate 201 using nitrogen as an n-type dopant by the same method as in the first embodiment. Thus, epitaxial substrate 203 including silicon carbide substrate 201 and epitaxial layer 202 formed on silicon carbide substrate 201 is obtained.

  Subsequently, as shown in FIG. 6B, impurity ions are implanted into a selected region of the epitaxial layer 202 of the epitaxial substrate 203. Specifically, p-type impurity (for example, Al) ions are implanted into a region of the epitaxial layer 202 where the mask 206 is not formed, thereby forming the well region 205.

Further, as shown in FIG. 6C, an n-type channel layer 215 is formed on the surface of the epitaxial layer 202. The channel layer 215 was formed by epitaxial growth by supplying propane gas as a carbon source before silane gas as a silicon source. When forming the channel layer 215, nitrogen was used as the dopant gas, the n-type concentration was 2 × 10 ¹⁷ cm ⁻³ , and the film thickness was 150 nm. Thus, silicon carbide layer 204 having channel layer 215 is formed on epitaxial layer 202.

Thereafter, as shown in FIG. 2D, a silicon oxide film (SiO ₂ ) as a mask is formed (not shown) at a predetermined position on the channel layer 115 by using, for example, a plasma CVD apparatus. N-type impurity (for example, nitrogen) ions are implanted into the opening of the mask (a part of the well region 205). Further, p-type impurity (for example, aluminum) ions are implanted into a part of the well region 205 using a predetermined mask in the same manner as described above. A source region 208 and a contact region 209 are formed in the well region by forming a carbon cap layer on the surface of the silicon carbide substrate 201 that has been subjected to these ion implantation processes and performing activation annealing (about 1100 ° C.).

Further, as shown in FIG. 6E, a gate insulating film 211 is formed. The gate insulating film 211 is a SiO ₂ film having a thickness of 50 nm, and can be formed by thermal oxidation at a temperature of about 1100 ° C.

  Finally, as shown in FIG. 6F, a gate electrode 213, a source electrode 212, and a drain electrode 214 are formed. The source electrode 212 and the drain electrode 214 are each formed by depositing Ni on the source region 208 and the back surface of the silicon carbide substrate 201 using an electron beam (EB) deposition apparatus, and subsequently heating at 1000 ° C. using a heating furnace. Formed by. Source electrode 212 forms an ohmic junction with source region 208, and drain electrode 214 forms an ohmic junction with silicon carbide substrate 201. The gate electrode 213 can be formed by depositing a phosphorus-doped poly-Si film on the gate insulating film 211 using an LPCVD apparatus. Thereby, the semiconductor element 200 is obtained.

In addition, the manufacturing method of the semiconductor element of this embodiment is not limited to the said method. For example, a substrate made of a polytype other than 4H—SiC may be used as the silicon carbide substrate 201. In the above method, the gate insulating film 211 is a thermal oxidation (SiO ₂ ) film formed by thermally oxidizing the silicon carbide layer 204, but the SiO deposited on the silicon carbide layer 204 by the CVD method. _Two films may be used.

<Measurement of channel layer defect density>
Here, since the density of defects on the surface of the channel layer 215 of the epitaxial substrate 203 was measured, the method and result will be described.

The epitaxial substrate 203 was immersed in potassium hydroxide (KOH) heated to 500 ° C. for 5 minutes to perform KOH etching on the surface of the epitaxial layer. The etched surface was then observed with a microscope to examine the density of defects. As a result, the density of defects on the surface of the epitaxial layer of the sample substrate was about 10 ³ cm ⁻² , which was found to be reduced by about an order of magnitude or more compared to the comparative sample substrate of the first embodiment. This is considered to be due to the principle of suppressing the ion implantation defect in the well region described in the first embodiment.

<Measurement of channel layer defect density>
Next, since the characteristics of the semiconductor element in this embodiment were examined, the results will be described.

  First, the MOSFET of the example was manufactured by the same method as that described with reference to FIG. As a comparative example, the conventional channel structure MOSFET 300 (MOSFET of the comparative example) shown in FIG. 7 was fabricated.

  The MOSFET 300 of the comparative example is manufactured by the method described above with reference to FIG. 7, and the channel layer is formed by a conventional method.

  Next, the current-voltage characteristics in the MOSFETs of the example and the comparative example were measured and the measurement results were compared. As a result, the on-resistance of the MOSFET of the example was reduced by about 10% compared to the MOSFET of the comparative example. I found out that

The reason is considered as follows. In the MOSFET of the comparative example, since the defect density on the surface of the channel layer is as high as the density in the well region (about 10 ⁵ cm ⁻² ), the channel mobility formed on the channel layer is greatly reduced. On the other hand, in the MOSFET of the present embodiment, the defect propagation suppression layer is a channel layer, thereby reducing defects that reduce the carrier mobility of the channel layer, and the defect density on the surface of the channel layer is about 10 ^3. It is reduced by about an order of magnitude to cm ⁻² . Therefore, it is considered that the on-resistance can be reduced as compared with the MOSFET of the comparative example.

  According to the present invention, a low-loss semiconductor element with low on-resistance can be provided by reducing the defect density in a desired channel region of the semiconductor layer. The application of the present invention to a silicon carbide power element is particularly advantageous because it can realize the low loss expected from the excellent physical properties of silicon carbide.

DESCRIPTION OF SYMBOLS 10,20 Epitaxial layer 11,21 Ion implantation layer 12,22 Defect area | region 23 Defect propagation suppression layer 24 Channel layer 101,201,301 Semiconductor substrate (silicon carbide substrate)
102, 202 Epitaxial layer 103, 203 Epi substrate 105, 205, 305 Well region 107, 207, 302 Drift region 108, 208, 308 Source region 111, 211, 311 Gate insulating film 112, 212, 312 Source electrode 114, 214, 314 Drain electrode 113, 213, 313 Gate electrode 116 Defect propagation suppression layer

Claims (10)

A first silicon carbide layer of a first conductivity type formed on the main surface of the semiconductor substrate;
A well region containing a second conductivity type impurity formed in the first silicon carbide layer;
A source region including a first conductivity type impurity formed in the well region;
A contact region containing a second conductivity type impurity formed in the well region;
A gate insulating film provided at a position facing the surface of the well region;
A channel layer made of a third silicon carbide layer formed between the well region and the gate insulating film;
A gate electrode formed on the gate insulating film;
A source electrode formed at a position in contact with the source region;
A drain electrode formed on a surface facing the main surface of the semiconductor substrate;
A second silicon carbide layer having a defect density lower than that of the well region between the well region and the channel layer;
A silicon carbide semiconductor element comprising:   2. The silicon carbide semiconductor device according to claim 1, wherein a defect density of the channel layer immediately below the gate insulating film is 50% or less of a defect density of the well region.   3. The silicon carbide semiconductor device according to claim 1, wherein a basal plane dislocation density of the channel layer immediately below the gate insulating film is 50% or less of a basal plane dislocation density of the well region.   4. The silicon carbide semiconductor device according to claim 1, wherein the channel layer contains an impurity of a first conductivity type. 5.   5. The impurity concentration of the first conductivity type contained in the second silicon carbide layer is lower than the impurity concentration of the first conductivity type contained in the first silicon carbide layer. The silicon carbide semiconductor element according to any one of the above.   6. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon carbide substrate having a main surface that is inclined by a predetermined angle from a (0001) Si surface. (A) forming a first conductivity type first silicon carbide layer by first epitaxial growth on a main surface of a semiconductor substrate having a predetermined off angle;
(B) forming a well region containing a second conductivity type impurity in the first silicon carbide layer by ion implantation;
(C) forming a second silicon carbide layer by second epitaxial growth on the well region and the first silicon carbide layer;
(D) forming a channel layer made of a third silicon carbide layer containing a first conductivity type impurity on the second silicon carbide layer,
In the step (C), at the start of the second epitaxial growth on the well region, a carbon source is supplied to the surface of the well region before the silicon source to perform the second epitaxial growth (C1). The manufacturing method of the silicon carbide semiconductor element characterized by the above-mentioned.   The ratio of the carbon content to the silicon content (C / Si) in the step (C1) is larger than the ratio of the carbon content to the silicon content when forming the channel layer. A method for manufacturing a silicon carbide semiconductor element according to claim 7.   9. The method for manufacturing a silicon carbide semiconductor element according to claim 7, wherein aluminum is used as the second conductivity type impurity, and the well region is formed by ion implantation of the aluminum. (E) forming a source region containing a first conductivity type impurity in the well region;
(F) forming a contact region containing a second conductivity type impurity in the well region;
(G) forming a gate insulating film on the surface of the channel layer;
(H) forming a gate electrode on the gate insulating film;
(I) forming a source electrode at a position in contact with the source region;
(J) forming a drain electrode on the back surface facing the main surface of the semiconductor substrate;
The method for manufacturing a silicon carbide semiconductor element according to claim 7, further comprising: