CN114530370A - MOSFET device based on epitaxial channel and preparation method thereof - Google Patents
MOSFET device based on epitaxial channel and preparation method thereof Download PDFInfo
- Publication number
- CN114530370A CN114530370A CN202011322803.0A CN202011322803A CN114530370A CN 114530370 A CN114530370 A CN 114530370A CN 202011322803 A CN202011322803 A CN 202011322803A CN 114530370 A CN114530370 A CN 114530370A
- Authority
- CN
- China
- Prior art keywords
- layer
- injection
- type
- gate oxide
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000002347 injection Methods 0.000 claims abstract description 93
- 239000007924 injection Substances 0.000 claims abstract description 93
- 238000000034 method Methods 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 230000001590 oxidative effect Effects 0.000 claims abstract description 8
- 238000002513 implantation Methods 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000007943 implant Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 7
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 16
- 238000005468 ion implantation Methods 0.000 description 12
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 11
- 238000004140 cleaning Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 239000012300 argon atmosphere Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- -1 aluminum ions Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Abstract
The invention relates to an MOSFET device based on an epitaxial channel and a preparation method thereof, wherein the method comprises the following steps: selecting an N-type substrate layer; forming an N-type epitaxial layer on the N-type substrate layer; forming P well injection regions on the inner surfaces of two ends of the N type epitaxial layer; forming an N + injection region and a P + injection region on the inner surface of the P well injection region, wherein the two N + injection regions are positioned between the two P + injection regions; forming an epitaxial channel layer on part of the N-type epitaxial layer, part of the P-well injection region and part of the N + injection region; thermally oxidizing the epitaxial channel layer and the N-type epitaxial layer to form a first gate oxide layer and a second gate oxide layer positioned on the first gate oxide layer and the N-type epitaxial layer; forming a source electrode on the P + injection region and part of the N + injection region; forming a drain electrode on the lower surface of the N-type substrate layer; and forming a grid electrode on the second grid oxide layer. According to the invention, the epitaxial channel layer is formed, oxidation treatment is carried out on the epitaxial channel layer, and the gate oxide layer is formed by an oxidation method, so that the C cluster problem at the channel in the traditional structure can be effectively avoided, the defect density of the channel is reduced, the mobility of the channel is improved, and the reliability of the device is improved.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and relates to an MOSFET device based on an epitaxial channel and a preparation method thereof.
Background
Silicon carbide (SiC) is the most advantageous semiconductor material for manufacturing high-temperature, high-power electronic devices due to its excellent physicochemical and electrical properties, and has a power device quality factor much greater than that of Si materials. The development of SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) power devices began in the 90 s of the 20 th century, and the SiC MOSFET power devices have a series of advantages of high input impedance, fast switching speed, high operating frequency, high temperature and high pressure resistance, and have been widely applied to switching regulated power supplies, high-frequency heating, automotive electronics, power amplifiers, and the like.
One key technical problem that currently limits the application of SiC power MOSFETs is SiC/SiO2The defects of the channel are more, on one hand, the mobility of the channel is reduced, and therefore the forward conduction current in the period is reduced, on the other hand, the fixed charges caused by the defects can shift the threshold voltage, and the circuit application of the SiC power MOSFET is influenced. The physical layer cause of these defects is the oxidation of SiC to form SiO2The C element which remains at that time is piled up to form C clusters.
Therefore, how to eliminate these C clusters becomes a key to solving this problem.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an epitaxial channel-based MOSFET device and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the embodiment of the invention provides a preparation method of an MOSFET device based on an epitaxial channel, which comprises the following steps:
selecting an N-type substrate layer;
forming an N-type epitaxial layer on the N-type substrate layer;
forming two P-well injection regions on the inner surfaces of two ends of the N-type epitaxial layer;
forming an N + injection region and a P + injection region on the inner surface of the P well injection region, wherein the two N + injection regions are positioned between the two P + injection regions;
forming an epitaxial channel layer on part of the N-type epitaxial layer, part of the P-well injection region and part of the N + injection region;
thermally oxidizing the epitaxial channel layer and the N-type epitaxial layer to form a first gate oxide layer and a second gate oxide layer positioned on the first gate oxide layer and the N-type epitaxial layer;
forming a source electrode on the P + injection region and a part of the N + injection region;
forming a drain electrode on the lower surface of the N-type substrate layer;
and forming a grid electrode on the second grid oxide layer.
In one embodiment of the invention, the N-type substrate layer is an N-type 4H-SiC substrate layer, and the N-type epitaxial layer is an N-type 4H-SiC epitaxial layer.
In an embodiment of the present invention, forming two P-well implantation regions on the inner surfaces of two ends of the N-type epitaxial layer includes:
and injecting Al ions into the inner surfaces of the two ends of the N-type epitaxial layer by using an ion injection method to form two P-well injection regions.
In one embodiment of the present invention, forming an N + implantation region and a P + implantation region on an inner surface of the P-well implantation region includes:
injecting N ions into the inner surface of the P trap injection region by using an ion injection method to form an N + injection region;
and injecting Al ions into the inner surface of the P trap injection region by using an ion injection method to form the P + injection region.
In one embodiment of the present invention, forming an epitaxial channel layer on a portion of the N-type epitaxial layer, a portion of the P-well implant region, and a portion of the N + implant region includes:
and growing a channel layer material on part of the N-type epitaxial layer, part of the P-well injection region and part of the N + injection region by adopting an MBE (molecular beam epitaxy) or CVD (chemical vapor deposition) method to form an epitaxial channel layer.
In one embodiment of the present invention, the material of the epitaxial channel layer is Si.
In one embodiment of the present invention, the thickness of the epitaxial channel layer is in a range of 5 to 10 nm.
In one embodiment of the invention, the materials of the first gate oxide layer and the second gate oxide layer are both SiO2。
In an embodiment of the present invention, after forming the drain on the lower surface of the N-type substrate layer, the method further includes:
and carrying out rapid thermal annealing treatment on the formed N-type substrate layer, the N-type epitaxial layer, the P well injection region, the N + injection region, the P + injection region, the first gate oxide layer, the second gate oxide layer, the source electrode and the drain electrode.
Another embodiment of the present invention provides an epitaxial channel-based MOSFET device, which is prepared by the preparation method according to any one of the above embodiments, and includes:
an N-type substrate layer;
the N-type epitaxial layer is positioned on the N-type substrate layer;
the two P well injection regions are respectively positioned in two ends of the N type epitaxial layer;
the two N + injection regions are respectively positioned in the two P well injection regions;
the two P + injection regions are respectively positioned in the two P well injection regions, and the two N + injection regions are positioned between the two P + injection regions;
the two first gate oxide layers are respectively positioned on part of the N-type epitaxial layer, part of the P-well injection region and part of the N + injection region;
the second gate oxide layer is positioned on the first gate oxide layer and the N-type epitaxial layer;
the two source electrodes are respectively positioned on the P + injection region and the part of the N + injection region at the two ends;
the drain electrode is positioned on the lower surface of the N-type substrate layer;
and the grid electrode is positioned on the second grid oxide layer.
Compared with the prior art, the invention has the beneficial effects that:
1) according to the invention, the epitaxial channel layer is formed, oxidation treatment is carried out on the epitaxial channel layer, and the gate oxide layer is formed by an oxidation method, so that the C cluster problem at the channel in the traditional structure can be effectively avoided, the defect density of the channel is reduced, the mobility of the channel is improved, and the reliability of the device is improved.
2) The first gate oxide layer and the second gate oxide layer have good interface quality, so that the forward characteristic and the application stability of the device can be improved.
3) The epitaxial channel growth process is simple, low in cost and suitable for mass production of devices.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
Fig. 1 is a flowchart of a method for manufacturing an epitaxial channel-based MOSFET device according to an embodiment of the present invention;
fig. 2a-2j are schematic process diagrams of an epitaxial channel-based MOSFET device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a MOSFET device based on an epitaxial channel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1 and fig. 2a to 2j, fig. 1 is a flowchart illustrating a method for manufacturing an epitaxial channel-based MOSFET device according to an embodiment of the present invention, and fig. 2a to 2j are schematic process diagrams illustrating an epitaxial channel-based MOSFET device according to an embodiment of the present invention. The invention provides a preparation method for preparing an MOSFET device based on an epitaxial channel, which comprises the following steps:
Specifically, an N-type substrate layer 1 is selected, and the N-type substrate layer 1 is cleaned by adopting an RCA cleaning standard.
Further, the N-type substrate layer 1 is an N-type 4H-SiC substrate layer.
Specifically, an N-type epitaxial layer 2 is epitaxially grown on the surface of an N-type substrate layer 1 by adopting a chemical vapor deposition process.
Further, the N-type epitaxial layer 2 is an N-type 4H-SiC epitaxial layer.
Specifically, two P-well implantation regions 3 are formed by implanting Al ions into the inner surfaces of both ends of the N-type epitaxial layer 2 by an ion implantation method.
Further, a layer of SiO is deposited on the surface of the N type epitaxial layer 2 by a low-pressure hot-wall chemical vapor deposition method2And then depositing Al to be used as a barrier layer for ion implantation of the P well implantation region 3, and forming the P well implantation region by photoetching and etching.
Performing four times of Al ion implantation on the P-well implantation region at 650 deg.C, sequentially adopting implantation energies of 450keV, 300keV, 200keV and 120keV, and making the implantation dosage be 7.97 × 1013cm-2、4.69×1013cm-2、3.27×1013cm-2And 2.97X 1013cm-2The aluminum ions are implanted into the P-well implantation region to form a P-well implantation region 3.
Cleaning the surface of the silicon carbide by adopting an RCA cleaning standard, and manufacturing a C film for protection after drying; and then carrying out ion activation annealing for 10min in argon atmosphere at 1700-1750 ℃.
And 4, forming an N + injection region 4 and a P + injection region 5 on the inner surface of the P well injection region 3, wherein the two N + injection regions 4 are positioned between the two P + injection regions 5.
Specifically, step 4 may comprise steps 4.1 to 4.2, wherein:
step 4.1, please refer to fig. 2d, N ions are implanted into the inner surface of the P-well implantation region 3 by an ion implantation method to form an N + implantation region 4.
Specifically, N ions are implanted into the inner surface of the P-well implantation region 3 by an ion implantation method to form an N + implantation region 4.
Further, a layer of SiO is deposited on the surfaces of the P-well injection region 3 and the N-type epitaxial layer 2 by a low-pressure hot-wall chemical vapor deposition method2And then depositing Al to be used as a barrier layer for ion implantation of the N + implantation region 4, and forming the N + implantation region by photoetching and etching.
Performing nitrogen ion implantation twice at 650 deg.C, sequentially adopting 80keV and 30keV implantation energies, and making the implantation dosage be 3.9 × 1014cm-2、1.88×1014cm-2And implanted into the N + implant region to form N + implant region 4.
Cleaning the surface of the silicon carbide by adopting an RCA cleaning standard, and manufacturing a C film for protection after drying; and then carrying out ion activation annealing for 10min in argon atmosphere at 1700-1750 ℃.
Step 4.2, please refer to fig. 2e, Al ions are implanted into the inner surface of the P-well implantation region 3 by an ion implantation method to form a P + implantation region 5.
Specifically, the P + implantation region 5 is formed by implanting Al ions into the inner surface of the P-well implantation region 3 by an ion implantation method.
Further, a layer of SiO is deposited on the surfaces of the P well injection region 3, the P + injection region 5 and the N type epitaxial layer 2 by a low-pressure hot-wall chemical vapor deposition method2And then depositing Al to be used as a barrier layer for ion implantation of the P + implantation area 5, and forming the P + implantation area through photoetching and etching.
Performing Al ion implantation twice at 650 deg.C with implantation energy of 90keV and 30keV, and Al ion implantation dosage of 1.88 × 1014cm-2、3.8×1014cm-2And implanted into the P + implant region to form a P + implant region 5.
Cleaning the surface of the silicon carbide by adopting an RCA cleaning standard, and manufacturing a C film for protection after drying; and then carrying out ion activation annealing for 10min in argon atmosphere at 1700-1750 ℃.
Preferably, the depth of the P + implant region 5 is greater than the depth of the P-well implant region 3.
Specifically, a channel layer material is grown on a part of the N-type epitaxial layer 2, a part of the P-well implantation region 3 and a part of the N + implantation region 5 by using an MBE (Molecular beam epitaxy) or CVD (Chemical vapor deposition) method to form the epitaxial channel layer 6, wherein the growth temperature of the MBE method is 650 to 750 degrees celsius, and the growth temperature of the CVD method is 1200 to 1250 degrees celsius.
Preferably, the material of the epitaxial channel layer 6 is Si. In the present embodiment, SiO is formed by oxidizing the epitaxial channel layer 6 made of Si and the N-type epitaxial layer 2 made of SiC2The gate oxide layer can effectively avoid the C cluster problem.
Preferably, the thickness of the epitaxial channel layer 6 is in the range of 5 to 10 nm. The epitaxial channel layer 6 with the thickness of 5-10 nm can ensure that the epitaxial channel layer 6 made of Si material can be completely oxidized in the subsequent oxidation process to form SiO with better quality2And oxidizing the gate oxide layer, thereby forming an interface of the first gate oxide layer and the second gate oxide layer with better quality.
And 6, referring to fig. 2g, thermally oxidizing the epitaxial channel layer 6 and the N-type epitaxial layer 2 to form a first gate oxide layer 7 and a second gate oxide layer 8 on the first gate oxide layer 7 and the N-type epitaxial layer 2.
Wherein, the first gate oxide layer 7 is formed by oxidizing the epitaxial channel layer 6, the second gate oxide layer 8 is formed by oxidizing the N-type epitaxial layer 2, because the epitaxial channel layer 6 is made of Si and the N-type epitaxial layer 2 is made of SiC, the first gate oxide layer 7 and the second gate oxide layer 8 are both SiO2。
In the present embodiment, SiO is formed on the epitaxial channel layer 6 made of Si by an oxidation method2Thus, the C cluster problem can be effectively avoided. Meanwhile, the formed material is SiO2The first gate oxide layer 7 and the material of the first gate oxide layer are SiO2Second gate oxide ofThe layer 8 has a better interface quality, so that the forward characteristics and application stability of the device can be improved.
In step 7, referring to fig. 2h, a source 9 is formed on the P + implantation region 5 and a portion of the N + implantation region 4.
Specifically, the source electrode 9 is formed on the P + implantation region 5 and a part of the N + implantation region 4 by using a magnetron sputtering or electron beam evaporation method.
Preferably, the material of the source electrode 9 is Ti/Al/Ni.
In step 8, referring to fig. 2i, a drain 10 is formed on the lower surface of the N-type substrate layer 1.
Specifically, the drain electrode 10 is formed on the lower surface of the N-type substrate layer 1 by magnetron sputtering or electron beam evaporation.
Preferably, the material of the drain electrode 10 is Ti/Ni.
And 9, carrying out rapid thermal annealing treatment on the whole sample prepared in the steps 1 to 8.
Specifically, the N-type substrate layer 1, the N-type epitaxial layer 2, the P-well implantation region 3, the N + implantation region 4, the P + implantation region 5, the first gate oxide layer 7, the second gate oxide layer 8, the source electrode 9 and the drain electrode 10 formed in the steps 1 to 8 are subjected to rapid thermal annealing treatment.
The process parameters of the rapid thermal annealing are as follows: the temperature is 1000 ℃, and the annealing time is 3 min.
In step 10, referring to fig. 2j, a gate 11 is formed on the second gate oxide layer 8.
Specifically, the gate electrode 11 is formed on the second gate oxide layer 8 using a magnetron sputtering or electron beam evaporation method.
Preferably, the material of the gate electrode 11 is Al.
The invention forms SiO on the epitaxial channel layer 6 made of Si by an oxidation method2Thus, the C cluster problem can be effectively avoided. Meanwhile, the formed material is SiO2The first gate oxide layer 7 and the material of the first gate oxide layer are SiO2The second gate oxide layer 8 has better interface quality, so that the forward characteristic and the application stability of the device can be improved.
The epitaxial channel growth process is simple, low in cost and suitable for mass production of devices.
Example two
Referring to fig. 3, fig. 3 is a schematic structural diagram of an epitaxial channel-based MOSFET device according to an embodiment of the invention. The invention provides an epitaxial channel-based MOSFET device, which is prepared by the preparation method of the embodiment I and comprises the following steps:
an N-type substrate layer 1;
an N-type epitaxial layer 2 located on the N-type substrate layer 1;
two P trap injection regions 3 respectively positioned in two ends of the N type epitaxial layer 2;
two N + injection regions 4 respectively located in the two P-well injection regions 3;
two P + injection regions 5 respectively located in the two P well injection regions 3, and two N + injection regions 4 located between the two P + injection regions 5;
the two first gate oxide layers 7 are respectively positioned on part of the N-type epitaxial layer 2, part of the P well injection region 3 and part of the N + injection region 5;
the second gate oxide layer 8 is positioned above the first gate oxide layer 7 and the N-type epitaxial layer 2;
two source electrodes 9 respectively located on the P + implantation region 5 and the part of the N + implantation region 4 at the two ends;
a drain electrode 10 located on the lower surface of the N-type substrate layer 1;
and the grid electrode 11 is positioned on the second grid oxide layer 8.
Further, the N-type substrate layer 1 is an N-type 4H-SiC substrate layer.
Further, the N-type epitaxial layer 2 is an N-type 4H-SiC epitaxial layer.
Further, the materials of the first gate oxide layer 7 and the second gate oxide layer 8 are both SiO2。
Further, the material of the source electrode 9 is Ti/Al/Ni.
Further, the material of the drain electrode 10 is Ti/Ni.
Further, the material of the gate electrode 11 is Al.
In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic data point described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A preparation method of an MOSFET device based on an epitaxial channel is characterized by comprising the following steps:
selecting an N-type substrate layer (1);
forming an N-type epitaxial layer (2) on the N-type substrate layer (1);
forming two P-well injection regions (3) on the inner surfaces of two ends of the N-type epitaxial layer (2);
forming an N + injection region (4) and a P + injection region (5) on the inner surface of the P well injection region (3), wherein the two N + injection regions (4) are positioned between the two P + injection regions (5);
forming an epitaxial channel layer (6) on part of the N-type epitaxial layer (2), part of the P-well injection region (3) and part of the N + injection region (5);
thermally oxidizing the epitaxial channel layer (6) and the N-type epitaxial layer (2) to form a first gate oxide layer (7) and a second gate oxide layer (8) positioned on the first gate oxide layer (7) and the N-type epitaxial layer (2);
forming a source (9) on the P + implantation region (5) and a part of the N + implantation region (4);
forming a drain electrode (10) on the lower surface of the N-type substrate layer (1);
and forming a grid electrode (11) on the second grid oxide layer (8).
2. Preparation method according to claim 1, characterized in that the N-type substrate layer (1) is an N-type 4H-SiC substrate layer and the N-type epitaxial layer (2) is an N-type 4H-SiC epitaxial layer.
3. Preparation method according to claim 1, characterized in that forming two P-well implant regions (3) on the inner surface of the two ends of the N-type epitaxial layer (2) comprises:
and injecting Al ions into the inner surfaces of two ends of the N-type epitaxial layer (2) by using an ion injection method to form two P-well injection regions (3).
4. The method according to claim 1, wherein forming an N + implant region (4) and a P + implant region (5) on an inner surface of the P-well implant region (3) comprises:
injecting N ions into the inner surface of the P trap injection region (3) by using an ion injection method to form an N + injection region (4);
and injecting Al ions into the inner surface of the P trap injection region (3) by using an ion injection method to form the P + injection region (5).
5. Method of manufacturing according to claim 1, wherein forming an epitaxial channel layer (6) on part of the N-type epitaxial layer (2), part of the P-well implant (3) and part of the N + implant (5) comprises:
and growing a channel layer material on part of the N-type epitaxial layer (2), part of the P-well injection region (3) and part of the N + injection region (5) by adopting an MBE (molecular beam epitaxy) or CVD (chemical vapor deposition) method to form an epitaxial channel layer (6).
6. Method of manufacturing according to claim 1, characterized in that the material of the epitaxial channel layer (6) is Si.
7. The method of manufacturing according to claim 6, wherein the thickness of the epitaxial channel layer (6) is in the range of 5 to 10 nm.
8. Preparation method according to claim 6, characterized in that the materials of the first gate oxide layer (7) and the second gate oxide layer (8) are both SiO2。
9. The method according to claim 1, further comprising, after forming a drain electrode (10) on a lower surface of the N-type substrate layer (1):
and carrying out rapid thermal annealing treatment on the formed N-type substrate layer (1), the N-type epitaxial layer (2), the P well injection region (3), the N + injection region (4), the P + injection region (5), the first gate oxide layer (7), the second gate oxide layer (8), the source electrode (9) and the drain electrode (10).
10. An epitaxial channel-based MOSFET device, wherein the epitaxial channel-based MOSFET device is prepared by the preparation method of any one of claims 1 to 9, and the MOSFET device comprises:
an N-type substrate layer (1);
the N-type epitaxial layer (2) is positioned on the N-type substrate layer (1);
the two P well injection regions (3) are respectively positioned in two ends of the N-type epitaxial layer (2);
the two N + injection regions (4) are respectively positioned in the two P well injection regions (3);
the two P + injection regions (5) are respectively positioned in the two P well injection regions (3), and the two N + injection regions (4) are positioned between the two P + injection regions (5);
two first gate oxide layers (7) respectively positioned on part of the N-type epitaxial layer (2), part of the P-well injection region (3) and part of the N + injection region (5);
the second gate oxide layer (8) is positioned above the first gate oxide layer (7) and the N-type epitaxial layer (2);
two source electrodes (9) respectively positioned on the P + injection region (5) and a part of the N + injection region (4) at two ends;
the drain electrode (10) is positioned on the lower surface of the N-type substrate layer (1);
and the grid electrode (11) is positioned on the second gate oxide layer (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011322803.0A CN114530370B (en) | 2020-11-23 | 2020-11-23 | MOSFET device based on epitaxial channel and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011322803.0A CN114530370B (en) | 2020-11-23 | 2020-11-23 | MOSFET device based on epitaxial channel and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114530370A true CN114530370A (en) | 2022-05-24 |
| CN114530370B CN114530370B (en) | 2023-11-07 |
Family
ID=81619702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011322803.0A Active CN114530370B (en) | 2020-11-23 | 2020-11-23 | MOSFET device based on epitaxial channel and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114530370B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090250705A1 (en) * | 2008-04-02 | 2009-10-08 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device comprising silicon carbide layer and method of manufacturing the same |
| JP2011003825A (en) * | 2009-06-22 | 2011-01-06 | Panasonic Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| KR20110049249A (en) * | 2009-11-04 | 2011-05-12 | 한국전기연구원 | Silicon carbide mosfet with short channel |
| CN102244099A (en) * | 2011-06-23 | 2011-11-16 | 西安电子科技大学 | SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide -Semiconductor Field Effect Transistor) device with epitaxy channel and manufacturing method of SiC IEMOSFET device |
| CN103928344A (en) * | 2014-04-21 | 2014-07-16 | 西安电子科技大学 | Method for improving N-typed DiMOSFET channel mobility based on N-typed nanometer thin layer |
| US20150311076A1 (en) * | 2012-11-28 | 2015-10-29 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device and method of manufacturing same |
| CN106340448A (en) * | 2016-11-28 | 2017-01-18 | 清华大学 | Manufacturing method of gate oxidation layer of SiC power MOSFET device and SiC power MOSFET device |
| CN107658215A (en) * | 2017-09-26 | 2018-02-02 | 中国科学院微电子研究所 | A kind of silicon carbide device and preparation method thereof |
| US20190027568A1 (en) * | 2015-05-26 | 2019-01-24 | Zhuzhou Ccr Times Electric Co., Ltd. | Silicon carbide mosfet device and method for manufacturing the same |
-
2020
- 2020-11-23 CN CN202011322803.0A patent/CN114530370B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090250705A1 (en) * | 2008-04-02 | 2009-10-08 | Mitsubishi Electric Corporation | Silicon carbide semiconductor device comprising silicon carbide layer and method of manufacturing the same |
| JP2011003825A (en) * | 2009-06-22 | 2011-01-06 | Panasonic Corp | Silicon carbide semiconductor device and method of manufacturing the same |
| KR20110049249A (en) * | 2009-11-04 | 2011-05-12 | 한국전기연구원 | Silicon carbide mosfet with short channel |
| CN102244099A (en) * | 2011-06-23 | 2011-11-16 | 西安电子科技大学 | SiC IEMOSFET (Implantation and Epitaxial Metal-Oxide -Semiconductor Field Effect Transistor) device with epitaxy channel and manufacturing method of SiC IEMOSFET device |
| US20150311076A1 (en) * | 2012-11-28 | 2015-10-29 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device and method of manufacturing same |
| CN103928344A (en) * | 2014-04-21 | 2014-07-16 | 西安电子科技大学 | Method for improving N-typed DiMOSFET channel mobility based on N-typed nanometer thin layer |
| US20190027568A1 (en) * | 2015-05-26 | 2019-01-24 | Zhuzhou Ccr Times Electric Co., Ltd. | Silicon carbide mosfet device and method for manufacturing the same |
| CN106340448A (en) * | 2016-11-28 | 2017-01-18 | 清华大学 | Manufacturing method of gate oxidation layer of SiC power MOSFET device and SiC power MOSFET device |
| CN107658215A (en) * | 2017-09-26 | 2018-02-02 | 中国科学院微电子研究所 | A kind of silicon carbide device and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114530370B (en) | 2023-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101859706B (en) | Silicon carbide semiconductor device and manufacturing method thereof | |
| JP6032831B2 (en) | SiC semiconductor device and manufacturing method thereof | |
| CN103928344B (en) | One kind improves N-type DiMOSFET channel mobility method based on N-type nano thin-layer | |
| CN113196499B (en) | Vertical silicon carbide power MOSFET and IGBT and manufacturing method thereof | |
| JP6222771B2 (en) | Method for manufacturing silicon carbide semiconductor device | |
| JP5995347B2 (en) | SiC semiconductor device and manufacturing method thereof | |
| JP6438933B2 (en) | Field effect transistor device having buried well region and epitaxial layer | |
| US20060108589A1 (en) | Semiconductor device | |
| JP2009266871A (en) | Silicon carbide semiconductor device and method of manufacturing same | |
| CN109037333B (en) | Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof | |
| JP2003243653A (en) | Method for manufacturing silicon carbide semiconductor device | |
| WO2010024243A1 (en) | Bipolar semiconductor device and method for manufacturing same | |
| US10510844B2 (en) | Semiconductor device and method of manufacturing same | |
| CN103681256B (en) | A kind of silicon carbide MOSFET device and preparation method thereof | |
| JP2008034464A (en) | Method for manufacturing semiconductor device | |
| CN109686667A (en) | A kind of SiC base MOS device and its preparation method and application | |
| CN112038409A (en) | Double-heterojunction enhanced metal oxide field effect transistor and preparation method thereof | |
| CN107818915B (en) | Method for improving 4H-SiC MOSFET inversion layer mobility by using nitrogen and boron | |
| CN114530370B (en) | MOSFET device based on epitaxial channel and preparation method thereof | |
| CN112038394A (en) | Preparation method of MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of improving stability of threshold voltage | |
| CN114725022A (en) | Based on GaOxPreparation method of-GaN CMOS inverter | |
| CN114530380A (en) | MOSFET device for reducing electric field intensity of oxide layer and preparation method thereof | |
| CN114530377B (en) | MOSFET device integrated with PiN structure temperature sensor and preparation method thereof | |
| CN107871781A (en) | A kind of silicon carbide MOSFET and its manufacture method | |
| CN115631996B (en) | Preparation method of SiC MOSFET device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |