JP2010532905A - スレッドに最適化されたマルチプロセッサアーキテクチャ - Google Patents

スレッドに最適化されたマルチプロセッサアーキテクチャ Download PDF

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JP2010532905A
JP2010532905A JP2010518258A JP2010518258A JP2010532905A JP 2010532905 A JP2010532905 A JP 2010532905A JP 2010518258 A JP2010518258 A JP 2010518258A JP 2010518258 A JP2010518258 A JP 2010518258A JP 2010532905 A JP2010532905 A JP 2010532905A
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processor
processors
memory
instruction
chip
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JP2010532905A5 (enExample
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ラッセル・エイチ・フィッシュ
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
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    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
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    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
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    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
JP2010518258A 2008-06-26 2008-06-27 スレッドに最適化されたマルチプロセッサアーキテクチャ Pending JP2010532905A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/147,332 US8984256B2 (en) 2006-02-03 2008-06-26 Thread optimized multiprocessor architecture
PCT/US2008/068566 WO2009157943A1 (en) 2008-06-26 2008-06-27 Thread optimized multiprocessor architecture

Publications (2)

Publication Number Publication Date
JP2010532905A true JP2010532905A (ja) 2010-10-14
JP2010532905A5 JP2010532905A5 (enExample) 2012-06-07

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JP2010518258A Pending JP2010532905A (ja) 2008-06-26 2008-06-27 スレッドに最適化されたマルチプロセッサアーキテクチャ

Country Status (10)

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US (2) US8984256B2 (enExample)
EP (1) EP2288988A4 (enExample)
JP (1) JP2010532905A (enExample)
KR (1) KR101121606B1 (enExample)
CN (2) CN101796484B (enExample)
AU (1) AU2008355072C1 (enExample)
BR (1) BRPI0811497A2 (enExample)
CA (1) CA2684753A1 (enExample)
RU (1) RU2450339C2 (enExample)
WO (1) WO2009157943A1 (enExample)

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