CN101796484B - 线程优化的多处理器架构 - Google Patents

线程优化的多处理器架构 Download PDF

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CN101796484B
CN101796484B CN200880014972.9A CN200880014972A CN101796484B CN 101796484 B CN101796484 B CN 101796484B CN 200880014972 A CN200880014972 A CN 200880014972A CN 101796484 B CN101796484 B CN 101796484B
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processor
memory
instruction
tomi
chip
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CN101796484A (zh
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拉塞尔·H·菲什
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    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
CN200880014972.9A 2008-06-26 2008-06-27 线程优化的多处理器架构 Active CN101796484B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/147,332 US8984256B2 (en) 2006-02-03 2008-06-26 Thread optimized multiprocessor architecture
US12/147,332 2008-06-26
PCT/US2008/068566 WO2009157943A1 (en) 2008-06-26 2008-06-27 Thread optimized multiprocessor architecture

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CN101796484B true CN101796484B (zh) 2015-02-04

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US (2) US8984256B2 (enExample)
EP (1) EP2288988A4 (enExample)
JP (1) JP2010532905A (enExample)
KR (1) KR101121606B1 (enExample)
CN (2) CN101796484B (enExample)
AU (1) AU2008355072C1 (enExample)
BR (1) BRPI0811497A2 (enExample)
CA (1) CA2684753A1 (enExample)
RU (1) RU2450339C2 (enExample)
WO (1) WO2009157943A1 (enExample)

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