BRPI0811497A2 - Arquitetura multiprocessador com encadeamento otimizado - Google Patents

Arquitetura multiprocessador com encadeamento otimizado

Info

Publication number
BRPI0811497A2
BRPI0811497A2 BRPI0811497-8A2A BRPI0811497A BRPI0811497A2 BR PI0811497 A2 BRPI0811497 A2 BR PI0811497A2 BR PI0811497 A BRPI0811497 A BR PI0811497A BR PI0811497 A2 BRPI0811497 A2 BR PI0811497A2
Authority
BR
Brazil
Prior art keywords
multiprocessor architecture
optimized chain
optimized
chain
multiprocessor
Prior art date
Application number
BRPI0811497-8A2A
Other languages
English (en)
Portuguese (pt)
Inventor
Russell H Fish Iii
Original Assignee
Russell H Fish Iii
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Russell H Fish Iii filed Critical Russell H Fish Iii
Publication of BRPI0811497A2 publication Critical patent/BRPI0811497A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
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    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
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    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30163—Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
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    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
BRPI0811497-8A2A 2008-06-26 2008-06-27 Arquitetura multiprocessador com encadeamento otimizado BRPI0811497A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/147,332 US8984256B2 (en) 2006-02-03 2008-06-26 Thread optimized multiprocessor architecture
PCT/US2008/068566 WO2009157943A1 (en) 2008-06-26 2008-06-27 Thread optimized multiprocessor architecture

Publications (1)

Publication Number Publication Date
BRPI0811497A2 true BRPI0811497A2 (pt) 2014-11-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
BRPI0811497-8A2A BRPI0811497A2 (pt) 2008-06-26 2008-06-27 Arquitetura multiprocessador com encadeamento otimizado

Country Status (10)

Country Link
US (2) US8984256B2 (enExample)
EP (1) EP2288988A4 (enExample)
JP (1) JP2010532905A (enExample)
KR (1) KR101121606B1 (enExample)
CN (2) CN101796484B (enExample)
AU (1) AU2008355072C1 (enExample)
BR (1) BRPI0811497A2 (enExample)
CA (1) CA2684753A1 (enExample)
RU (1) RU2450339C2 (enExample)
WO (1) WO2009157943A1 (enExample)

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CN101796484B (zh) 2015-02-04
AU2008355072B2 (en) 2012-05-31
WO2009157943A1 (en) 2009-12-30
CN104536723A (zh) 2015-04-22
AU2008355072A1 (en) 2010-01-14
RU2009145519A (ru) 2011-06-20
KR20100032359A (ko) 2010-03-25
RU2450339C2 (ru) 2012-05-10
US20080320277A1 (en) 2008-12-25
US20150234777A1 (en) 2015-08-20
CN101796484A (zh) 2010-08-04
US8984256B2 (en) 2015-03-17
KR101121606B1 (ko) 2012-02-28
JP2010532905A (ja) 2010-10-14
AU2008355072C1 (en) 2012-11-29
CA2684753A1 (en) 2009-12-28
EP2288988A1 (en) 2011-03-02
EP2288988A4 (en) 2012-06-27

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