AU2008355072C1 - Thread optimized multiprocessor architecture - Google Patents

Thread optimized multiprocessor architecture Download PDF

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Publication number
AU2008355072C1
AU2008355072C1 AU2008355072A AU2008355072A AU2008355072C1 AU 2008355072 C1 AU2008355072 C1 AU 2008355072C1 AU 2008355072 A AU2008355072 A AU 2008355072A AU 2008355072 A AU2008355072 A AU 2008355072A AU 2008355072 C1 AU2008355072 C1 AU 2008355072C1
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Australia
Prior art keywords
processor
processors
memory
tomi
instruction
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AU2008355072A
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AU2008355072B2 (en
AU2008355072A1 (en
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Russell H. Fish Iii
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
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    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
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    • G06F9/30003—Arrangements for executing specific machine instructions
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    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
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    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
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    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
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    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
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    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Semiconductor Memories (AREA)
AU2008355072A 2006-02-03 2008-06-27 Thread optimized multiprocessor architecture Ceased AU2008355072C1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2008355072A AU2008355072C1 (en) 2006-02-03 2008-06-27 Thread optimized multiprocessor architecture

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US60/764,955 2006-02-03
AU2007212342A AU2007212342B2 (en) 2006-02-03 2007-02-05 Thread optimized multiprocessor architecture
US12/147,332 US8984256B2 (en) 2006-02-03 2008-06-26 Thread optimized multiprocessor architecture
US12/147,332 2008-06-26
PCT/US2008/068566 WO2009157943A1 (en) 2008-06-26 2008-06-27 Thread optimized multiprocessor architecture
AU2008355072A AU2008355072C1 (en) 2006-02-03 2008-06-27 Thread optimized multiprocessor architecture

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AU2007212342A Division AU2007212342B2 (en) 2006-02-03 2007-02-05 Thread optimized multiprocessor architecture

Publications (3)

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AU2008355072A1 AU2008355072A1 (en) 2010-01-14
AU2008355072B2 AU2008355072B2 (en) 2012-05-31
AU2008355072C1 true AU2008355072C1 (en) 2012-11-29

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AU2008355072A Ceased AU2008355072C1 (en) 2006-02-03 2008-06-27 Thread optimized multiprocessor architecture

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US (2) US8984256B2 (enExample)
EP (1) EP2288988A4 (enExample)
JP (1) JP2010532905A (enExample)
KR (1) KR101121606B1 (enExample)
CN (2) CN101796484B (enExample)
AU (1) AU2008355072C1 (enExample)
BR (1) BRPI0811497A2 (enExample)
CA (1) CA2684753A1 (enExample)
RU (1) RU2450339C2 (enExample)
WO (1) WO2009157943A1 (enExample)

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