JP2010503205A5 - - Google Patents

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Publication number
JP2010503205A5
JP2010503205A5 JP2009526621A JP2009526621A JP2010503205A5 JP 2010503205 A5 JP2010503205 A5 JP 2010503205A5 JP 2009526621 A JP2009526621 A JP 2009526621A JP 2009526621 A JP2009526621 A JP 2009526621A JP 2010503205 A5 JP2010503205 A5 JP 2010503205A5
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JP
Japan
Prior art keywords
integrated system
shorten
exposure
oxygen
limiting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009526621A
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English (en)
Japanese (ja)
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JP2010503205A (ja
JP5489717B2 (ja
Filing date
Publication date
Priority claimed from US11/513,634 external-priority patent/US8771804B2/en
Priority claimed from US11/513,446 external-priority patent/US8747960B2/en
Priority claimed from US11/514,038 external-priority patent/US8241701B2/en
Application filed filed Critical
Priority claimed from PCT/US2007/018270 external-priority patent/WO2008027216A2/en
Publication of JP2010503205A publication Critical patent/JP2010503205A/ja
Publication of JP2010503205A5 publication Critical patent/JP2010503205A5/ja
Application granted granted Critical
Publication of JP5489717B2 publication Critical patent/JP5489717B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009526621A 2006-08-30 2007-08-17 金属堆積のために基板表面を調整する方法および統合システム Expired - Fee Related JP5489717B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US11/513,634 US8771804B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a copper surface for selective metal deposition
US11/514,038 2006-08-30
US11/513,446 US8747960B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide
US11/514,038 US8241701B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a barrier surface for copper deposition
US11/513,634 2006-08-30
US11/513,446 2006-08-30
PCT/US2007/018270 WO2008027216A2 (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013266333A Division JP5820870B2 (ja) 2006-08-30 2013-12-25 金属堆積のために基板表面を調整する方法および統合システム

Publications (3)

Publication Number Publication Date
JP2010503205A JP2010503205A (ja) 2010-01-28
JP2010503205A5 true JP2010503205A5 (enExample) 2010-09-24
JP5489717B2 JP5489717B2 (ja) 2014-05-14

Family

ID=41202298

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2009526621A Expired - Fee Related JP5489717B2 (ja) 2006-08-30 2007-08-17 金属堆積のために基板表面を調整する方法および統合システム
JP2013266333A Expired - Fee Related JP5820870B2 (ja) 2006-08-30 2013-12-25 金属堆積のために基板表面を調整する方法および統合システム

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2013266333A Expired - Fee Related JP5820870B2 (ja) 2006-08-30 2013-12-25 金属堆積のために基板表面を調整する方法および統合システム

Country Status (5)

Country Link
JP (2) JP5489717B2 (enExample)
CN (2) CN101558186B (enExample)
MY (2) MY171542A (enExample)
SG (1) SG174752A1 (enExample)
TW (1) TWI393186B (enExample)

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US20090269507A1 (en) * 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8227344B2 (en) * 2010-02-26 2012-07-24 Tokyo Electron Limited Hybrid in-situ dry cleaning of oxidized surface layers
JP5560144B2 (ja) * 2010-08-31 2014-07-23 東京エレクトロン株式会社 半導体装置の製造方法
JP2012054306A (ja) * 2010-08-31 2012-03-15 Tokyo Electron Ltd 半導体装置の製造方法
WO2012029475A1 (ja) * 2010-08-31 2012-03-08 東京エレクトロン株式会社 半導体装置の製造方法
CN102468265A (zh) * 2010-11-01 2012-05-23 中芯国际集成电路制造(上海)有限公司 连接插塞及其制作方法
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8603913B1 (en) * 2012-12-20 2013-12-10 Lam Research Corporation Porous dielectrics K value restoration by thermal treatment and or solvent treatment
US9040385B2 (en) * 2013-07-24 2015-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for cleaning substrate surface for hybrid bonding
CN105682856A (zh) * 2013-10-22 2016-06-15 东曹Smd有限公司 经优化的纹理化表面及优化的方法
EP3155655B1 (en) * 2014-06-16 2021-05-12 Intel Corporation Selective diffusion barrier between metals of an integrated circuit device
US9997405B2 (en) * 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9768060B2 (en) * 2014-10-29 2017-09-19 Applied Materials, Inc. Systems and methods for electrochemical deposition on a workpiece including removing contamination from seed layer surface prior to ECD
CN109844930B (zh) * 2016-10-02 2024-03-08 应用材料公司 以钌衬垫改善铜电迁移的经掺杂选择性金属覆盖
JP6842159B2 (ja) * 2016-12-13 2021-03-17 サムコ株式会社 プラズマ処理方法
US10438846B2 (en) 2017-11-28 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Physical vapor deposition process for semiconductor interconnection structures
JP2019192892A (ja) 2018-04-18 2019-10-31 東京エレクトロン株式会社 処理システムおよび処理方法
SG11202106002VA (en) 2018-12-05 2021-07-29 Lam Res Corp Void free low stress fill
KR102301933B1 (ko) * 2018-12-26 2021-09-15 한양대학교 에리카산학협력단 반도체 소자의 제조 방법
US12261081B2 (en) 2019-02-13 2025-03-25 Lam Research Corporation Tungsten feature fill with inhibition control
US20220344205A1 (en) * 2019-09-25 2022-10-27 Tokyo Electron Limited Substrate liquid processing method and substate liquid processing apparatus
US11555250B2 (en) * 2020-04-29 2023-01-17 Applied Materials, Inc. Organic contamination free surface machining
KR20230008822A (ko) * 2020-05-08 2023-01-16 램 리써치 코포레이션 코발트, 니켈 및 이의 합금들의 전기 도금
US20220375751A1 (en) * 2021-05-24 2022-11-24 Applied Materials, Inc. Integrated epitaxy and preclean system
CN115394911B (zh) * 2022-06-06 2025-10-03 昕原半导体(杭州)有限公司 阻变式存储器的下电极及制备方法
CN120376473B (zh) * 2025-06-26 2025-09-23 昆山科比精工设备有限公司 一种硅片镀铜前处理用转运装置

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US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
US6144099A (en) * 1999-03-30 2000-11-07 Advanced Micro Devices, Inc. Semiconductor metalization barrier
US6365516B1 (en) * 2000-01-14 2002-04-02 Advanced Micro Devices, Inc. Advanced cobalt silicidation with in-situ hydrogen plasma clean
JP2001355074A (ja) * 2000-04-10 2001-12-25 Sony Corp 無電解メッキ処理方法およびその装置
WO2001082368A2 (en) * 2000-04-25 2001-11-01 Tokyo Electron Limited Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module
JP2001326192A (ja) * 2000-05-16 2001-11-22 Applied Materials Inc 成膜方法及び装置
US6475893B2 (en) * 2001-03-30 2002-11-05 International Business Machines Corporation Method for improved fabrication of salicide structures
JP2003034876A (ja) * 2001-05-11 2003-02-07 Ebara Corp 触媒処理液及び無電解めっき方法
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
US7008872B2 (en) * 2002-05-03 2006-03-07 Intel Corporation Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures
US6875693B1 (en) * 2003-03-26 2005-04-05 Lsi Logic Corporation Via and metal line interface capable of reducing the incidence of electro-migration induced voids
JP2004363155A (ja) * 2003-06-02 2004-12-24 Ebara Corp 半導体装置の製造方法及びその装置
JP2005116630A (ja) * 2003-10-03 2005-04-28 Ebara Corp 配線形成方法及び装置
JP2007042662A (ja) * 2003-10-20 2007-02-15 Renesas Technology Corp 半導体装置
US20050095855A1 (en) * 2003-11-05 2005-05-05 D'urso John J. Compositions and methods for the electroless deposition of NiFe on a work piece
JP4503356B2 (ja) * 2004-06-02 2010-07-14 東京エレクトロン株式会社 基板処理方法および半導体装置の製造方法

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