JP2010282352A - Ｄｍａ転送制御装置 - Google Patents

Ｄｍａ転送制御装置 Download PDF

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Publication number
JP2010282352A
JP2010282352A JP2009134126A JP2009134126A JP2010282352A JP 2010282352 A JP2010282352 A JP 2010282352A JP 2009134126 A JP2009134126 A JP 2009134126A JP 2009134126 A JP2009134126 A JP 2009134126A JP 2010282352 A JP2010282352 A JP 2010282352A
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JP
Japan
Prior art keywords
dma
dma transfer
transfer
time
determination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009134126A
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English (en)
Japanese (ja)
Other versions
JP2010282352A5 (cg-RX-API-DMAC7.html
Inventor
Naoko Shinohara
直子 篠原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009134126A priority Critical patent/JP2010282352A/ja
Priority to US12/789,741 priority patent/US8285889B2/en
Publication of JP2010282352A publication Critical patent/JP2010282352A/ja
Publication of JP2010282352A5 publication Critical patent/JP2010282352A5/ja
Priority to US13/476,484 priority patent/US20120290745A1/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP2009134126A 2009-06-03 2009-06-03 Ｄｍａ転送制御装置 Pending JP2010282352A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009134126A JP2010282352A (ja) 2009-06-03 2009-06-03 Ｄｍａ転送制御装置
US12/789,741 US8285889B2 (en) 2009-06-03 2010-05-28 DMA transfer control device
US13/476,484 US20120290745A1 (en) 2009-06-03 2012-05-21 Dma transfer control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009134126A JP2010282352A (ja) 2009-06-03 2009-06-03 Ｄｍａ転送制御装置

Publications (2)

Publication Number Publication Date
JP2010282352A true JP2010282352A (ja) 2010-12-16
JP2010282352A5 JP2010282352A5 (cg-RX-API-DMAC7.html) 2012-04-05

Family

ID=43301557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009134126A Pending JP2010282352A (ja) 2009-06-03 2009-06-03 Ｄｍａ転送制御装置

Country Status (2)

Country Link
US (2) US8285889B2 (cg-RX-API-DMAC7.html)
JP (1) JP2010282352A (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021082103A (ja) * 2019-11-21 2021-05-27 ルネサスエレクトロニクス株式会社 調停回路、データ転送システム、及び、調停回路による調停方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0814484D0 (en) * 2008-08-07 2008-09-10 Icera Inc Dma engine
US9465755B2 (en) 2011-07-18 2016-10-11 Hewlett Packard Enterprise Development Lp Security parameter zeroization
JP5888050B2 (ja) * 2012-03-27 2016-03-16 株式会社ソシオネクスト 半導体集積回路およびそのｄｍａ制御方法
JP7192427B2 (ja) * 2018-11-19 2022-12-20 オムロン株式会社 制御システムおよび制御装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000099455A (ja) * 1998-09-21 2000-04-07 Nec Corp 先着優先バス競合制御方式
JP2002197050A (ja) * 2000-12-27 2002-07-12 Fuji Xerox Co Ltd 調停制御システム、調停制御方法及び調停制御装置
JP2004133572A (ja) * 2002-10-09 2004-04-30 Fanuc Ltd バス調停機能を備える装置及び数値制御装置
JP2006171887A (ja) * 2004-12-13 2006-06-29 Mitsubishi Electric Corp バス制御装置および情報処理システム

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3202272B2 (ja) 1991-10-16 2001-08-27 日本電気株式会社 Ｄｍａコントローラ
US5752081A (en) * 1995-06-08 1998-05-12 Vlsi Technology, Inc. Signalling system and method for allowing a direct memory access (DMA) input/output (I/O) device on the peripheral component interconnect (PCI) bus to perform DMA transfers
US7356346B2 (en) * 2002-06-28 2008-04-08 Lucent Technologies Inc. Method of uplink scheduling for data communication
US6993639B2 (en) * 2003-04-01 2006-01-31 Hewlett-Packard Development Company, L.P. Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell
JP2005004563A (ja) 2003-06-13 2005-01-06 Canon Inc Ｄｍａ転送制御装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000099455A (ja) * 1998-09-21 2000-04-07 Nec Corp 先着優先バス競合制御方式
JP2002197050A (ja) * 2000-12-27 2002-07-12 Fuji Xerox Co Ltd 調停制御システム、調停制御方法及び調停制御装置
JP2004133572A (ja) * 2002-10-09 2004-04-30 Fanuc Ltd バス調停機能を備える装置及び数値制御装置
JP2006171887A (ja) * 2004-12-13 2006-06-29 Mitsubishi Electric Corp バス制御装置および情報処理システム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021082103A (ja) * 2019-11-21 2021-05-27 ルネサスエレクトロニクス株式会社 調停回路、データ転送システム、及び、調停回路による調停方法

Also Published As

Publication number Publication date
US20100312940A1 (en) 2010-12-09
US8285889B2 (en) 2012-10-09
US20120290745A1 (en) 2012-11-15

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