JP2010252095A - Image sensor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce in size an image sensor module by effectively utilizing the dead space in the module. <P>SOLUTION: The present invention relates to an image sensor module comprising a first wiring board which has a first surface and a second surface and in which a first wiring pattern having a first land is provided at a first surface side; a solid-state image sensor chip in which a functional surface having a photodetection part and a non-photodetection part including a terminal pad is provided on a side opposite to a side of the first wiring board and which is provided on the first surface of the first wiring board; a second wiring board which has a first surface and a second surface, in which a second wiring pattern having a second land is provided at a first surface side and a third wiring pattern having a third land is provided at a second surface side, in which the second surface side is turned toward a side of the solid-state image sensor chip and the third land is electrically connected with the terminal pad of the solid-state image sensor chip via a conductive pad, and which is provided on the non-photodetection part of the solid-state image sensor chip; and a connection member for electrically connecting the second land of the second wiring board and the first land of the first wiring board. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an image sensor module having a solid-state image sensor chip and a wiring board, and more particularly to an image sensor module suitable for miniaturization thereof.

  In recent years, many portable electronic devices such as cellular phones and portable PCs include an imaging input unit. The imaging input unit mainly includes a wiring board on which a solid-state imaging device chip and its peripheral components are mounted, and a lens unit (hereinafter, the imaging input unit as a component is referred to as an “imaging device module”). In such an image sensor module of a portable electronic device, it is generally required that the image sensor module can be accommodated in a smaller space and can cope with imaging with a larger number of pixels. In recent years, solid-state image sensor chips having 5 million pixels or 8 million pixels have been put on the market. The wiring board is designed to be miniaturized by multilayering, high-density layout of patterns, built-in components, and the like.

  Japanese Patent Application Laid-Open No. 2004-120615 discloses an image sensor module technology. In this disclosure, a wiring board having peripheral components on the outer periphery of the solid-state imaging device chip is used. In such a configuration, if the chip size is increased by increasing the number of pixels of the solid-state imaging device chip, the overall size of the two-dimensional image inevitably increases. Further, since the wiring board bears all the peripheral circuit portions required as a module, the number of layers tends to increase, and as a result, the size of the module in the thickness direction does not decrease much.

JP 2004-120615 A

  The present invention has been made in consideration of the above circumstances, and in an image sensor module having a solid-state image sensor chip and a wiring board, an image sensor capable of contributing to downsizing by utilizing a dead space in the module. The purpose is to provide modules.

  In order to solve the above-described problem, an imaging element module which is one embodiment of the present invention includes a first wiring pattern having a first surface and a second surface, and having a first land. A functional surface having a first wiring board provided on the surface side and a non-light receiving portion including a light receiving portion and a terminal pad, the functional surface being directed to a side opposite to the first wiring board side; And a second wiring pattern having a solid state imaging device chip provided on the first surface of the first wiring board, a first surface, a second surface, and a second land. Is provided on the first surface side, a third wiring pattern having a third land is provided on the second surface side, and the second surface side is directed to the solid-state imaging device chip side, and The third land and the terminal pad of the solid-state imaging device chip are electrically connected via a conductive bump, and the solid-state imaging is performed. A second wiring board provided on the non-light-receiving portion of the element chip; the second land on the first face of the second wiring board; and the first face of the first wiring board. And a connecting member for electrically connecting the first land.

  That is, in this imaging device module, the peripheral circuit portion required as a module is divided into a first wiring board located below the solid-state imaging device chip and a second wiring provided on the non-light-receiving portion of the solid-state imaging device chip. It can be shared with the board. Therefore, it is possible to reduce the size of the first wiring board that controls the two-dimensional size as a module. Further, the circuit pattern configuration necessary for the first wiring board is also reduced, and the thickness of the first wiring board can be reduced by reducing the number of wiring layers.

  On the other hand, the second wiring board on the solid-state imaging device chip, which has been introduced with the simplification of the first wiring board, is provided on the non-light-receiving portion of the solid-state imaging element chip. Absent. Further, since the lens for forming an image on the light receiving portion of the solid-state image pickup device chip is provided apart from the solid-state image pickup device chip, a second wiring board is provided on the non-light receiving portion of the solid-state image pickup device chip. However, the thickness does not increase as a module.

  Therefore, the imaging element module is realized by making use of the dead space in the module to achieve miniaturization.

  ADVANTAGE OF THE INVENTION According to this invention, in the image pick-up element module which has a solid-state image pick-up element chip | tip and a wiring board, the image pick-up element module which can contribute to size reduction using the dead space in a module can be provided.

1 is a cross-sectional view schematically showing a configuration of an image sensor module according to an embodiment of the present invention. FIG. 2 is a plan view illustrating an example of a positional relationship between a solid-state imaging element chip 30 and a wiring board 20 illustrated in FIG. 1. FIG. 6 is a plan view showing another example of the positional relationship between the solid-state imaging device chip 30 and the wiring board 20 shown in FIG. 1. Sectional drawing which shows typically the example of a specific structure of the wiring board 10 shown in FIG. Sectional drawing which shows typically the example of a specific structure of the wiring board 20 shown in FIG.

  As an embodiment of the present invention, a plurality of the second wiring boards may be present at different positions on the non-light receiving portion of the solid-state imaging device chip. Since the non-light-receiving portion of the solid-state imaging device chip is usually provided so as to surround the light-receiving portion, a plurality of second wiring boards can be provided at different positions on these non-light-receiving portions. is there. Every place is a dead space, and this makes it possible to further reduce the size by utilizing the dead space in the module.

  Further, as an embodiment, the second wiring board has a square-shaped plate shape having an opening at a position facing the light receiving portion of the solid-state image sensor chip, and the non-solid state of the solid-state image sensor chip. It can be provided on the light receiving part. In this case, the second wiring board is set in a square shape corresponding to a non-light-receiving portion provided so as to surround the light-receiving portion of the solid-state imaging device chip. According to this, the utilization of the dead space in the module can be improved, and the process of flip-chip connecting the solid-state imaging device chip on the second wiring board and electrically and mechanically connecting them can be facilitated. become.

  In addition, as an embodiment, it may further include a lens unit including a lens provided to face the light receiving portion of the solid-state imaging element chip. Adding a lens unit can increase added value. Further, it can be supplied to the market as a module assembled so that the lens is arranged at an appropriate position with respect to the light receiving portion of the solid-state imaging device chip.

  As an embodiment, the second wiring board may be a wiring board on which the components are mounted on the first surface or embedded. By mounting components on the second wiring board, it is possible to reduce the burden of component mounting on the first wiring board. Thereby, the further miniaturization of the 1st wiring board which controls the two-dimensional magnitude | size as a module is possible.

  As an embodiment, the first wiring board may include a fourth wiring pattern having a fourth land for external connection on the second surface of the first wiring board. . By providing the external connection lands on the back surface of the first wiring board in this manner, for example, a separate substrate or a lead frame is unnecessary as a member for external connection, which is preferable for downsizing of the module.

  Further, as an embodiment, the first wiring board or the second wiring board may include a vertical electrical connection path having a conductive composition. The vertical electrical connection path having the conductive composition can be formed in a smaller area than the vertical electrical connection path by the plating layer using the through hole, and can contribute to miniaturization as a module. It is also suitable for more complex pattern design.

  As an embodiment, the connecting member can be a bonding wire. Generally, a bonding wire is a member frequently used for bonding a solid-state imaging device chip onto a terminal pad, and this embodiment uses this as a member for electrical connection between the first and second wiring boards. .

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing the configuration of an image sensor module according to an embodiment of the present invention. As shown in FIG. 1, the imaging element module includes a wiring board 10, a wiring board 20, a solid-state imaging element chip 30, a bonding wire 41, a conductive bump 42, an underfill resin 51, a lens 61, and a lens holding portion 62.

  The wiring board 10 includes at least a wiring pattern on the front surface including the lands 11 and a wiring pattern on the back surface including the lands 12, and these wiring patterns are electrically connectable by a not-shown vertical conductor. Yes. The wiring board 20 includes at least a wiring pattern on the front surface including the land 21, a component (surface mounted passive element component) 22 mounted on the surface of the wiring pattern, and a wiring pattern on the back surface including the land 23. Yes. The wiring patterns on the front and back surfaces can be electrically connected by a not-shown vertical conductor. The solid-state imaging device chip 30 includes a light receiving unit 31, and a terminal pad 32 is positioned near the surface end of the surface on which the light receiving unit 31 is provided.

  Between the wiring board 10 and the solid-state image sensor chip 30, an adhesive layer (not shown) is disposed and fixed therebetween. In addition, a solder resist layer (not shown) is provided on each of the front and back surfaces of the wiring board 10 and the wiring board 20. This solder resist layer is a protective film formed on the entire surface except on a land to which a conductive material such as solder, conductive bump or bonding wire can be connected. About the wiring board 10 and the wiring board 20, the example of a more concrete structure is mentioned later (FIG. 4, FIG. 5).

  The wiring board 10 functions as a substrate on which the solid-state imaging device chip 30 is placed and held at substantially the center thereof, and electrically, from the terminal pads 32 of the solid-state imaging device chip 30, the conductive bumps 32, the wiring board 20, It is an intermediary substrate that mediates a route from the land 11 to the land 12 via the bonding wire 41. The land 12 serves as a terminal for external connection as the image sensor module. If the terminals for external connection are provided on the wiring board 10 in this way, the module can be made compact. The land 11 is provided outside the periphery of the place where the solid-state imaging device chip 30 is located on the wiring board 10.

  The wiring board 20 is a component mounting board disposed on the functional surface of the solid-state imaging device chip 30 so as to avoid the light receiving portion 31. Electrically, the land 11 on the wiring board 10 is connected to the wiring board 10 via the bonding wire 41 and the path of the land 21, and is further connected to the terminal pad 32 of the solid-state imaging device chip 30 via the conductive bump 32. The solid-state image sensor chip 30 is also connected to each other through the path of the land 23. The form of component mounting is not limited to the form in which the component 22 is mounted on the surface thereof, and may be provided in the board (embedded).

  The solid-state imaging device chip 30 has a light receiving unit 31 in which photoelectric conversion elements are integrated and formed on the functional surface, and a circuit for controlling and driving the elements of the light receiving unit 31 is further integrated on the functional surface. An area (hereinafter also referred to as a non-light receiving portion) that has been made is also secured. The light receiving part 31 is located at the approximate center of the functional surface, and the non-light receiving part is located in a frame shape surrounding the light receiving part 31 when seen in a plan view. A terminal pad 32 that is a terminal of the solid-state imaging device chip 30 is formed in the vicinity of the outer end portion of the non-light receiving portion. The wiring board 20 can be provided on the non-light-receiving portion of the solid-state image sensor chip 30 and at least on a region overlapping the terminal pad 32.

  The bonding wire 41 is a connection member that connects the land 21 on the wiring board 20 and the land 11 on the wiring board 10 so as to be electrically connected. The material is gold (Au), for example, and a well-known gold bonding technique can be used for connection with the land 11 and the land 21. For the purpose of electrically connecting the lands 21 on the wiring board 20 and the lands 11 on the wiring board 10, the bonding wire 41 is replaced with, for example, a film-like wiring board having a polyimide resin base material. It is also possible to use a flat cable or the like.

  The conductive bumps 42 are members that electrically connect the lands 23 of the wiring board 20 and the terminal pads 32 of the solid-state image sensor chip 30. The material of the conductive bumps 42 is, for example, gold (Au). The state of electrical connection between the wiring board 20 and the solid-state imaging device chip 30 via the conductive bumps 42 can be obtained by applying a so-called flip chip connection technique.

  That is, for example, by connecting a gold wire on the terminal pad 32 of the solid-state imaging device chip 30 by using a wire bonding tool and cutting the gold wire near the base of the connection, first, a conductive bump is formed on the terminal pad 32. 42 can be shaped. Then, a paste-like resin material to be used as the underfill resin 51 is applied on the solid-state imaging element chip 30 or a film-like resin material to be used as the underfill resin 51 is pasted on the lower surface of the wiring board 20. The element chip 30 and the wiring board 20 can be electrically and mechanically connected as illustrated by pressurizing and heating the element chip 30 and the wiring board 20 in the stacking direction in the illustrated positional relationship.

  The lens holding unit 62 holds the lens 61 so that the position of the lens 61 is at a desired distance from the light receiving unit 31 of the solid-state imaging device chip 30. The lens 61 is provided so that the optical axis thereof is orthogonal to the surface of the light receiving unit 31 of the solid-state image sensor chip 30, and guides light from the side opposite to the side where the solid-state image sensor chip 30 is located. An image is formed on 31. The lens 61 and the lens holding part 62 constitute a lens unit.

  In the imaging element module described above, a part of the functions that the wiring board 10 located under the solid-state imaging element chip 30 should bear is transferred to the wiring board 20. That is, the peripheral circuit portion of the solid-state image sensor chip 30 necessary as a module is provided on the wiring board 20. Therefore, the wiring board 10 can be made smaller. Since the wiring board 10 dominates the planar area of the module as can be seen in the figure, the effect of miniaturizing the module by providing the wiring board 20 is great.

  In addition, the pattern design of the wiring board 10 can be made simpler. For this reason, use of a wiring board with many wiring layers can be avoided. As a result, the wiring board 10 can be made thinner to contribute to making the module thinner.

  The wiring board 20 is a space necessary for the separation between the light receiving unit 31 and the lens 61 of the solid-state image sensor chip 30, and is arranged in a region on the non-light receiving unit. Therefore, the optical function between the light receiving unit 31 and the lens 61 is not impaired, and it is arranged in a space that can be regarded as a conventional dead space, so that the module does not increase in size.

  As described above, the size of the image pickup device module is reduced both in plan and in the thickness direction.

  Next, FIG. 2 is a plan view showing an example of the positional relationship between the solid-state imaging element chip 30 and the wiring board 20 shown in FIG. In FIG. 2, the same components as those already described with reference to FIG. In FIG. 2, the main purpose is to explain the positional relationship between the solid-state imaging device chip 30 and the wiring board 20, and therefore other elements are not shown in principle.

  In this example, two wiring boards 20 are provided on the solid-state imaging device chip 30 at positions facing each other with the light receiving unit 31 interposed therebetween. By providing a plurality of wiring boards 20 in this way, the effect of downsizing utilizing the dead space in the module is enhanced. Based on the same idea, two or three wiring boards 20 can be provided along any two or more of the four sides of the solid-state imaging element chip 30. Of course, four sheets can be provided along the four sides.

  Reference numeral 43 denotes a terminal pad that is not provided for connection to the wiring board 20 among terminal pads provided on the solid-state imaging element chip 30 and is electrically connected to a land on the wiring board 10. It is a bonding wire. As described above, the terminal pads provided on the solid-state imaging element chip 30 can be used for connection to the wiring board 10 by the bonding wires when the wiring board 20 is not connected.

  As described above, the solid-state image sensor chip 30 and the wiring board 20 can be electrically and mechanically connected by applying a flip chip connection technique. In the case of the positional relationship with 20, attention should be paid to the weighted position by the flip chip bonder. That is, the row positions of the conductive bumps 42 that serve as the legs that support the flip chip connection are biased in the plane of the wiring board 20, and when a load is applied around the central region of the wiring board 20, the wiring board 20 is tilted and fixed. There is a possibility. Therefore, it is preferable that the weighting at the time of the flip chip connection process is performed around the row position where the land 23 exists.

  Next, FIG. 3 is a plan view showing another example of the positional relationship between the solid-state imaging element chip 30 and the wiring board 20 shown in FIG. In FIG. 3, the same components as those already described with reference to FIG. 3 mainly explains the positional relationship between the solid-state imaging device chip 30 and the wiring board 20, and other elements are not shown in principle.

  In this example, the wiring board 20 has a square plate shape with an opening at a position facing the light receiving portion 31 of the solid-state image sensor chip 30 and is provided on the non-light-receiving portion of the solid-state image sensor chip 30. ing. Thus, by providing the wiring board 20 in a square shape, the effect of miniaturization utilizing the dead space in the module is enhanced. Further, in this embodiment, the process of flip-chip connecting the solid-state imaging element chip 30 on the wiring board 20 and electrically and mechanically connecting them is easier. That is, since the row positions of the conductive bumps 42 that serve as the legs that support the flip chip connection are along the four sides of the wiring board 20, the weights may be uniformly distributed over the specific area.

  Next, FIG. 4 is a cross-sectional view schematically showing a specific configuration example of the wiring board 10 shown in FIG. 4, the same components as those shown in FIG. 1 are denoted by the same reference numerals. The wiring board 10 used in the image sensor module shown in FIG. 1 is not limited to the one shown in FIG. However, it will be described as an example. In FIG. 4, solder resists 17 and 18 that are not shown in FIG. 1 and the internal structure of the wiring board 10 are shown.

  The wiring board 10 includes a wiring pattern on the front surface including the lands 11, a wiring pattern on the back surface including the lands 12, an inner wiring layer 141, 161, an insulating layer 14, 15, 16, an interlayer connector 14 a, 15 a, 16a, solder resist 17 and 18 are provided. Therefore, the wiring board 10 is a four-layer board having four wiring layers separated by the insulating layers 14, 15, and 16.

  The insulating layers 14, 15, and 16 are rigid layers made of, for example, glass epoxy resin. The wiring pattern on the front surface including the lands 11, the wiring pattern on the back surface including the lands 12, and the wiring layers 141 and 161 on the inner layer are obtained by, for example, performing desired patterning on a copper foil by a known photolithography technique. Is a layer. The interlayer connectors 14a, 15a, and 16a are conductive composition connectors that pass through the insulating layers 14, 15, and 16 and are sandwiched between wiring patterns, respectively. Functions as a road. The solder resists 17 and 18 are protective films formed entirely on the insulating layer 14 or the insulating layer 16 except on lands to which solder or bonding wires can be connected.

  The manufacturing process will be briefly described. First, the wiring pattern including the land 12, the wiring layer 141, the insulating layer 14, the partial stacked body including the interlayer connection body 14a, the wiring pattern including the land 11, the wiring layer 161, the insulating layer 16, A partial laminated body having the interlayer connector 16a is formed. In the former partial laminated body, first, a paste-like conductive composition (a fine silver particle, for example, is dispersed in a resin) to be the interlayer connector 14a on the copper foil to be the wiring layer 141. The composition is printed in the form of bumps.

  Subsequently, the conductive composition is dried and cured, and a prepreg to be the insulating layer 14 is laminated on the copper foil so as to penetrate the bumps of the conductive composition. Then, another copper foil to be a wiring pattern including the land 12 is laminated on the prepreg so as to cover the heads of the penetrating bumps. Further, in this state, the prepreg is cured by compressing and pressing in the laminating direction and heated to be integrated into a partial laminated body centered on the insulating layer 14. Thereafter, the copper foils on both sides of the partial laminate are patterned to form a wiring pattern including the land 12 and a wiring layer 141. A partial laminate including the wiring pattern including the land 11, the wiring layer 161, the insulating layer 16, and the interlayer connector 16a can be formed in the same manner.

  In the partial laminated body centering on the insulating layer 14, after patterning the copper foils on both sides, a paste-like conductive composition to be the interlayer connection body 15 a is formed in a bump shape at a predetermined position on the wiring layer 141. Printed on. Subsequently, the conductive composition is dried and cured, and a prepreg to be the insulating layer 15 is laminated on the partial laminate so as to penetrate the bumps of the conductive composition.

  And the latter partial laminated body mentioned above is laminated | stacked on the prepreg which should be used as the insulating layer 15, so that it may cover the head of the penetrated bump. Further, in this state, the prepreg that should be made into the insulating layer 15 is compressed and pressurized in the laminating direction and heated to be integrated to obtain a laminated body having three insulating layers. Thereafter, layers of solder resists 17 and 18 are formed on both sides of the laminate, and finished to a wiring board 10 as shown in FIG.

  In addition, about the wiring pattern of the surface containing the land 11, and the wiring pattern of the back surface containing the land 12, the patterning can also be performed after the latter lamination | stacking (entire lamination | stacking). Further, it is appropriate to perform Ni / Au plating on the lands 11 and 12 so that the surfaces thereof are suitable for connection with other conductors such as bonding connection.

  In such a wiring board 10, the electrical connection path in the vertical direction is derived from the conductive bump printed by the conductive composition printing. For example, the electrical connection in the vertical direction by a plating layer using a through hole. It can be formed in an area smaller than the path. Therefore, even when complicated wiring is required as the wiring board 10, the wiring board 10 can be made smaller.

  Next, FIG. 5 is a cross-sectional view schematically showing a specific configuration example of the wiring board 20 shown in FIG. In FIG. 5, the same components as those shown in FIG. The wiring board 20 used in the imaging element module shown in FIG. 1 is not limited to the one shown in FIG. However, it will be described as an example. FIG. 5 shows solder resists 261 and 262 not shown in FIG. 1 and the internal structure of the wiring board 20.

  The wiring board 20 includes a wiring pattern on the front surface including the lands 21, a wiring pattern on the back surface including the lands 23, an inner wiring layer 222, 223, 224, 225, insulating layers 201, 202, 203, and 204. 205, interlayer connection body 231, 232, 234, 235, through-hole conductor 233, solder resist 261, 262. Further, it has a surface-mounted passive element component 241 that is embedded in the board and mounted on the wiring layer 222 via the solder 251. Furthermore, the surface-mounted passive element component 22 is also connected to the surface wiring pattern via the solder 22a. Has been implemented. The wiring board 20 is a six-layer substrate having six wiring layers separated by insulating layers 201 to 205.

  Each of the insulating layers 201 to 205 is a rigid layer made of, for example, a glass epoxy resin. The wiring pattern on the front surface including the lands 21, the wiring pattern on the back surface including the lands 23, and the inner wiring layers 222 to 225 are each obtained by, for example, performing desired patterning on a copper foil by a known photolithography technique. Is a layer. The interlayer connectors 231, 232, 234, and 235 are conductive composition connectors that pass through the insulating layers 201, 202, 204, and 205 and are sandwiched between the wiring patterns, respectively. It functions as an electrical connection path.

  Furthermore, the solder resists 261 and 262 are protective films formed on the entire surface of the insulating layer 201 or the insulating layer 205 except on the lands to which solder, conductive bumps or bonding wires can be connected. The through-hole conductor 233 is a vertical electrical connection path formed as a copper plating layer on the inner wall surface of the through-hole that penetrates the insulating layer 203.

  The manufacturing process of the wiring board 20 is similar to the wiring board 10 described above in that the interlayer connectors 231, 232, 234, and 235 made of a conductive composition are used. The main difference is the difference in the number of wiring layers and the incorporation of the component 241.

  First, the wiring pattern including the land 21, the wiring layer 225, the insulating layer 205, the first partial stacked body including the interlayer connector 235, the wiring pattern including the land 23, the wiring layer 222, the insulating layer 201, and the interlayer connector 231. And a third partial laminated body having a wiring layer 223, a wiring layer 224, an insulating layer 203, and a through-hole conductor 233, respectively. About the 1st, 2nd partial laminated body, it can form in the way similar to description of the partial laminated body in FIG. The third partial laminate can be formed by forming a through hole in a normal double-sided copper-clad substrate and growing a copper plating layer on the inner wall surface to form a through-hole conductor 233.

  On the first partial stacked body, an interlayer connector 234 and an insulating layer (prepreg stage) 204 are formed in the same manner as the interlayer connector 15a and the insulating layer 15 in FIG. Further, the interlayer connector 232 and the insulating layer (prepreg stage) 202 are also formed on the third partial stacked body in the same manner as the interlayer connector 15a and the insulating layer 15 in FIG. Thereafter, an opening is formed in the third partial laminate in accordance with the position of the component 241.

  On the second partial laminate, the component 241 is mounted at a predetermined position on the wiring layer 222 by using the solder 251. For this purpose, for example, the procedures of screen printing of cream solder to be the solder 251, placement of the component 241 by the mounter, and reflow of the cream solder can be adopted as in the case of normal component surface mounting.

  Thereafter, the second (lower), third (middle), and first (upper) partial laminates are stacked and pressed and heated with a press. As a result, the prepreg to be the insulating layer 202 and the prepreg to be the insulating layer 204 are completely cured and integrated as a whole to obtain a laminate having five insulating layers. In this integration, due to the fluidity of each prepreg obtained by heating, each prepreg enters the space around the component 241 and the space inside the through-hole conductor 233 so that no gap is generated. The wiring layers 222 and 224 are electrically connected to the interlayer connectors 232 and 234, respectively.

  Thereafter, layers of solder resists 261 and 262 are formed on both sides of the laminate. Further, the component 22 is mounted by executing a normal surface mounting process to finish the wiring board 20 as shown in FIG. In addition, about the wiring pattern of the surface containing the land 21, and the wiring pattern of the back surface containing the land 23, the patterning can also be performed after the whole lamination | stacking. Further, it is appropriate to perform Ni / Au plating on the lands 21 and 23 so that the surfaces thereof are suitable for bonding connection and flip chip connection, respectively.

  In such a wiring board 20, the electrical connection path in the vertical direction is derived from the conductive bumps printed by the conductive composition except for a part thereof, and can be formed in a small area. Therefore, even when complicated wiring is required as the wiring board 20, the wiring board 20 can be made smaller. Further, the mounting density of the components is improved by incorporating the components 241, and a large number of components can be mounted in a small area. Therefore, it is possible to further avoid a situation where components must be mounted on the wiring board 10 that controls the two-dimensional size as a module, and contribute to further miniaturization as a module.

  DESCRIPTION OF SYMBOLS 10 ... Wiring board (1st wiring board), 11 ... Land (1st land), 12 ... Land (4th land), 14 ... Insulating layer, 14a ... Interlayer connection body (conductivity by electroconductive composition printing) 15 ... Insulating layer, 15a ... Interlayer connection body (derived from conductive bump by conductive composition printing), 16 ... Insulating layer, 16a ... Interlayer connection body (conductive composition printing) 17 ... Solder resist, 18 ... Solder resist, 20 ... Wiring board (second wiring board), 21 ... Land (second land), 22 ... Surface mounted passive element parts 22a ... solder, 23 ... land (third land), 30 ... solid-state imaging device chip, 31 ... light receiving portion, 32 ... terminal pad, 41 ... bonding wire, 42 ... conductive bump, 43 ... bonding wire, 51 ... under Fill resin, 61 ... lens, 62 ... lens holding part, 141 ... wiring layer (wiring pattern), 161 ... wiring layer (wiring pattern), 201 ... insulating layer, 202 ... insulating layer, 203 ... insulating layer, 204 ... insulating layer , 205 ... insulating layer, 222 ... wiring layer (wiring pattern), 223 ... wiring layer (wiring pattern), 224 ... wiring layer (wiring pattern), 225 ... wiring layer (wiring pattern), 231 ... interlayer connector (conductive) Derived from conductive bump by composition printing), 232 ... Interlayer connection (derived from conductive bump by conductive composition printing), 233 ... Through-hole conductor, 234 ... Interlayer connection (conductive composition) Conductive bump by physical printing), 235... Interlayer connection body (derived from conductive bump by conductive composition printing), 241... Surface mounted passive element component (substrate built-in component), 2 1 ... solder, 261 ... solder resist, 262 ... solder resist.

Claims (9)

A first wiring board having a first wiring pattern having a first surface and a second surface and having a first land on the first surface side;
A functional surface having a light receiving portion and a non-light receiving portion including a terminal pad, the functional surface being directed to a side opposite to the side of the first wiring board; A solid-state imaging device chip provided on the surface of
A second wiring pattern having a first surface and a second surface and having a second land is provided on the first surface side, and a third wiring pattern having a third land is provided in the second surface. The second land side is directed to the solid-state image sensor chip side, and the third land and the terminal pad of the solid-state image sensor chip are electrically connected via a conductive bump. A second wiring board connected and provided on the non-light-receiving part of the solid-state imaging device chip;
A connecting member that electrically connects the second land on the first surface of the second wiring board and the first land on the first surface of the first wiring board. An image sensor module characterized by the above.   2. The image pickup device module according to claim 1, wherein a plurality of the second wiring boards exist at different positions on the non-light-receiving portion of the solid-state image pickup device chip.   The second wiring board has a square-shaped plate shape having an opening at a position facing the light receiving portion of the solid-state image sensor chip, and is provided on the non-light-receiving portion of the solid-state image sensor chip. The image pickup device module according to claim 1, wherein the image pickup device module is provided.   The image pickup device module according to claim 1, further comprising a lens unit including a lens provided to face the light receiving portion of the solid-state image pickup device chip.   The imaging device module according to claim 1, wherein the second wiring board is a wiring board on which the components are mounted on the first surface or embedded.   The imaging device according to claim 1, wherein the first wiring board includes a fourth wiring pattern having a fourth land for external connection on the second surface of the first wiring board. module.   The image sensor module according to claim 1, wherein the first wiring board includes a vertical electrical connection path having a conductive composition.   The imaging device module according to claim 1, wherein the second wiring board includes a vertical electrical connection path having a conductive composition.   The imaging device module according to claim 1, wherein the connection member is a bonding wire.

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