JP2010245098A - Metal core substrate, conductive member for metal plate, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily manufacture a metal plate having two functions, namely a portion covered with an insulating layer and a portion connected electrically to the outside. <P>SOLUTION: A conductive member 11 includes a Cu-based base material 12 with an Sn based surface layer 14 formed on its surface, and an intermetallic compound layer 13 comprising a Cu-Sn intermetallic component or Ni-Sn intermetallic component formed between the Sn-based surface layer 14 and the Cu-based base material 12. The surface roughness of the surface contacting the Sn-based surface layer 14 of the intermetallic compound layer 13 is 0.05-0.3 μm in terms of arithmetic mean roughness Ra, and the ten-point mean roughness Rz is 0.5-3.0 μm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a metal core substrate in which a metal plate is disposed as a core material of a circuit board, a metal plate of the metal core substrate, a conductive member suitable for use as the metal plate, and a method of manufacturing the same.

A metal core substrate is formed by arranging a metal plate as a core material of a circuit board, and is excellent in heat dissipation, mechanical strength, shielding properties, and the like. In recent years, along with demands for higher performance of automobiles, securing a large cabin space, and the like, they have been widely used in vehicles as substrates for realizing compact and high-density mounting.
Examples of this type of metal core substrate include those described in Patent Document 1 to Patent Document 5. In the metal core substrates described in these patent documents, an insulating layer is formed on the surface of a metal plate such as aluminum or copper as a core, a circuit pattern is formed on the upper surface, and electronic components are mounted on the circuit pattern. It is like that.

  Among these, in the metal core substrate described in Patent Document 1, the portion where the circuit pattern is formed through the insulating layer is the heat radiating plate portion, and both end portions are the external connection terminal plate portions. A part of the core metal plate is exposed from the insulating layer. And it is stored and fixed in a box-shaped case made of resin in a state where the heat generating element and the driving component are mounted on the heat radiating plate portion. Moreover, the male connector part is integrally formed in the case, and it arrange | positions so that the terminal plate part of a metal core board may protrude outward in the male connector part, The terminal plate part in the male connector part An external female connector can be connected.

In Patent Document 2, a part of the insulating layer of the metal core substrate is removed to expose the metal plate, and the exposed portion is subjected to Ni plating or Au plating to form a solder connection pad. Patent Document 3 and Patent Document 4 also describe that a plating film is formed on the metal plate so that a part of the metal plate can be electrically connected to the outside.
On the other hand, in Patent Document 5, when a metal plate made of a rolled copper plate having a small surface roughness is used, the surface of the metal plate is roughened by etching or a pulse electrolysis technique in order to improve adhesion to the insulating layer. It is described. Roughening the surface of the metal plate to improve the adhesion with the insulating layer is also described in Patent Document 3.

JP 2006-253428 A JP 2004-172425 A Japanese Patent Laid-Open No. 2002-2223070 JP 2003-332752 A JP 2008-223063 A

By the way, in this kind of metal core substrate, as represented by Patent Document 1, both a part where an electronic component is mounted such as a heat radiating plate part and a part which is electrically connected to the outside such as a terminal plate part. In the former case, the metal plate serving as the core is covered with the insulating layer in the former, and is exposed from the insulating layer in the latter. In this embodiment, since the surface of the metal plate is generally smooth at the portion covered with the insulating layer, the insulating layer is not directly formed on the metal plate as described in Patent Document 3 and Patent Document 5. In order to improve the adhesion to the insulating layer, it is necessary to roughen the metal plate. On the other hand, in the external connection portion, the metal plate is exposed from the insulating layer as described in Patent Documents 2 to 4. In addition, it is necessary to plate the exposed metal plate.
In either case, the metal plate cannot be used as it is, and the roughening process and the partial processing of the plating process are necessary, and the productivity is poor.

  The present invention has been made in view of such circumstances, and an object thereof is to easily manufacture a metal plate having two functions of a portion covered by an insulating layer and a portion electrically connected to the outside. To do.

In order to solve this problem, the present invention proposes a conductive member for a metal plate, a metal plate manufactured from the conductive member, a metal core substrate using the metal plate, and a manufacturing method thereof.
The conductive member for a metal plate of the present invention has a Cu-based substrate, and a Sn-based surface layer is formed on the surface, and a Cu-Sn intermetallic compound or a Cu-Sn intermetallic compound between the Sn-based surface layer and the Cu-based substrate. In the conductive member in which the intermetallic compound layer having the Ni—Sn intermetallic compound is formed, the surface roughness of the surface in contact with the Sn-based surface layer of the intermetallic compound layer is an arithmetic average roughness Ra of 0. It is 05 to 0.35 μm, and the ten-point average roughness Rz is 0.5 to 3.0 μm.

That is, the Sn-based surface layer formed on the outermost layer has electrical characteristics such as good contact and solderability as a conductive member, and is widely used for connector terminals, lead frames, and the like. The Cu—Sn intermetallic compound or the Ni—Sn intermetallic compound intermetallic compound layer formed under the Sn-based surface layer is not necessarily uniform in film thickness and has irregularities. By setting the surface roughness of the irregularities in the above range, when using the conductive member as a metal plate, the exposed intermetallic compound layer is removed by removing the Sn-based surface layer for the portion covered with the insulating layer. The surface has moderate irregularities, and the insulating layer can be bonded with high bonding strength. Moreover, since the portion not covered with the insulating layer has good electrical characteristics as a conductive member due to the Sn-based surface layer, it can be used as an electrical connection portion with the outside as it is.
In this case, when the surface roughness of the surface of the intermetallic compound layer in contact with the Sn-based surface layer is smaller than the above range, the unevenness is almost eliminated, and good bonding strength with the insulating layer cannot be obtained. If the above range is exceeded, the bonding strength with the insulating layer will increase, but an intermetallic compound layer with large irregularities will be present under the Sn-based surface layer. This is not preferable because the resistance is increased.

The metal plate of the present invention is characterized in that a part of the Sn-based surface layer on the surface of the conductive member is removed, and the surface of the intermetallic compound layer is exposed.
Furthermore, the metal core substrate of the present invention is characterized in that an exposed portion of the intermetallic compound layer in the metal plate is covered with an insulating layer.

  And the manufacturing method of the metal plate of this invention plated either Ni or Ni alloy, Cu or Cu alloy on the surface of Cu-type base material, and plated Sn or Sn alloy on it, and each plating After forming the layer, by heating and reflowing, between the Cu-based substrate and the outermost Sn-based surface layer, an intermetallic compound having a Ni-Sn intermetallic compound or a Cu-Sn intermetallic compound The method includes a step of manufacturing a conductive member in which a compound layer is formed, and a step of removing a part of the Sn-based surface layer in the conductive member to expose a surface of the intermetallic compound layer.

  The method for manufacturing a metal core substrate of the present invention includes a step of manufacturing a metal plate by the method for manufacturing a metal plate and forming an insulating layer on the exposed intermetallic compound layer.

  According to the present invention, the intermetallic compound layer under the outermost Sn-based surface layer has moderate irregularities, and when used as a metal plate, the portion covered with the insulating layer is Sn-based. When the surface layer is removed, the insulating layer can be bonded with high bonding strength due to the unevenness of the exposed intermetallic compound layer surface, while the portion not covered by the insulating layer is formed by the Sn-based surface layer having excellent electrical characteristics. It can be used as it is as an electrical connection part with the outside as it is, and also when it is used as a connector terminal, good insertability can be obtained. Therefore, a metal plate that has two different functions, a part that has improved bondability to the insulating layer and a part that has improved electrical connection reliability and connector terminals without special post-processing. Easy to make.

It is sectional drawing which shows one Embodiment of the manufacturing method of the metal core board | substrate which concerns on this invention to process order. It is the expanded sectional view which modeled and showed the surface layer part of one embodiment of the conductive member for metal plates concerning the present invention. It is sectional drawing which shows a use condition about one Embodiment of the metal core board | substrate which concerns on this invention. It is a front view which shows notionally the apparatus for measuring the dynamic friction coefficient of an electrically-conductive member.

Embodiments of the present invention will be described below.
First, the metal core substrate will be described. As shown in FIG. 3, the metal core substrate 1 is composed of a circuit board portion 2 arranged at the center in the length direction and connector terminal portions 3 arranged at both ends. It is formed. In the circuit board portion 2, both surfaces of a metal plate 4 serving as a core are covered with an insulating layer 5, a circuit conductor 6 is formed on the insulating layer 5, and an electronic component 7 is mounted thereon. On the other hand, the connector terminal portion 3 has both end portions not covered by the insulating layer 5 of the metal plate 4 as the connector terminal portion 3 as it is, and the external connector terminal 8 is connected in a fitted state as indicated by a two-dot chain line. It has become so.
Further, the metal plate 4 is formed by removing a part of the outermost surface layer of the central portion to be the connector terminal portion 3 and exposing the surface of the inner layer in the metal plate conductive member 11 described below. is there.

Next, the metal plate conductive member 11 will be described.
As shown in FIG. 2, the metal plate conductive member 11 of this embodiment has a Cu—Sn intermetallic compound layer 13 and a Sn-based surface layer 14 formed in this order on the surface of the Cu-based substrate 12. The Cu—Sn intermetallic compound layer 13 is further composed of a Cu ₃ Sn layer 15 and a Cu ₆ Sn ₅ layer 16.
The Cu-based substrate 12 is made of, for example, a plate made of Cu or a Cu alloy. The material of the Cu alloy is not necessarily limited, but oxygen-free copper, tough pitch copper, Cu-Zr alloy, Cu-Cr-Zr alloy, Cu-Fe-P alloy is excellent in press workability while having conductivity. For example, OFC, TC, TAMAC4, C151, MZC1, ZC, TAMAC194 manufactured by Mitsubishi Shindoh Co., Ltd. are preferably used.

As will be described later, the Cu—Sn intermetallic compound layer 13 is an alloy layer formed by diffusing a Cu alloy plated on the Cu base 12 and Sn on the surface by reflow treatment. The Cu—Sn intermetallic compound layer 13 is formed to a thickness of 0.05 to 2 μm, preferably 0.1 μm or more as a whole, and is further disposed on the Cu-based substrate 12. The Cu ₃ Sn layer 15 and the Cu ₆ Sn ₅ layer 16 disposed on the Cu ₃ Sn layer 15 are configured. Further, at least one of the Cu—Sn intermetallic compound layer 13 and the Sn-based surface layer 14 contains S (sulfur) in a range of 10 to 100 ppm. In this case, the Cu—Sn intermetallic compound layer 13 as a whole is uneven, and the surface roughness of the surface in contact with the Sn-based surface layer 14 is 0.05 to 0.35 μm in terms of arithmetic average roughness Ra. In addition, the ten-point average roughness Rz is 0.5 to 3.0 μm.

The reason why the arithmetic average roughness Ra is set to 0.05 to 0.35 μm is that when the connector terminal portion 3 is used, a smaller Ra is preferable because the insertion / extraction force is reduced, but an Sn-based surface layer as described later. In order to ensure good bonding strength with the insulating layer 5 from the surface when 14 is removed, Ra is required to be 0.05 μm or more, and if the irregularities become larger than 0.35 μm, the Sn-based surface layer This is because, when the connector terminal portion 3 is used while being coated with 14, the unevenness of the Cu—Sn intermetallic compound layer 13 becomes a resistance and the insertion / extraction force increases, which is not preferable.
On the other hand, with regard to the ten-point average roughness Rz, when Rz is 0.5 μm or more, the anchor effect for the insulating layer 5 functions effectively and the bonding strength can be increased, but the peaks and valleys are locally too large. And cause defects. When Rz exceeds 3.0 μm, Cu of the Cu-based substrate 12 diffuses at a high temperature and the Cu—Sn alloy layer 13 grows, and the Cu ₆ Sn ₅ layer 16 reaches the surface of the conductive member 11, thereby Then, Cu oxide is formed on the surface, and the contact resistance is increased. Therefore, Rz is preferably up to 3.0 μm.
S described above is effective for adjusting the irregularities on the surface of the Cu—Sn intermetallic compound layer 13 to an appropriate range. If it exceeds 100 ppm, the plating film becomes brittle, which is not preferable. 20 ppm to 50 ppm is more preferable.

Further, _Cu 3 Sn layer 15 is arranged under one of the Cu-Sn intermetallic compound layer 13 covers the Cu Keimotozai 12, the area coverage is 60 to 100%. If this area coverage is low and less than 60%, Cu of the Cu-based substrate 12 diffuses at high temperatures, so that the Cu—Sn intermetallic compound layer 13 grows and reaches the surface of the conductive member 11. As a result, Cu oxide is formed on the surface, and the contact resistance increases. Since at least 60% or more of the Cu-based substrate 12 is covered with the Cu ₃ Sn layer 15, an increase in contact resistance at high temperatures can be prevented. More preferably, 80% or more is covered.
This area coverage can be confirmed from a surface scanning ion image (SIM image) obtained by observing a cross-section of the film with a focused ion beam (FIB) and observing with a scanning ion microscope (SIM). it can.

The average thickness of the _Cu 3 Sn layer 15 is a 0.01 to 0.5 [mu] m, in which case the average thickness is as small as less than 0.01μm are suppressed diffusion of Cu Cu Keimotozai 11 effects Becomes scarce. On the other hand, if it exceeds 0.5 μm, the Cu ₃ Sn layer 15 is changed to the Sn-rich Cu ₆ Sn ₅ layer 16 at a high temperature, and accordingly, the Sn-based surface layer 14 is reduced and the contact resistance is increased. . This average thickness is a portion where the Cu ₃ Sn layer 15 is present, and is an average value when the thickness is measured at a plurality of locations.
In addition, since this Cu-Sn intermetallic compound layer 13 is alloyed by diffusion of Cu plated on the Cu-based substrate 12 and Sn on the surface, depending on conditions such as reflow treatment, In some cases, the entire Cu plating layer is diffused to form the Cu—Sn intermetallic compound layer 13, but the Cu plating layer may remain. When this Cu plating layer remains, the Cu plating layer has a thickness of 0.01 to 0.1 μm, for example.

  The outermost Sn-based surface layer 14 is formed by performing reflow treatment after electrolytic plating of Sn or an Sn alloy, and has a thickness of 0.05 to 2.5 μm, for example. When the thickness of the Sn-based surface layer 14 is less than 0.05 μm, Cu diffuses at high temperatures and Cu oxide is easily formed on the surface, so that contact resistance increases, and solderability and Corrosion resistance also decreases. On the other hand, when the thickness exceeds 2.5 μm, the effect of hardening the surface base by the Cu—Sn intermetallic compound layer 13 existing in the lower layer of the flexible Sn-based surface layer 14 is thinned, and insertion / extraction at the time of use as the connector terminal portion 3 Power increases.

Next, such a conductive member 11 and a series of methods for manufacturing the metal core substrate 1 from the conductive member 11 will be described with reference to FIG.
First, as shown in FIG. 1A, a Cu or Cu alloy plate material is prepared as a Cu-based substrate 12, and the surface is cleaned by degreasing, pickling, etc., and then Cu plating and Sn plating are performed. By sequentially performing in this order, a Cu plating layer 21 and a Sn plating layer 22 are formed as shown in FIG. In addition, pickling or rinsing is performed between the plating processes.
As the conditions for Cu plating, a copper sulfate bath containing copper sulfate (CuSO ₄ ) and sulfuric acid (H ₂ SO ₄ ) as main components is used in the plating bath, and chlorine ions (Cl ⁻ ) are added for leveling. . The plating temperature is 35 to 55 ° C., and the current density is 20 to 60 A / dm ² .
As the conditions for Sn plating, a sulfuric acid bath mainly composed of sulfuric acid (H ₂ SO ₄ ) and stannous sulfate (SnSO ₄ ) is used as a plating bath, the plating temperature is 15 to 35 ° C., and the current density is 10 to 10. 30 A / dm ² . Further, in the Sn plating bath, an aromatic brightener (for example, benzothiazoles) containing S as a regulator is added in a range of 0.1 to 10 mg / L. With this additive component, the S component is taken in during Sn plating, and the shape of the interface between the Cu-Sn intermetallic compound layer and the Sn-based surface layer can be finely adjusted during the reflow process.

By making Cu plating at a high current density of 20 A / dm ² or more, the particles are roughened to make the plating surface moderately uneven, and the Cu-Sn intermetallic compound layer by subsequent reflow treatment has a good surface roughness. Can do. When the current density exceeds 60 A / dm ² , the unevenness becomes too large and the insertion / extraction force when used as a connector terminal increases.
Moreover, if the current density of Sn plating is less than 10 A / dm ² , the effect of forming a dense surface layer is low because the Sn grain boundary density is low, while if the current density exceeds 30 A / dm ² , the current efficiency is increased. This is not desirable because it significantly decreases.

All the plating processes are performed at a higher current density than a general plating technique. In this case, the plating solution agitation technology is important. However, by using a method of spraying the plating solution at a high speed toward the processing plate or a method of flowing the plating solution in parallel with the processing plate, A fresh plating solution can be supplied quickly, and a uniform plating layer can be formed in a short time with a high current density. The flow rate of the plating solution is desirably 0.5 m / second or more on the surface of the treatment plate. In addition, in order to enable the plating process at a current density that is an order of magnitude higher than that of the prior art, an insoluble anode such as a Ti plate coated with iridium oxide (IrO ₂ ) having a high anode limit current density is used as the anode. It is desirable.
These plating conditions are summarized as shown in Table 1 and Table 2 below.

And after giving these two types of plating processes, it heats and performs a reflow process. The reflow treatment is a treatment in which the treated material after plating is heated at a temperature of 240 to 300 ° C. for 10 to 90 seconds in a heating furnace having a CO reducing atmosphere and then cooled using 10 to 90 ° C. water. .
By performing this reflow treatment in a reducing atmosphere, it is possible to prevent the formation of a tin oxide film having a high melting temperature on the surface of the Sn plating, and to perform the reflow treatment at a lower temperature and in a shorter time. It becomes easy to produce an intermetallic compound structure.

As described above, after the two-layer plating is performed on the surface of the Cu-based substrate 12 under the plating conditions shown in Tables 1 and 2, the reflow treatment is performed, as shown in FIG. The conductive member 11 having the surface covered with the Cu ₃ Sn layer 15, the Cu ₆ Sn ₅ layer 16 formed thereon, and the Sn-based surface layer 14 formed on the outermost surface is manufactured. In FIG. 1C, the space between the Cu-based substrate 12 and the Sn-based surface layer 14 is displayed as a Cu—Sn intermetallic compound layer 13.

  Next, in order to use the conductive member 11 manufactured as described above as the metal plate 4 of the metal core substrate 1 shown in FIG. 3, as shown in FIG. The Sn-based surface layer 14 that is the outermost surface layer is removed. When this Sn-based surface layer 14 is removed, a mask 23 is coated on a region to be the connector terminal portion 3 in the conductive member 11, and pure Sn such as L80 manufactured by Reybold Co., Ltd. is etched to form a Cu-Sn alloy. By immersing in an etching solution for stripping a plating film made of a component that does not corrode for 5 minutes, the Sn-based surface layer 14 in a region not covered by the mask 23 is removed, and the underlying Cu—Sn intermetallic compound layer 13 is formed. Exposed. The Cu—Sn intermetallic compound layer 13 is formed with Ra and Rz having a predetermined surface roughness as described above, and on the other hand, the region to be the connector terminal portion 3 covered with the mask 23. Then, the Sn-based surface layer 14 maintains a smooth surface. The state shown in FIG. 1D where the Sn-based surface layer 14 is partially removed and the Cu—Sn intermetallic compound layer 13 is exposed is the metal plate 4.

Next, as shown in FIG. 1E, the insulating layer 5 made of resin is coated on the portion of the metal plate 4 where the Cu—Sn intermetallic compound layer 13 is exposed. This insulating layer 5 is formed by laminating an adhesive sheet (prepreg) obtained by thermocompression bonding a resin of epoxy resin or polyimide resin, or by impregnating a glass cloth of a reinforcing material into a semi-cured state. It is formed by a method such as applying in a liquid state and curing.
When the circuit conductor 6 is formed on the insulating layer 5, the metal core substrate 1 is completed. The circuit conductor 6 is formed by laminating a copper foil on the insulating layer 5 and is formed by a method such as pattern etching of a necessary portion.

Next, examples of the present invention will be described.
A TC material manufactured by Mitsubishi Shindoh Co., Ltd. having a thickness of 0.25 mm was used as a Cu alloy plate (Cu-based substrate), and Cu and Sn plating treatments were sequentially performed thereon. In this case, as shown in Table 3, a plurality of samples were prepared by changing the current density of each plating treatment. Regarding the target thickness of each plating layer, the thickness of the Cu plating layer was 0.3 μm, and the thickness of the Sn plating layer was 1.5 μm. In addition, a water washing step for washing the plating solution from the surface of the treatment material was inserted between these two types of plating steps.
In the plating treatment in this example, an insoluble anode of a Ti plate coated with iridium oxide was sprayed on the Cu alloy plate at a high speed.
After performing the above two types of plating treatments, a reflow treatment was performed on the treated material. This reflow treatment was performed 1 minute after the last Sn plating treatment and heated at 270 ° C. for 20 seconds.

With respect to the treatment material produced by performing the plating treatment and the reflow treatment in this way, the cross section thereof was observed, and the S content in the Sn-based surface layer was measured by glow discharge optical emission spectrometry (GD-OES).
Treatment material cross-section of this embodiment, the result of energy dispersive X-ray spectroscopy using a transmission electron microscope (TEM-EDS analysis), on the Cu-based substrate, _Cu 3 Sn layer, _Cu 6 Sn ₅ layer, The Sn-type surface layer has a three-layer structure, and the surface of the Cu ₆ Sn ₅ layer was uneven. In addition, there is a discontinuous Cu ₃ Sn layer at the interface between the Cu ₆ Sn ₅ layer and the Cu-based substrate, and the Cu ₃ Sn layer Cu observed by a scanning ion microscope (FIB-SIM image) of a cross section by a focused ion beam. The surface coverage with respect to the system substrate was 60% or more. Further, the thickness of the Sn-based surface layer was measured with this transmission electron microscope, and the minimum film thickness was obtained.

Next, with respect to this treatment material, the region assuming the connector portion is covered with a mask, the Sn-based surface layer is removed using the above-described plating film peeling etchant, and the exposed Cu-Sn intermetallic compound is exposed. As the surface roughness of the layer, arithmetic average roughness Ra and ten-point average roughness Rz were measured.
This surface roughness is obtained by using a scanning confocal infrared laser microscope LEXT OLS-3000-IR manufactured by Olympus Co., Ltd. on the surface of the exposed Cu—Sn intermetallic compound layer. The distance was obtained by irradiating light, measuring the distance from the reflected light, and continuously measuring the distance while linearly scanning the laser light along the surface of the Cu—Sn intermetallic compound layer.
Table 3 summarizes the above test conditions and the measurement results of the surface roughness of the Cu—Sn intermetallic compound layer, the minimum film thickness of the Sn-based surface layer, and the S content.

About the sample produced as shown in Table 3, the insulating layer made of the glass epoxy resin of FR / ANSI grade in the portion where the Sn-based surface layer is removed and the Cu-Sn intermetallic compound layer is exposed Was formed with a thickness of 0.2 mm by hot pressing.
Then, the contact resistance, the dynamic friction coefficient, and the solder heat resistance after 105 ° C. × 1000 hours are measured for the connector portion that is in the Sn-based surface layer state, and the insulating layer is formed on the circuit board portion on which the insulating layer is formed. The peel strength was measured.
The contact resistance was measured under the condition of sliding with a load of 0.49 N (50 gf) using an electrical contact simulator manufactured by Yamazaki Seiki Co., Ltd. after leaving the sample at 105 ° C. for 1000 hours.

As for the dynamic friction coefficient, a plate-shaped male test piece and a hemispherical female test piece having an inner diameter of 1.5 mm are prepared with each sample so as to simulate the contact portion of the male terminal and female terminal of the fitting type connector. Then, using a horizontal load measuring device (Model-2152NRE) manufactured by Aiko Engineering Co., Ltd., the frictional force between the two test pieces was measured to obtain the dynamic friction coefficient. Referring to FIG. 4, a male test piece 32 is fixed on a horizontal base 31, a hemispherical convex surface of a female test piece 33 is placed on the male test piece 33, and the plating surfaces are brought into contact with each other. The load P of 9N (500 gf) is applied and the male test piece 32 is pressed. With the load P applied, the frictional force F when the male test piece 32 was pulled 10 mm in the horizontal direction indicated by the arrow at a sliding speed of 80 mm / min was measured by the load cell 35. A dynamic friction coefficient (= Fav / P) was obtained from the average value Fav of the friction force F and the load P.
The peel strength was difficult to measure with a 0.25 mm copper plate. Therefore, Sn plating was performed on a 35 μm TC copper foil under the same conditions, followed by a reflow treatment, and then measured according to JIS C 6481.
The solder heat resistance was measured in accordance with the provisions of the normal measurement method of JIS C 6481. The case where the circuit board portion on which the insulating layer was formed was swollen or peeled was evaluated as x, and the case where it did not occur was rated as ○.
These results are shown in Table 4.

  As is apparent from Table 4, the metal plate of this example has a small contact resistance at high temperatures and a small coefficient of dynamic friction with respect to the connector portion, and the insertion / extraction force when using the connector is small and good. It can be judged that the heat resistance is also excellent. Further, in the circuit board portion, the insulating layer is firmly bonded, and it can be determined that the bonding reliability is high so that no peeling or the like occurs.

In addition, with respect to the migration resistance of the insulating layer, an applied voltage of DC 50 V is applied between the metal plate sandwiching the insulating layer and the outer copper foil under the conditions in accordance with the provisions of JPCA-ET04-2007, and the insulation after 1000 hours has passed. The resistance value was measured.
As an example sample, a sample manufactured under the conditions of samples 1 to 6 in Table 3 was selected, and as a comparative example, a sample obtained by applying a blackening treatment as a conventional technique as a roughening treatment of a metal plate was used. A sample having an insulation resistance value of 1 MΩ or less was evaluated as x.

  As is apparent from Table 5, in the comparative example by the blackening treatment, the insulation resistance was lowered and became defective, but the example was not defective. This is presumably because Cu is roughened as an oxide in the blackening treatment, and therefore when Cu is humidified, the Cu oxide is easily ionized to cause insulation deterioration. On the other hand, in the Cu—Sn intermetallic compound layer of the example, Sn of the alloy component is passivated, so that metal ions are difficult to elute, and therefore the insulation resistance value is maintained without lowering. .

In addition, in the conductive member of one embodiment, the surface of the Cu base material is subjected to Cu plating and Sn plating, and reflow treatment is performed, so that a Cu-Sn intermetallic layer is formed between the Cu base material and the Sn base surface layer. Although a compound layer was formed, a Ni-Sn intermetallic compound layer was formed between the Cu-based substrate and the Sn-based surface layer by applying Ni plating and Sn plating to the surface of the Cu-based substrate and performing a reflow treatment. You may make it do. In this case, the Ni-Sn intermetallic compound layer having the same surface roughness as that of the Cu-Sn intermetallic compound layer is obtained as the metal plate by removing the Sn-based surface layer in the region to be the circuit board portion. Since it is exposed, an insulating layer may be bonded to the Ni—Sn intermetallic compound layer.
Further, in the embodiment, the aromatic brightener containing S is added to the Sn plating bath, but may be added to the Cu plating bath.

DESCRIPTION OF SYMBOLS 1 Metal core board | substrate 2 Circuit board part 3 Connector part 4 Metal plate 5 Insulation layer 6 Circuit conductor 7 Electronic component 11 Conductive member 12 Cu-type base material 13 Cu-Sn intermetallic compound layer 14 Sn-type surface layer 15 Cu ₃ Sn layer 16 Cu ₆ Sn ₅ layer 21 Cu plating layer 22 Sn plating layer 23 Mask

Claims (5)

  An intermetallic compound having a Cu-based substrate, a Sn-based surface layer formed on the surface, and a Cu-Sn intermetallic compound or a Ni-Sn intermetallic compound between the Sn-based surface layer and the Cu-based substrate. A conductive member in which a compound layer is formed, and the surface roughness of the surface of the intermetallic compound layer in contact with the Sn-based surface layer is an arithmetic average roughness Ra of 0.05 to 0.35 μm, and A conductive member for a metal plate of a metal core substrate, wherein the ten-point average roughness Rz is 0.5 to 3.0 μm.   The metal plate for a metal core substrate, wherein a part of the Sn-based surface layer in the conductive member for a metal plate according to claim 1 is removed, and a surface of the intermetallic compound layer is exposed.   The metal core board | substrate characterized by the exposed part of the said intermetallic compound layer being covered with the insulating layer in the metal plate for core metal boards | substrates of Claim 2.   The surface of the Cu-based substrate is plated with either Ni or Ni alloy, Cu or Cu alloy, and Sn or Sn alloy is plated thereon to form each plating layer, and then heated and reflowed. A process for producing a conductive member in which an intermetallic compound layer having a Ni-Sn intermetallic compound or a Cu-Sn intermetallic compound is formed between the Cu-based substrate and the outermost Sn-based surface layer; And a step of removing a part of the Sn-based surface layer in the conductive member to expose the surface of the intermetallic compound layer. A method for producing a metal plate for a metal core substrate. A method for producing a metal core substrate, comprising: producing a metal plate by the production method according to claim 4 and forming an insulating layer on the exposed intermetallic compound layer.

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