JPS6214490A - Substrate for pga - Google Patents

Substrate for pga

Info

Publication number
JPS6214490A
JPS6214490A JP15329085A JP15329085A JPS6214490A JP S6214490 A JPS6214490 A JP S6214490A JP 15329085 A JP15329085 A JP 15329085A JP 15329085 A JP15329085 A JP 15329085A JP S6214490 A JPS6214490 A JP S6214490A
Authority
JP
Japan
Prior art keywords
substrate
copper
pga
lead pin
heat dissipation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15329085A
Other languages
Japanese (ja)
Inventor
飯塚 富雄
松山 圭宏
三宅 保彦
護 御田
佐原 邦造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Hitachi Ltd
Original Assignee
Hitachi Cable Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd, Hitachi Ltd filed Critical Hitachi Cable Ltd
Priority to JP15329085A priority Critical patent/JPS6214490A/en
Publication of JPS6214490A publication Critical patent/JPS6214490A/en
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)
  • Laminated Bodies (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は高集積度素子のパッケージング材料として用い
られるPGA (ピン・グリッド・アレイ)用基板に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PGA (pin grid array) substrate used as a packaging material for highly integrated devices.

[従来の技術と問題点] 現在、高集積度の回路素子を直接マウン1〜塔載できる
基板材料にはガラスエポキシ、ポリイミド等の有機材料
とセラミック材料とがある。これらの材料は電気絶縁性
に優れ、かつ量産性があるため、PGA用基板、多層配
線基板、ハイブリッドIC基板等に多用されてきた。し
かし、最近ICの高集積化がさらに進み、また一つの基
板上に複数個の素子を搭載するマルチチップ型IC等の
計画もあり、従来これらの材料では十分にICの信頼性
を確保できない状況となった。
[Prior Art and Problems] Currently, substrate materials on which highly integrated circuit elements can be directly mounted include organic materials such as glass epoxy and polyimide, and ceramic materials. These materials have excellent electrical insulation properties and can be mass-produced, so they have been widely used for PGA substrates, multilayer wiring boards, hybrid IC substrates, and the like. However, recently, ICs have become more highly integrated, and there are also plans for multi-chip ICs that mount multiple elements on a single substrate, making it difficult to ensure sufficient IC reliability using conventional materials. It became.

高集積度素子を塔載する基板には三つの重要な要件が必
要であり、それは(1)高熱放散性、(2)熱膨張係数
の整合性、(3)高周波特性である。このうち特に高熱
放散性と熱膨張係数の整合性は信頼性の確保に関係する
重要な要件であるが、前記従来の材料はデバイス設計名
の要求を完全に満たしjqない。それは搭載素子の発熱
量がデバイスの熱放散速度よりも大きいためにデバイス
内部の温麿が上昇し、シリコン素子と基板材料の熱膨張
係数の差による歪応力がシリコン素子に付加されるため
でおる。
There are three important requirements for a substrate on which highly integrated devices are mounted: (1) high heat dissipation, (2) matching of thermal expansion coefficients, and (3) high frequency characteristics. Among these, high heat dissipation and consistency of thermal expansion coefficients are particularly important requirements related to ensuring reliability, but the conventional materials described above do not completely satisfy the requirements of device design names. This is because the amount of heat generated by the mounted elements is greater than the heat dissipation rate of the device, which increases the temperature inside the device, and strain stress is added to the silicon element due to the difference in thermal expansion coefficient between the silicon element and the substrate material. .

このような高集積良化、高密度実装化の方向に対応して
、最近基板材料への金属の応用が注目されている。これ
は金属本来の高い熱放散りを利用しようとするものでお
るが、この場合電気絶縁処理が最大の難点となっている
。また熱膨張係数も問題となっており、熱膨張係数の完
全整合にはモリブデン、タングステン等の高価な材料を
使用する必要があるが、これらは熱放散性がそれ程良く
ない。81に各種基板材料の1h性を総括し一〇示り゛
In response to the trend towards higher integration and higher density packaging, the application of metals to substrate materials has recently attracted attention. This attempts to take advantage of the inherent high heat dissipation of metals, but the biggest difficulty in this case is electrical insulation. Coefficient of thermal expansion is also a problem, and perfect matching of coefficients of thermal expansion requires the use of expensive materials such as molybdenum and tungsten, which do not have very good heat dissipation properties. 81 summarizes the 1h properties of various substrate materials.

なお上記表中テフロンはデュポン社(米国)の商品名で
、四ふつ化エチレン系樹脂の代表的なものであるが、基
板材料として用いられた例はなく、参考として示したも
のである。
Note that Teflon in the above table is a trade name of DuPont (USA) and is a typical tetrafluoroethylene resin, but there are no examples of it being used as a substrate material, and it is shown for reference only.

発明者等は金属基板材料のうち、特にCl0(銅/イン
バー/銅クラッド材)に着眼した。理由はCICの三層
v4造の比率を変えられる、いわゆる熱放散設計が可能
なことと、さらに熱放散性の高い銅の性質を利用できる
ためである。CICを基板材料として使用する案はすで
にあるが、この材料を利用する場合絶縁処理の方法と、
三層崩造のクラッド祠の切断面も含む表面処理等が問題
となり、未だ完全な実用化には至っていない。
Among metal substrate materials, the inventors particularly focused on Cl0 (copper/invar/copper clad material). The reason is that it is possible to change the ratio of CIC's three-layer V4 structure, which is a so-called heat dissipation design, and it is also possible to utilize the properties of copper, which has high heat dissipation properties. There is already a plan to use CIC as a substrate material, but when using this material, there are issues with insulation treatment methods,
There are problems with surface treatment, including the cut surfaces of the three-layer collapsed clad shrine, and it has not yet been fully put into practical use.

[発明の目的] 本発明の目的は、上記事情に鑑みCICに特別な表面処
理及び絶縁処理を施すことにより(qられる高信頼性の
高集積度、高密度実装用PGA用基板基板供することに
ある。
[Object of the Invention] In view of the above-mentioned circumstances, the object of the present invention is to provide a highly reliable, highly integrated, and high-density mounting PGA substrate by subjecting CIC to special surface treatment and insulation treatment. be.

[発明の概要] すなわら本発明は、リードピン挿入孔を有する銅/イン
バー/銅クラッド材からなる基板の表面を粗化めっきし
、この粗化めつき面上に基板の熱放散部を除いて四ふつ
エチレン系樹脂のコーティングを施し、この樹脂コーテ
ィング上に銅箔により所望の回路パターンを形成し、こ
の回路パターン上に電極数出品を設け、この電極数出品
から前記挿入口にリードピンを挿入して構成されたもの
で、粗化めっぎ面上に誘電率の小さい四ふっ化エチレン
系樹脂を密着コーティングすることにより高信頼性のP
GA用基板基板qようとするものである。
[Summary of the Invention] In other words, the present invention roughens the surface of a substrate made of copper/invar/copper cladding material having lead pin insertion holes, and coats the surface of the substrate on this roughened plating surface except for the heat dissipating portion of the substrate. Then, apply a coating of ethylene resin to the resin coating, form a desired circuit pattern with copper foil on this resin coating, provide a number of electrodes on this circuit pattern, and insert a lead pin from this number of electrodes into the insertion hole. It is constructed by coating a polytetrafluoroethylene resin with a low dielectric constant on the roughened plating surface to achieve high reliability.
This is a substrate for GA.

本発明において絶縁処理材料として四ふっ化エチレン系
樹脂を用いた理由は、その誘電率にある。
The reason why tetrafluoroethylene resin is used as the insulation treatment material in the present invention is its dielectric constant.

ICの方向は高集積度化に加えて高速化する傾向におり
、基板の絶縁材料の誘電率がこの高速化に直接関係する
In addition to higher integration, the trend in ICs is toward higher speeds, and the dielectric constant of the insulating material of the substrate is directly related to this higher speed.

一般に高周波信号の遅延時間は次の式で表わされる。Generally, the delay time of a high frequency signal is expressed by the following formula.

To −12Co Zo =1−2 za=J’E丁’CO’7(K/fi下)d/ωTo 
:遅延時間、1:配線長さ、CO:容量、Zo :イン
ピーダンス、Lo :インダクタンス、εr:誘電率、
ω:配線幅、d:絶縁層厚さ。
To −12Co Zo =1-2 za=J'E ding'CO'7 (K/fi lower) d/ωTo
: delay time, 1: wiring length, CO: capacitance, Zo: impedance, Lo: inductance, εr: dielectric constant,
ω: wiring width, d: insulation layer thickness.

このため絶縁材料には誘電率が小さいことが要求される
が、本発明においては有機材料の中でも誘電率の小さい
四ふつ化エチレン系樹脂例えばテフロンを選定したもの
である。テフロンは表1に示すように熱伝導率が低いが
、熱放散についてはCICで達成される。テフロンは正
式には四ふつ化エチレンー六ふつ化プロピレン共重合体
であるか、このほか有望な四ふつ化エチレン樹脂として
は四ふつ化エチレンアルキルビニルエーテル共重合体、
エチレン−四ぶつ化エチレン共重合体などがあげられる
For this reason, the insulating material is required to have a low dielectric constant, and in the present invention, a tetrafluoroethylene resin such as Teflon, which has a low dielectric constant among organic materials, is selected. Although Teflon has low thermal conductivity as shown in Table 1, heat dissipation is achieved by CIC. Teflon is officially a tetrafluoroethylene-hexafluoropropylene copolymer, or other promising tetrafluoroethylene resins include tetrafluoroethylene alkyl vinyl ether copolymer,
Examples include ethylene-tetrabutylene copolymer.

[実施例] 次に添付図面により本発明PG△用具板の実施例を説明
する。
[Example] Next, an example of the PG△ tool plate of the present invention will be described with reference to the accompanying drawings.

実施例1 第1図にPGA用基板基板面を示ず。1が銅/インバー
/銅クラッド材からなる基板であり、2が銅、3がイン
バーでおる。4が基板1を貫通ずべく設けられたリード
ピン挿入口である。基板1の銅、インバー、・銅の厚さ
の比率は18:1であり、厚さは全体で1.0#である
Example 1 The surface of a PGA substrate is not shown in FIG. 1 is a substrate made of copper/invar/copper clad material, 2 is copper, and 3 is invar. 4 is a lead pin insertion hole provided to penetrate the substrate 1. The thickness ratio of copper, invar, and copper in the substrate 1 is 18:1, and the total thickness is 1.0#.

本実施例においては、後述するテフロンコーティング6
の密着性を高めるため、基板1の表面全体に青化銅無光
沢浴による粗化電気銅めっき5を施した。銅めつき5は
リードピン挿入口4の内部まで施し、挿入口4の内部に
おいてもテフロンコーティング6の密着性を高めるよう
にした。基板1の周辺部はテフロンコーティング6が1
#Aされないため銅めっぎ5が露出するが、これは防錆
が目的である。銅めつぎ5の粗度はテフロンとの密着性
の点から表面平均粗さで0.5〜3μの範囲が好ましく
、銅めつぎの厚さはcrcm板1の端面の腐食を防止す
る意味から最低2μ以上は必要でおる。
In this example, the Teflon coating 6 described later is used.
In order to improve the adhesion, the entire surface of the substrate 1 was subjected to roughening electrolytic copper plating 5 using a copper cyanide matte bath. The copper plating 5 is applied to the inside of the lead pin insertion opening 4 to improve the adhesion of the Teflon coating 6 even inside the insertion opening 4. The periphery of the substrate 1 is coated with Teflon coating 6.
#A is not applied, so the copper plating 5 is exposed, but this is for the purpose of rust prevention. The roughness of the copper peg 5 is preferably in the range of 0.5 to 3μ in average surface roughness from the viewpoint of adhesion with Teflon, and the thickness of the copper pew is determined from the viewpoint of preventing corrosion of the end face of the CRC plate 1. At least 2μ or more is required.

銅めつき5後、CIC基板1の外周部すなわら熱放散部
7を一部残してテフロンコーティング6を施すことによ
り絶縁処理する。テフロンコーティング6の方法は溶融
テープ貼付法、溶射法、モールド法等を試みたが、いず
れの方法でも挿入口4内面までテフロンを流し込む(穴
埋めする)ことができるが、素子搭載部8および熱放散
部7はコーティングしないためモールド法が最も適して
いる。
After the copper plating 5, insulation treatment is performed by applying a Teflon coating 6 to a portion of the outer peripheral portion of the CIC substrate 1, that is, the heat dissipating portion 7, with a portion remaining. Methods for Teflon coating 6 have been tried, such as fusion tape application, thermal spraying, and molding, but all of these methods allow Teflon to be poured (fill holes) up to the inner surface of the insertion port 4, but there is a problem with the element mounting area 8 and heat dissipation. Since part 7 is not coated, the molding method is most suitable.

次にテフロンコーディング6された基板1上に所定位置
に銅張テフロンシート9を貼付け、このシー1〜9の銅
i(3S 10においてフォトエツチング法により所望
の回路パターンを形成する。そしてこの回路パターン上
に電極取出部11を設け、この電極取出部11から基板
1のリードピン挿入口4にリードピン12を挿入するた
め、上記テフロンコーディングにより穴埋めされたリー
ドピン挿入LI4を再び精密ドリルまたは打扱加1−に
より穴明けする。挿入1」4はリードピン12の直径よ
り幾分小さい孔とし、自動ピン打込み装置によりここに
リードピン12を圧入する。
Next, a copper-clad Teflon sheet 9 is pasted at a predetermined position on the Teflon-coated substrate 1, and a desired circuit pattern is formed by photoetching the copper sheets 1 to 9 (3S 10). An electrode extraction part 11 is provided on the top, and in order to insert the lead pin 12 from this electrode extraction part 11 into the lead pin insertion hole 4 of the board 1, the lead pin insertion LI4, which has been filled with the Teflon coating, is again drilled with a precision drill or hammered. The insertion hole 1"4 is made into a hole somewhat smaller than the diameter of the lead pin 12, and the lead pin 12 is press-fitted therein by an automatic pin driving device.

ピン圧入掛はリードピン12と銅箔V10の回路パター
ンとの電気的な接触を完全にするため、ピン脚部を溶融
半田槽に浸漬し、半ITl接続加二[を施す。この方法
によれば、半田はり一ドピン12と挿入口4壁間を吸い
上がり、上部の銅箔糸10の回路パターンとリードピン
12との電気的接続を確実にする。最終的にはピン全体
に半田層13が形成されるはか、ピン頭部14の周囲に
半田接t*層15が形成される。
For pin press-fitting, in order to make complete electrical contact between the lead pin 12 and the circuit pattern of the copper foil V10, the pin leg is immersed in a molten solder bath and a semi-ITl connection is applied. According to this method, the solder is sucked up between the lead pin 12 and the wall of the insertion opening 4, thereby ensuring electrical connection between the circuit pattern of the upper copper foil thread 10 and the lead pin 12. Eventually, not only the solder layer 13 is formed over the entire pin, but also the solder contact t* layer 15 is formed around the pin head 14.

以上によりPGA用基板は完成するが、この基板上に例
えばシリコン素子16をマウントする場合には、銅めつ
き5上において金−シリコン共晶接合により接合する方
法が一般的なため、銅めっき5上にニッケルめっき17
を約3μ、金めつぎ18を約4μ施すかまたは金箔を介
して索子16を金−シリコン共晶接合する。そしてワイ
ヤボンディング19を行ない、封止枠(コバール製)2
0をロウ付すし蓋(コバール製)21で完全封止してP
GAを完成させた。
The PGA substrate is completed as described above, but when mounting, for example, a silicon element 16 on this substrate, the common method of bonding is gold-silicon eutectic bonding on the copper plating 5. Nickel plating on top 17
3μ and about 4μ of gold pegs 18, or gold-silicon eutectic bonding is applied to the cord 16 via gold foil. Then, wire bonding 19 is performed, and the sealing frame (made by Kovar) 2
0 completely sealed with a brazed sushi lid (manufactured by Kovar) 21 and P
Completed GA.

このPGAの外観を第2図に示す。このPGAによれば
CIC基板1の外周部が熱放散部7となっているため、
封止素子の信頼性を茗しく向上させることができる。ま
たCICLj板1はシリコンとの熱膨張係数を整合さひ
るため、厚さ0.8Mのインバーの両面に厚さ0.1m
の無酸素銅をそれぞれクラッドしたものを用いた。すで
に述べたように基板1の熱膨張係数はインバーの体積比
によつ−(任意に設定づることができる。第3図はその
CIC基板1にお[)るインバ一体積比と熱膨張係数の
関係を示したもので必る。
Figure 2 shows the appearance of this PGA. According to this PGA, the outer periphery of the CIC board 1 serves as the heat dissipation section 7;
The reliability of the sealing element can be significantly improved. In addition, in order to match the coefficient of thermal expansion with silicon, the CICLj board 1 is coated with a 0.1 m thick invar on both sides of a 0.8 m thick invar.
clad with oxygen-free copper was used. As already mentioned, the thermal expansion coefficient of the substrate 1 depends on the volume ratio of Invar (which can be set arbitrarily). It must show the relationship between

実施例2 実施例1において表面粗化銅めつき5の替わりに表面粗
化ニッケルめっきを施した。これによれば基板コの外周
熱放散部7がニッケルの耐誘性により変色しにくくなる
ほか、シリコン素子16を接合するに必たつ−Cのニッ
ケルめっき17を省略することができる。
Example 2 In Example 1, surface roughening nickel plating was applied instead of surface roughening copper plating 5. According to this, the outer circumferential heat dissipating portion 7 of the substrate is not easily discolored due to the induction resistance of nickel, and the -C nickel plating 17 necessary for bonding the silicon element 16 can be omitted.

[発明の効果] (1)上記実施例1にもとづいて試作したPGAを、E
IJA規格IC−121熱衝撃試験及び[IJA規格I
C−121温磨サイクル試験によりそれぞれ試験をし、
従来型ガラスエポキシ製PGAとの信頼性の比較を行な
った。その試験結果を表2に示す。
[Effects of the invention] (1) The PGA prototyped based on the above Example 1 was
IJA Standard IC-121 Thermal Shock Test and [IJA Standard I
Each was tested using the C-121 warm polishing cycle test,
Reliability was compared with a conventional glass epoxy PGA. The test results are shown in Table 2.

表2によれば、本実施例にもとづ<PGAの素子ダメー
ジ発生率が非常に小さく、基板の信頼性の高いことが分
かる。これにはテフロンコーティングの密着強度と共に
してCI i板の熱膨張係数が関係している。
According to Table 2, it can be seen that based on this example, the element damage occurrence rate of PGA was very small, and the reliability of the substrate was high. This is related to the adhesion strength of the Teflon coating as well as the coefficient of thermal expansion of the CI i plate.

(2)従来のレラミック製基板は穴明は加工が非常に困
難なため未焼結シート(グリーンシート)に穴明は加工
をしてから焼結して製造しているが、焼結時の収縮によ
り完成品の寸法精度が出ない等の問題があるが、本実施
例のCIC基板はこの点穴明は加工が非常に容易であり
、量産性に優れている。
(2) Conventional Relamic substrates are manufactured by drilling holes in an unsintered sheet (green sheet) and then sintering it, as it is extremely difficult to process holes. Although there is a problem in that the dimensional accuracy of the finished product is not achieved due to shrinkage, the CIC board of this embodiment is very easy to process with the point holes, and is excellent in mass production.

(3)すでに述べたように本実施例の基板は熱放散性に
優れているため、高集積度の素子付けが可能である。こ
の魚節2図に示すPGAの素子部の温麿上昇率=熱抵抗
Rth(’C/W>を、熱放散部7の長さaを変えて出
力20Wのシリコン素子をマウントし20Wの電力を付
加した時の温度を実測して求めた。この結果を第4図に
示す。これから明らかなように本実施例の場合基板の熱
抵抗が非常に小さく熱放散性が数(8高いため、同一の
信頼性のもとて素子の集積度を高く取ることができ、ま
た高い印加電圧を付与できるため高速化を達成できる。
(3) As already mentioned, the substrate of this embodiment has excellent heat dissipation properties, so it is possible to attach highly integrated elements. The temperature increase rate = thermal resistance Rth ('C/W) of the PGA element shown in Fig. 2 is calculated by changing the length a of the heat dissipation part 7 and mounting a silicon element with an output of 20 W. Figure 4 shows the results.As is clear from this, in this example, the thermal resistance of the substrate is very small and the heat dissipation is high by several (8). The device can be highly integrated with the same reliability, and a high applied voltage can be applied, so high speeds can be achieved.

以上のように本発明の基板によれば、PGAの信頼性を
向上することができると共に基板の製作加工が容易であ
り、又熱放散性に優れているため素子の高集積化、高速
化が可能であるという顕著な効果を有する。
As described above, according to the substrate of the present invention, it is possible to improve the reliability of the PGA, the manufacturing process of the substrate is easy, and because it has excellent heat dissipation properties, it is possible to increase the integration and speed of elements. It has the remarkable effect of being possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明PGA用基板の一実施例説明図、第2図
は前記実施例に係るPGAの外観説明図、第3図はCI
C基板におけるインバ一体積比と熱膨張係数の関係を示
す特性図、第4図は第2図に示されたPGAの熱放散部
の長さと素子部の温度上昇率との関係を示ず特性図であ
る。 1 :CIC基板、 2:銅、 3:インバー、 4:リードピン挿入口、 5:銅めつき、 6:テフロンコーティング、 7:熱放散部、 8:素子搭載部、 9:銅張テフロンシー1〜. 10:銅箔層、 11:電極取出部、 12:リードピン、 13:半田層、 14:ピン頭部、 15:半田接続層、 16、シリコン素子、 17:ニッケルめっき、 18:金めつき、 19:ワイヤボンディング、 20:封止枠、 21:M。 代理人  弁理士  佐 藤 不二雄 6: テア0〉ツーティ)り゛
FIG. 1 is an explanatory diagram of one embodiment of the PGA substrate of the present invention, FIG. 2 is an explanatory diagram of the external appearance of the PGA according to the embodiment, and FIG. 3 is a CI
A characteristic diagram showing the relationship between the Invar volume ratio and the coefficient of thermal expansion in the C substrate. Figure 4 shows the relationship between the length of the heat dissipation part of the PGA shown in Figure 2 and the temperature rise rate of the element part. It is a diagram. 1: CIC board, 2: Copper, 3: Invar, 4: Lead pin insertion port, 5: Copper plating, 6: Teflon coating, 7: Heat dissipation section, 8: Element mounting section, 9: Copper-clad Teflon seam 1~ .. 10: Copper foil layer, 11: Electrode extraction part, 12: Lead pin, 13: Solder layer, 14: Pin head, 15: Solder connection layer, 16, Silicon element, 17: Nickel plating, 18: Gold plating, 19 : Wire bonding, 20: Sealing frame, 21: M. Agent: Patent Attorney Fujio Sato 6: Thea

Claims (2)

【特許請求の範囲】[Claims] (1)リードピン挿入孔を有する銅/インバー/銅クラ
ッド材からなる基板の表面を粗化めっきし、この粗化め
っき面上に基板の熱放散部を除いて四ふっ化エチレン系
樹脂のコーティングを施し、この樹脂コーティング上に
銅箔により所望の回路パターンを形成し、この回路パタ
ーン上に電極取出部を設け、この電極取出部から前記挿
入孔にリードピンを挿入して構成されたことを特徴とす
るPGA用基板。
(1) The surface of a board made of copper/invar/copper clad material with lead pin insertion holes is rough plated, and a coating of tetrafluoroethylene resin is applied to the rough plated surface except for the heat dissipating parts of the board. A desired circuit pattern is formed using copper foil on the resin coating, an electrode extraction portion is provided on the circuit pattern, and a lead pin is inserted into the insertion hole from the electrode extraction portion. PGA board.
(2)表面平均粗さ0.5〜3μの銅めっき又はニッケ
ルめつきにより粗化めつきして構成されたことを特徴と
する特許請求の範囲第1項記載のPGA用基板。
(2) The PGA substrate according to claim 1, characterized in that the substrate is roughened by copper plating or nickel plating with a surface average roughness of 0.5 to 3 μm.
JP15329085A 1985-07-11 1985-07-11 Substrate for pga Pending JPS6214490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15329085A JPS6214490A (en) 1985-07-11 1985-07-11 Substrate for pga

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15329085A JPS6214490A (en) 1985-07-11 1985-07-11 Substrate for pga

Publications (1)

Publication Number Publication Date
JPS6214490A true JPS6214490A (en) 1987-01-23

Family

ID=15559241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15329085A Pending JPS6214490A (en) 1985-07-11 1985-07-11 Substrate for pga

Country Status (1)

Country Link
JP (1) JPS6214490A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6465895A (en) * 1987-09-07 1989-03-13 Hitachi Cable Mesh-shaped metal core substrate
JPS6473695A (en) * 1987-09-14 1989-03-17 Mitsubishi Plastics Ind Substrate for printed-circuit board
JPH01256157A (en) * 1988-04-06 1989-10-12 Denki Kagaku Kogyo Kk Compound pin grid array
JPH04309289A (en) * 1991-02-06 1992-10-30 Internatl Business Mach Corp <Ibm> Electrolytic method for etchback of sealed copper-invar-copper structure
JPH05191042A (en) * 1991-07-17 1993-07-30 Internatl Business Mach Corp <Ibm> Manufacture of layer of multilayer electronic circuit package and manufacture of multilayer electronic circuit package
JP2010245098A (en) * 2009-04-01 2010-10-28 Mitsubishi Shindoh Co Ltd Metal core substrate, conductive member for metal plate, and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136569A (en) * 1974-09-21 1976-03-27 Mitsubishi Electric Corp Konseishusekikairo no seizohoho
JPS58147189A (en) * 1982-02-26 1983-09-01 富士通株式会社 Circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5136569A (en) * 1974-09-21 1976-03-27 Mitsubishi Electric Corp Konseishusekikairo no seizohoho
JPS58147189A (en) * 1982-02-26 1983-09-01 富士通株式会社 Circuit board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6465895A (en) * 1987-09-07 1989-03-13 Hitachi Cable Mesh-shaped metal core substrate
JPS6473695A (en) * 1987-09-14 1989-03-17 Mitsubishi Plastics Ind Substrate for printed-circuit board
JPH01256157A (en) * 1988-04-06 1989-10-12 Denki Kagaku Kogyo Kk Compound pin grid array
JPH04309289A (en) * 1991-02-06 1992-10-30 Internatl Business Mach Corp <Ibm> Electrolytic method for etchback of sealed copper-invar-copper structure
JPH05191042A (en) * 1991-07-17 1993-07-30 Internatl Business Mach Corp <Ibm> Manufacture of layer of multilayer electronic circuit package and manufacture of multilayer electronic circuit package
JP2010245098A (en) * 2009-04-01 2010-10-28 Mitsubishi Shindoh Co Ltd Metal core substrate, conductive member for metal plate, and manufacturing method thereof

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