JPS58147189A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPS58147189A
JPS58147189A JP57030018A JP3001882A JPS58147189A JP S58147189 A JPS58147189 A JP S58147189A JP 57030018 A JP57030018 A JP 57030018A JP 3001882 A JP3001882 A JP 3001882A JP S58147189 A JPS58147189 A JP S58147189A
Authority
JP
Japan
Prior art keywords
circuit board
layer
fluoroethylene
circuit
circuit pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57030018A
Other languages
Japanese (ja)
Inventor
貴志男 横内
一典 山中
亀原 伸男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57030018A priority Critical patent/JPS58147189A/en
Publication of JPS58147189A publication Critical patent/JPS58147189A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (U 発明の技術分野 本発明は低温で動作させるジ冒セフソン素子勢を1!!
装するための回路基板に関する。
[Detailed Description of the Invention] (U Technical Field of the Invention The present invention provides a first infrared Sefson device that operates at low temperatures!!
The present invention relates to a circuit board for mounting.

(2)6発明の背景 従来電子計算機部に用いられる回路基板は、通例常温乃
至これに比較的近い温度で用いられている。そして、回
路基INK搭載される素子の動作速度の高速化と整合さ
せるべく回路基板に低誘電率のもo−is採用されてい
る。
(2) 6 Background of the Invention Conventionally, circuit boards used in electronic computer units are usually used at room temperature or a temperature relatively close to this temperature. In order to match the increased operating speed of elements mounted on the circuit board INK, O-IS with a low dielectric constant is adopted for the circuit board.

そして、このような1隆基板に搭載される素子として、
ジ冒セフノン素子等を用い、その回路基板を極低温濃境
円に置き、上記素子を動作させ良場合、この回路基板は
常温では殆んど間11EKする必要性のなかった熱収縮
が解決しなければならない技術的IIQとして大きく浮
び上がって来ている。
And, as an element mounted on such a single board,
If the circuit board is placed in an extremely low-temperature concentration circle using a dithering element, etc., and the above-mentioned element is operated successfully, the circuit board will be free from heat shrinkage, which does not need to be heated to 11EK for almost no time at room temperature. It is emerging as an indispensable technical IIQ.

(3)、従来技術と間融 即ち、従来回路基板の材料として一般に用いられている
ものは、エポキシ樹脂、セラミック(アルミナ)、ガラ
ス轡である。これらの材料はこれを用いた回路基板をジ
ョセフソン素子等を動作させる極低温にすると、その温
度では熱収縮が1〜2’lにもなり、基板のひソ割れ、
基板と回路パターンとの剥離が生じ、回路基板に形成さ
れている電気(ロ)路の機能を著しく阻害するか、その
機能に壊滅的な打撃を与える。また、回路基板自体には
接地手段はない、更に杜、上述材料の誘電率は、例えば
エポキシ樹脂にあって社誘電率が4乃至5、アルミナに
あっては誘電率が6乃至7と高く、信号の伝播に遅延を
与え、上述し九素子の高速性とよく整合し得なくなって
いる。
(3) Prior art and fusion: The materials commonly used for conventional circuit boards are epoxy resin, ceramic (alumina), and glass. When a circuit board using these materials is heated to the extremely low temperature used to operate a Josephson device, the heat shrinkage reaches 1 to 2'L at that temperature, causing cracks in the board,
Peeling occurs between the circuit board and the circuit pattern, which significantly impedes the function of the electrical path formed on the circuit board or gives a catastrophic blow to the function. Furthermore, the circuit board itself has no grounding means, and the dielectric constants of the above-mentioned materials are as high as, for example, epoxy resin, which has a dielectric constant of 4 to 5, and alumina, which has a dielectric constant of 6 to 7. This gives a delay to signal propagation, making it impossible to match well with the high-speed performance of the nine elements described above.

(4)9発明の目的 本発明は上述したような従来回路基板の有する欠点に鑑
みて創案されたもので、その目的は極低−Ktかれても
熱収縮から惹起せしめられる問題は生ぜず、信号伝播性
の向上4b図れ、又それ自体に接地手段も儒えている回
路基板を提供することにある。
(4) 9 Purpose of the Invention The present invention was devised in view of the above-mentioned drawbacks of conventional circuit boards, and its purpose is to avoid problems caused by thermal shrinkage even if the Kt is extremely low. It is an object of the present invention to provide a circuit board which has improved signal propagation properties and also has a grounding means.

(5)0発明の構成 そして、この目的は11面を多孔質化処理したアル2ニ
ウム板上に厚さ0.5 W以下の4−フッ化エチレン層
を形成し、皺4−フッ化エチレン層上に回路パターンを
形成することKよって達成される。
(5) 0 Structure of the invention And this purpose is to form a 4-fluoroethylene layer with a thickness of 0.5 W or less on an aluminum plate whose 11 sides have been made porous, and to form a layer of wrinkled 4-fluoroethylene. This is accomplished by forming a circuit pattern on the layer.

(6)0発明の実施例 以下、添付図面を参照して本発明の詳細な説明する。(6) Example of 0 invention Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

添付図面は本発明のll!麹例を示す。図において、1
はアルミニウム板で、その多孔質表面2に樹脂層(絶縁
層)、例えば犀さ0.5m以下になるように4−フッ化
エチレン層3が塗布されて本発明の回路基板4−が形成
されている。金属板1の熱収縮性は樹脂層3の熱収縮性
と近位されている。例えは、4−フッ化エチレンの30
0Kから4Ktでの熱収縮は2畳であり、アル(ニウム
の熱収縮は他の金属より大きく上記温度間Sにおいて0
.5鳴である。
The attached drawings illustrate the present invention! An example of koji is shown. In the figure, 1
is an aluminum plate, and a resin layer (insulating layer), for example, a 4-fluoroethylene layer 3 is applied to the porous surface 2 so that the thickness is 0.5 m or less to form the circuit board 4- of the present invention. ing. The heat shrinkability of the metal plate 1 is similar to that of the resin layer 3. For example, 30 of 4-fluoroethylene
The thermal contraction from 0K to 4Kt is 2 tatami, and the thermal contraction of aluminum is larger than that of other metals.
.. There are 5 sounds.

ソシテ、アルきニウム板1の表面2は陽極酸化により多
孔質に形成され、その多孔質表面2に上述した熱収縮性
を有する4−フッ化エチレン層3が塗布され、比較的に
薄く形成されているから、アルミニウム板1の熱収縮と
4−フッ化エチレン層3の熱収縮とが整合している。従
って、4−フッ化エチレン層3上にジlセフソン素子勢
を含んで回路パターン5が形成され(6は保Sg層(4
−フッ化エチレン)である、)、それを4.2KsI!
I:の極低温で動作させても、基板にひソ割れ、基板と
回路パターンとの剥離を生じさせ、回路機能に重大な悪
影響を及ぼす廁れ蝶々くなる。管た、4−7ツ化工チレ
ン層3をアルミニウム板1の多孔質表面に結合させてい
ることと上述の熱収量lI合性とが相俟って、4−フッ
化エチレン層3の熱収縮の吸収性は更に向上され、上述
の不都合の一層の改曽が果されている。このことは又4
一フツ化エチレン層3自体だけで回路基板を製造したな
ら生ずるであろうそりO発生を防止しうる。
The surface 2 of the aluminum plate 1 is made porous by anodic oxidation, and the above-mentioned 4-fluoroethylene layer 3 having heat shrinkability is applied to the porous surface 2 to form a relatively thin layer. Therefore, the thermal contraction of the aluminum plate 1 and the thermal contraction of the 4-fluoroethylene layer 3 match. Therefore, a circuit pattern 5 is formed on the 4-fluoroethylene layer 3 (6 is a protective Sg layer (4
- ethylene fluoride), which is 4.2KsI!
Even when operated at an extremely low temperature of I:, the board cracks, the board and the circuit pattern separate, and the circuit pattern becomes detached, which has a serious adverse effect on circuit function. In addition, the fact that the 4-7 chemically modified ethylene layer 3 is bonded to the porous surface of the aluminum plate 1 and the above-mentioned heat yield property combine to cause thermal contraction of the 4-7 fluoroethylene layer 3. The absorbency of the material has been further improved, and the above-mentioned disadvantages have been further alleviated. This is also 4
It is possible to prevent the occurrence of warpage that would occur if the circuit board was manufactured using only the monofluoroethylene layer 3 itself.

また、4−フッ化エチレンの双極子モーメントが小さく
、従って誘電率が小さいから、その上に形成される回路
パターン5を経て伝播する信号の伝播速度を高め得るば
かシでなく、信号に与える歪、減衰も緩和しうる。
In addition, since the dipole moment of 4-fluoroethylene is small, and therefore the dielectric constant is small, it is possible to increase the propagation speed of the signal propagating through the circuit pattern 5 formed thereon. , damping can also be alleviated.

そして、回路基1[4のアルミニウム板は接地手段とし
て用いることが出来る。
The aluminum plate of the circuit board 1 [4] can be used as a grounding means.

(7)0発明の効果 以上の説明から明らかなように*発明によれば次の効果
が得られる。
(7) Effects of the Invention As is clear from the above explanation, the invention provides the following effects.

(1)  熱収縮で従来生じてい友回路基板のひずみの
発生を回避し得る。
(1) It is possible to avoid distortion of the circuit board, which conventionally occurs due to thermal contraction.

(2) 回路パターンの曳めの接地手段を(ロ)路基板
自体に設けることが出来る。
(2) Grounding means for tracing the circuit pattern can be provided on the circuit board itself.

(3)  信号の伝播性を向上出来る等である。(3) Signal propagation can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

添付図面は本発明の実施例を示す図である。 図中、lは金属板、2は多孔質表面、3は4−7ツ化工
チレン層、5は回路パターン、6は保賎膜である。 特許出願人 富士通株丈会社
The accompanying drawings illustrate embodiments of the invention. In the figure, l is a metal plate, 2 is a porous surface, 3 is a 4-7 polyethylene layer, 5 is a circuit pattern, and 6 is a protective film. Patent applicant Fujitsu Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 表面を多孔質化処理したアルZニウム板上に犀さ0.5
m以下の4−7フ化工チレン層を形成し、#4−、フッ
化エチレン層上に回路パターンを形成してなることを特
徴とする回路基板。
0.5 cm of rhinoceros on an aluminum plate whose surface has been made porous
A circuit board characterized in that a 4-7 fluorinated ethylene layer having a thickness of 4-7 m or less is formed, and a circuit pattern is formed on the 4-7 fluorinated ethylene layer.
JP57030018A 1982-02-26 1982-02-26 Circuit board Pending JPS58147189A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57030018A JPS58147189A (en) 1982-02-26 1982-02-26 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57030018A JPS58147189A (en) 1982-02-26 1982-02-26 Circuit board

Publications (1)

Publication Number Publication Date
JPS58147189A true JPS58147189A (en) 1983-09-01

Family

ID=12292099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57030018A Pending JPS58147189A (en) 1982-02-26 1982-02-26 Circuit board

Country Status (1)

Country Link
JP (1) JPS58147189A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225750A (en) * 1984-04-24 1985-11-11 株式会社 潤工社 Printed substrate
JPS6214490A (en) * 1985-07-11 1987-01-23 日立電線株式会社 Substrate for pga

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60225750A (en) * 1984-04-24 1985-11-11 株式会社 潤工社 Printed substrate
JPH0249544B2 (en) * 1984-04-24 1990-10-30 Junkosha Co Ltd
JPS6214490A (en) * 1985-07-11 1987-01-23 日立電線株式会社 Substrate for pga

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