JPH02210851A - Semiconductor chip carrier - Google Patents

Abstract

PURPOSE:To heighten the heat dissipating effect while reducing the characteristic impedance by a method wherein conductor shield layers are connected to a metallic sheet by a conductor formed on the innerwalls of recessions. CONSTITUTION:Conductor shield layers 6 are formed on the whole surface excluding the end peripheral parts of through hole conductive channels 10 and insulating layers 3 in the insulating layers 3 between conductive patterns 5 and a metallic sheet 4. Then, the conductor shield layers 6 fill the role of confining the carrier waves of the electricity fed to the conductive patterns 5 in the limited space so as to reduce the characteristic impedance. Besides, the conductor shield layers 6 are connected to the metallic sheet 4 through the intermediary of a conductor 7 formed on the inner wall of a recession 1 so as to dissipate the heat of a conductor chip mounted on the metallic sheet 4. Furthermore, the metallic sheet 4 exposed to the bottom surface of another recession 2 is connected to a heat conductive layer 8 provided on the surface in the same side as the side whereon the recession 2 is formed through the intermediary of another thermal conductor g formed on the inner wall of the recession 2 so as to further heighten the heat dissipating effect due to the expansion of the heat dissipating area. Through these procedures, the heat dissipating effect can be heightened while reducing the characteristic impedance of the conductive patterns 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a chip carrier used for mounting semiconductors.

(Prior Art) Conventional semiconductor chip carriers, particularly plastic chip carriers, have a known structure shown in FIG. 3 in order to increase heat dissipation from semiconductor chips. an insulating layer 3 in which a second recess 2 for heat dissipation is formed on both front and back surfaces, a metal plate 4 embedded in this insulating layer 3 and exposed at the bottom of the two recesses, and a semiconductor. First recess 1 for chip mounting
The leadless chimp carrier B is provided with a conductive pattern 5 disposed on the surface of an insulating layer 3 on which a conductive pattern 5 is formed, and this conductive pattern 5 extends to the end surface of the insulating layer to serve as an external terminal. In this case, heat radiation is limited by the area of the heat radiation surface of the metal plate 4 exposed at the bottom of the second recess 2. FIG. 4 shows another conventional example in which the first recess l is formed in the insulating layer 3.
A thermally conductive layer 8 disposed on a surface opposite to the surface on which
and a metal plate 4 embedded in the insulating layer 3 and exposed at the bottom of the second recess 2 formed on the same surface as the heat conduction layer 8. The external terminal of the conductive pattern 5 disposed on the surface of the insulating layer 3 on which the first four parts 1 are formed is inserted and bonded to the through-hole conductive path 10 connecting the conductive pattern 5 to the conductive pattern 5. It is known as a bin grid array C formed of terminal bins 11. In this semiconductor chip carrier, the first
The heat generated by the semiconductor chip mounted on the metal plate 4 exposed by the recessed part moves from the metal plate 4 via this heat conductor 9 to the heat conductive layer 8 exposed to the outside, so in the case of FIG. In comparison, the amount of heat dissipated by the heat conductive layer 8 exposed to the outside is added, and the heat dissipation effect is further improved.

However, in the case of the plastic chip carrier according to the above-mentioned conventional example, it is expected to create a semiconductor chip carrier with further enhanced heat dissipation effect.

Furthermore, when the conductive pattern 5 with narrow circuit intervals made on the surface of the insulator N3 operates as a signal circuit, the characteristic impedance becomes large and the signal is delayed, and when the ground of the semiconductor chip is set in the first recess l. However, the buried metal plate 4 has a small ground area, and as a result, there is a problem that the ground potential of the semiconductor chip lacks stability.

To solve these problems, as described in "Printed Wiring Board Reader" (written by Kinji Ito, published by Nikkan Kogyo Shimbun), pages 111-113, a highly conductive metal plate of the same size or larger than the printed wiring board is used. However, the metal plate is not included in the printed wiring board, and it is still not possible to reduce the characteristic impedance inherent in conventional printed wiring boards.

(Problems to be Solved by the Invention) It is an object of the present invention to provide a semiconductor chip carrier including a conductive shield layer that has high heat dissipation, low characteristic impedance of a conductive pattern, and stabilizes the ground potential of the semiconductor chip.

<Means for Solving tJIB> In order to solve the above problems, the present invention provides an insulating layer having a first recess formed on its surface for mounting a semiconductor chip, an insulating layer embedded in this insulating layer and exposed at the bottom of the recess. a conductive shield layer formed in an insulating layer between the conductive pattern disposed on the surface of the insulating layer in which the recess is formed and the metal plate, the conductive shield layer and An object of the present invention is to provide a semiconductor chip carrier characterized in that the metal plate is connected to the metal plate through a conductor formed on the inner wall of the recess.

(Example) A detailed description will be given below based on the drawings. FIG. 1 shows a semiconductor chip carrier according to an embodiment of the present invention. The semiconductor chip carrier shown in FIG. 1 is a metal plate 4 embedded in an insulating layer 3.
are exposed at the bottoms of a first recess 1 for mounting a semiconductor chip and a second recess 2 for heat dissipation, which are formed in the shape of a rectangular prism having the same center on the front and back surfaces of the insulating layer 3. Note that the shape of the recesses is not limited to a rectangular prism shape, but may be a cylinder or the like, and the size of the recesses 1 and 2 is preferably smaller than the metal plate 4 in order to prevent the metal plate 4 from falling off. 1st of
A conductive pattern 5 is arranged on the surface of the recess 1 to be connected to the circuit of the semiconductor chip, and a through-hole conductive pattern is formed in the same insulation YFJ3 to insert a terminal pin that serves as an external terminal. Connected to 10. This conductive pattern 5 is the insulating layer 3
The entire surface of the insulating layer 3 between the conductive pattern 5 and the metal plate 4 except for the through-hole conductive path 10 and the peripheral edge of the end surface of the insulating layer 3 may be extended to the end of the insulating layer 3 to serve as an external terminal. A conductive shield layer 6 is formed, and this conductive shield layer 6 acts to confine the propagating waves of electricity flowing through the conductive pattern 5 within a space to the extent possible, thereby lowering the characteristic impedance. Note that setting the thickness d of the insulating layer between the conductive shield layer 6 and the conductive pattern 5 on the surface of the insulating layer 3 to be less than about 0.3 mm is particularly effective in reducing the characteristic impedance.

This conductor shield layer 6 is connected to the metal plate 4 via a conductor 7 formed on the inner wall of the first recess 1, and also functions to radiate heat generated by the semiconductor chip mounted on the metal plate 4. . Further, the metal plate 4 exposed on the bottom surface of the recess 2 is connected to a heat conductive layer 8 disposed on the same surface on which the recess 2 is formed, via a heat conductor 9 formed on the inner wall of the recess 2.
is connected to. Therefore, the heat generated by the semiconductor chip mounted on the metal plate 4 exposed by the first recess is transferred to the metal plate 4.
Since the heat is transferred from the heat conductor 9 to the heat conductive layer 8 exposed to the outside, the heat dissipation area is expanded and the heat dissipation effect is further improved.

Next, regarding the materials used, as the insulating material N3 constituting the semiconductor chip carrier of FIG. 1, an insulating material obtained by curing the resin of a prepreg obtained by impregnating and drying a base material with a resin is used. Here, the resin for the insulating layer is preferably one that has excellent heat resistance and moisture resistance, and has high resin purity, especially low ionic impurities. Specifically, epoxy resin, polyimide resin, fluorine resin, PPO resin, etc. are suitable. .

As the base material for the insulating layer, an inorganic material such as glass fiber is preferable to paper because of its superior heat resistance and moisture resistance.

Conductive pattern 5 on the surface of the insulating layer 3 on the semiconductor chip mounting side
The thermally conductive layer 8 on the opposite surface and the conductive shield layer 6 formed in the insulating layer 3 can be appropriately selected from copper, brass, aluminum, iron, nickel, stainless steel, etc. Among them, copper can be used. In forming the conductive pattern 5 on the surface of the semiconductor chip mounting side of the insulating layer 3 and the thermally conductive layer 8 on the opposite surface, which is particularly preferable due to its excellent electrical conductivity and thermal conductivity, an additive method or a subtractive method can be used. Various methods are used, such as: To form the conductor shield layer 6, a multilayer printed wiring board manufacturing method such as mass lamination or bottle lamination is used. The through-hole conductive path 10 and the conductor 7 and thermal conductor 9 on the inner wall of the recess are formed by a through-hole plating method or the like when forming the conductive pattern 5 on the surface of the insulating layer 3.

In the second part, a part G of the conductive pattern 5 disposed on the surface of the insulating layer on the semiconductor chip mounting side is shown in FIG.
is connected to the metal plate 4 via a conductor 7 formed on the inner wall of the first recess l. Although not shown, the conductor 7 formed on the inner wall of the recess 1 is also connected to a conductor shield N6 formed within the insulating layer. Therefore, when the ground of the semiconductor chip and the conductive pattern G in the conductive pattern 5 are wire-bonded, the ground area expands to the buried metal body 4 and the conductive shield layer 6 in the insulating layer, so that the ground potential increases. It can be stabilized.

(Effects of the Invention) The present invention is as described above (a first recess for mounting a semiconductor chip is formed on the surface of an insulating layer, a metal plate embedded in the insulating layer is exposed at the bottom of this recess, The gap between the metal plate in which the conductor formed on the inner wall is embedded and the conductive pattern arranged on the surface of the insulating layer in which the recess is formed &! is bonded to the conductor shield layer in the layer. By doing so, a conductor shield layer having an area approximately equal to the semiconductor chip carrier can be secured as a heat conductor to dissipate the heat generated by the semiconductor chip mounted on the metal plate 4 exposed by the first recess. The heat dissipation effect is enhanced compared to the conventional example without a conductive shield layer.Furthermore, the metal plate exposed at the bottom of the second recess is connected to the second recess through a heat conductor formed on the inner wall of the second recess. Since the semiconductor chip mounted on the metal plate 4 exposed by the first recess is connected to the heat conductive layer 8 disposed on the same side surface where the recess is formed, the heat generated by the semiconductor chip mounted on the metal plate 4 exposed by the first recess is transferred from the metal plate 4. The heat is transferred to the heat conductive layer 8 exposed to the outside through the heat conductor 9, further increasing the heat dissipation effect.Also, a conductor shield layer is formed directly below the conductive pattern disposed on the surface of the insulating layer. By doing so, it is possible to confine the electrical propagation waves flowing through the conductive pattern within a finite space and reduce the characteristic impedance.Particularly when the conductive pattern operates as a signal circuit, signal delay can be prevented.

Furthermore, among the conductive patterns wire-bonded to the semiconductor chip, the conductive pattern that serves as the ground is connected to the conductor formed on the inner wall of the first recess, so the ground area is the same as the buried metal body and the insulating layer. It expands to the conductive shield layer. This stabilizes the ground potential.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG. 2 is a perspective view showing a bonding state between the conductor on the inner wall of the first recess and the conductive pattern on the surface of the insulating layer in another embodiment of the present invention. 6A...Semiconductor chip carrier B...Leadless chip carrier C...Pin grid array G... First recess 2... First recess 3... Insulation 1 4... Metal plate 5... Conductive pattern 6.
...Conductor shield layer 7...Conductor 8...
Thermal conductor layer 9...Thermal conductor 10...Through-hole conductive path procedure amendment (voluntary) Display of the July 11, 1999 incident 1999 Patent application No. 31748 Name of the invention Semiconductor chip carrier amendment Relationship with the patent applicant's case Patent applicant address 1048 Kadoma, Kadoma City, Osaka Prefecture
Name (583) Matsushita Electric Works Co., Ltd. Representative Toshio Miyoshi

Claims (3)

[Claims] (1) An insulating layer with a first recess formed on its surface for mounting a semiconductor chip, a metal plate embedded in this insulating layer and exposed at the bottom of the recess, and a metal plate disposed on the surface of the insulating layer in which the recess is formed. a conductor shield layer formed in an insulating layer between the conductive pattern and the metal plate, and the conductor shield layer and the metal plate are connected by a conductor formed on an inner wall of the recess. A semiconductor chip carrier characterized by: (2) comprising a thermally conductive layer disposed on a surface different from the surface of the insulating layer on which the conductive pattern is disposed, and a second recess formed on the surface of the insulating layer on which the thermally conductive layer is disposed; The metal plate and the thermally conductive layer exposed on the bottom surface of this recess are
2. The semiconductor chip carrier according to claim 1, wherein the semiconductor chip carrier is connected by a thermal conductor formed on an inner wall of the recess. (3) A claim characterized in that a part of the conductive pattern disposed on the surface of the insulating layer is connected to the conductor shield layer and the metal plate by a conductor formed on the inner wall of the first recess. Item 1. Semiconductor chip carrier according to item 1.