CN113823571A - Manufacturing method of chip packaging substrate - Google Patents
Manufacturing method of chip packaging substrate Download PDFInfo
- Publication number
- CN113823571A CN113823571A CN202110924971.5A CN202110924971A CN113823571A CN 113823571 A CN113823571 A CN 113823571A CN 202110924971 A CN202110924971 A CN 202110924971A CN 113823571 A CN113823571 A CN 113823571A
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- dry film
- solder resist
- solder
- manufacturing
- base material
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- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims abstract description 122
- 239000000463 material Substances 0.000 claims abstract description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 238000005553 drilling Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000009713 electroplating Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 24
- 239000003292 glue Substances 0.000 claims description 4
- 238000004381 surface treatment Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract description 6
- 230000009172 bursting Effects 0.000 abstract description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 238000007731 hot pressing Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000004880 explosion Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
Abstract
The invention relates to the technical field of chip packaging, and discloses a manufacturing method of a chip packaging substrate. The manufacturing method of the chip packaging substrate comprises the following steps: providing a substrate; drilling a hole on the base material; depositing copper on the base material and the hole wall of the drilled hole; electroplating copper on the surface of the base material and the drilled hole to form an electroplated copper layer; etching the electroplated copper layer to form a conductive circuit, a routing finger and a welding ball pad; making a solder mask layer, comprising: pasting a solder mask dry film for the first time; pasting the solder resist dry film for the second time; and exposing and developing the solder resist dry film to form a solder resist pattern. According to the manufacturing method of the chip packaging substrate, the solder mask layer is formed in a mode of film pasting twice. The gaps between the conducting circuits and the through holes of the base material are filled with the solder resist dry film during the first pasting, the total thickness of the solder resist dry film reaches the thickness of the solder resist dry film required by the solder resist layer during the second pasting, the surface of the solder resist layer is smoother, the adhesion is firmer during the chip pasting, and the yield of the packaging body is improved; and the risk of the package bursting at high temperatures is reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of chip packaging, in particular to a manufacturing method of a chip packaging substrate.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips after a scribing process, then the cut chips are attached to corresponding islands of a substrate through conductive silver adhesive or bonding adhesive tapes, and bonding pads (Bond pads) of the chips are connected to corresponding pins (leads) of the substrate through superfine metal (gold, silver, copper and aluminum) wires or conductive resin to form a required circuit.
When the chip is packaged, a solder mask (solder mask pattern) is arranged on the substrate, and the solder mask coats the conducting circuits and the like on the substrate to form a beautiful outer coat of the circuit board. And the solder mask layer plays a role in long-time insulation and chemical resistance protection and prevents short circuit caused by welding.
In the existing solder mask layer, a vacuum film sticking machine sticks a solder mask with required thickness on the surface of a substrate at one time. However, since the solder resist is thick, the solder resist cannot completely fill the gaps between the conductive traces and the through holes on the substrate when being adhered, so that the surface of the substrate (the solder resist) is uneven, air bubbles can remain in the through holes of the substrate, and the air bubbles in the through holes can cause the bursting of the packaging substrate and even the packaging body at high temperature.
Disclosure of Invention
The present invention is directed to a method for manufacturing a chip package substrate, so as to solve the above problems in the related art.
The embodiment of the invention provides a manufacturing method of a chip packaging substrate, which comprises the following steps:
s1 providing a substrate;
s2 drilling holes on the base material;
s3, depositing copper on the surface of the base material and the hole wall of the drilled hole;
s4, electroplating copper on the surface of the base material and the drilled hole to form an electroplated copper layer;
s5, selectively etching the copper layer to form a conductive circuit, a routing finger and a solder ball pad;
s6, forming a solder mask, including:
s61, pasting a solder mask dry film for the first time;
s62, adhering the solder mask dry film for the second time to make the total thickness of the solder mask dry film reach the thickness of the solder mask dry film required by the solder mask layer;
s63 exposing and developing the solder resist dry film to form a solder resist pattern.
Based on the above scheme, in the method for manufacturing the chip package substrate, the solder mask layer is formed by two times of film pasting when the solder mask layer is manufactured. The dry film thickness of hindering that pastes for the first time is less, uses vacuum sticking machine to paste, when evacuation and hot pressing flattening, can make to hinder and weld the dry film and fill up the space between conducting wire and the conducting wire on the substrate to and the through-hole on the substrate, paste again and hinder and weld the dry film, make the gross thickness that hinders and welds the dry film reach the required dry film thickness of hindering of solder mask. The surfaces of the solder mask layers are smoother by twice film pasting, the adhesion between the chip and the substrate is firmer when the packaged chip is pasted, and the yield of the packaged body is improved; and no bubble is left in the through hole of the substrate, so that the risk of explosion of the packaging body due to expansion of the bubble at high temperature is reduced.
In a possible solution, after step S6, the following steps are further included:
and S7, performing surface treatment on the routing finger and the solder ball pad.
In a possible scheme, in step S61 and step S62, the thickness of the first pasted solder resist dry film and the second pasted solder resist dry film is 1/2 of the thickness of the solder resist dry film required by the solder resist layer.
In one possible solution, in step S61, the thickness of the solder resist dry film that is pasted for the first time is equal to or greater than the thickness of the copper layer.
In one possible scenario, the time between step S62 and step S61 is less than 6 hours.
In a possible solution, before step S3, the following steps are further included:
s301, removing the glue residues.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a chip package substrate according to an embodiment of the invention;
FIG. 2 is a first state diagram of a chip package substrate according to an embodiment of the invention;
FIG. 3 is a second state diagram of the chip package substrate according to the embodiment of the invention;
FIG. 4 is a third state diagram of the chip package substrate according to the embodiment of the invention;
fig. 5 is a fourth state diagram of the chip package substrate according to the embodiment of the invention.
Reference numbers in the figures:
11. a substrate; 12. a conductive circuit; 13. routing fingers; 14. welding a ball pad; 15. and (7) solder-resisting the dry film.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," and the like are used in the indicated orientations and positional relationships based on the drawings for convenience in describing and simplifying the description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention.
In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication connection; either directly or indirectly through intervening media, either internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
As described in the background of the present application, during chip packaging, a solder resist layer (solder resist pattern) is provided on a substrate, and the solder resist layer covers a conductive circuit and the like on the substrate, so as to form a beautiful outer coat of the circuit board. And the solder mask layer plays a role in long-time insulation and chemical resistance protection and prevents short circuit caused by welding.
The inventor of this application discovers, the solder mask of present packaging substrate adopts vacuum sticking film machine will need the solder mask of thickness once to paste on the surface of base plate, through evacuation and press mold, makes the solder mask fill in the space between the base plate circuit and the through-hole of base plate. However, since the solder resist is thick, the solder resist cannot completely fill the gaps between the conductive traces and the through holes on the substrate during the pasting process, so that the surface of the substrate (the solder resist) is uneven, and air bubbles can remain in the through holes of the substrate, and the air bubbles in the through holes can cause the bursting of the packaging substrate and even the packaging body at high temperature.
In order to solve the above problems, the inventor of the present application proposes a technical solution of the present application, and specific embodiments are as follows:
fig. 1 is a flowchart of a method for manufacturing a chip package substrate according to an embodiment of the present invention, fig. 2 is a first state diagram of the chip package substrate according to the embodiment of the present invention, fig. 3 is a second state diagram of the chip package substrate according to the embodiment of the present invention, fig. 4 is a third state diagram of the chip package substrate according to the embodiment of the present invention, and fig. 5 is a fourth state diagram of the chip package substrate according to the embodiment of the present invention. As shown in fig. 1 to 5, the method for manufacturing a chip package substrate of the present embodiment includes the following steps:
s1 provides a substrate 11.
The base material 11 is in a square plate shape, the base material 11 is made of resin and glass fiber cloth, and original copper layers are arranged on the upper surface and the lower surface of the base material 11.
And S2 drilling holes on the base material.
Specifically, a plurality of through holes are formed in the substrate 11 by mechanically or laser drilling holes at the process locations of the substrate 11.
S3 depositing copper on the surface of the substrate and the hole wall of the drilled hole.
Specifically, a copper deposition layer is formed on the surface of the base material 11 and the circumferential hole wall of the drilled hole (through hole) of the base material 11 by depositing copper on the surface of the base material 11 and the circumferential hole wall of the drilled hole of the base material by a chemical copper deposition method.
S4, electroplating copper on the surface of the base material and the drilled hole to form an electroplated copper layer.
Specifically, the copper-deposited base material 11 is plated with copper, and copper plating layers are formed on the upper and lower surfaces of the base material 11 and the hole walls of the drilled holes of the base material 11.
S5 selectively etching the copper layer to form conductive circuit, wire bonding finger and solder ball pad.
Specifically, by attaching a dry film of a circuit, and then performing exposure, development and etching, the copper layer of an unnecessary area on the surface of the substrate 11 is removed, a required conductive circuit 12 is formed on the upper and lower surfaces of the substrate 11, a plurality of wire bonding fingers 13 are formed on the upper surface of the substrate 11, a plurality of solder ball pads 14 are formed on the lower surface of the substrate 11, and the plurality of wire bonding fingers 13 and the plurality of solder ball pads 14 are electrically connected through the conductive circuit 12, so as to form the substrate in the state shown in fig. 2.
S6, manufacturing the solder mask layer, comprising the following steps:
s61 paste solder mask dry film for the first time.
Specifically, a vacuum laminator is used for adhering the dry solder resist film 15 on the upper and lower surfaces of the substrate 11, and the thickness of the dry solder resist film 15 adhered for the first time is smaller than the thickness of the dry solder resist film required by the solder resist layer. The thinner solder resist dry film 15 has better plasticity, after the solder resist dry film 15 is pasted, the solder resist dry film 15 is enabled to fill the gap between the conductive circuit 12 and the conductive circuit 12 on the base material 11 through vacuumizing and hot pressing leveling, the solder resist dry film 15 is enabled to fill the drilled hole (through hole) of the base material 11, the solder resist dry film 15 fills the through hole of the base material 11, and the substrate in the state shown in fig. 3 is formed.
And S62, adhering the solder mask dry film for the second time to make the total thickness of the solder mask dry film reach the thickness of the solder mask dry film required by the solder mask layer.
Specifically, the dry solder resist film 15 is attached again by using a vacuum laminator, and the second dry solder resist film 15 is attached to the first dry solder resist film 15 by vacuumizing and hot pressing leveling, wherein the sum of the thicknesses of the twice attached dry solder resist films 15 is the thickness of the dry solder resist film required by the solder resist layer of the substrate, so that the substrate in the state shown in fig. 4 is formed.
S63 exposing and developing the solder resist dry film to form a solder resist pattern.
Specifically, after the two solder mask dry film pastes, a solder mask pattern is formed on the substrate in an exposure and development mode. In other words, the dry solder mask film 15 on the substrate 11 at the position of the wire bonding finger 13 and the position of the solder ball pad 14 is removed by exposure and development, so that the dry solder mask film 15 is exposed from the wire bonding finger 13 and the solder ball pad 14, and the substrate in the state shown in fig. 5 is formed.
As can be seen from the above, in the method for manufacturing a chip package substrate according to the present embodiment, the solder resist layer is formed by two times of film pasting when the solder resist layer is manufactured. The dry film thickness of hindering that pastes for the first time is less, uses vacuum sticking machine to paste, when evacuation and hot pressing flattening, can make to hinder and weld the dry film and fill up the space between conducting wire and the conducting wire on the substrate to and the through-hole on the substrate, paste again and hinder and weld the dry film, make the gross thickness that hinders and welds the dry film reach the required dry film thickness of hindering of solder mask. The surfaces of the solder mask layers are smoother by twice film pasting, the adhesion between the chip and the substrate is firmer when the packaged chip is pasted, and the yield of the packaged body is improved; and no bubble is left in the through hole of the substrate, so that the risk of explosion of the packaging body due to expansion of the bubble at high temperature is reduced.
Optionally, after step S6, the method for manufacturing a package substrate in this embodiment further includes the following steps:
and S7, performing surface treatment on the routing finger and the solder ball pad.
Specifically, after the solder resist pattern on the substrate is completed, the outer surfaces of the wire bonding finger 13 and the solder ball pad 14 on the substrate are plated with nickel and then with gold, so as to form a nickel layer on the outer surfaces of the wire bonding finger 13 and the solder ball pad 14. The nickel layer coats the copper wire bonding finger and the welding ball pad, so that the oxidation of the wire bonding finger and the welding ball pad is prevented. Meanwhile, when the chip is electrically connected with the routing finger through the gold wire, the gold wire is connected to the nickel layer of the routing finger, so that the conductivity of the routing finger is enhanced.
Further, in the manufacturing method of the package substrate in this embodiment, in step S61 and step S62, the thicknesses of the solder resist dry film pasted for the first time and the solder resist dry film pasted for the second time are both 1/2 of the thickness of the solder resist dry film required by the solder resist layer.
That is to say, the thickness of the solder resist dry film pasted twice is the same, and after the solder resist dry film is pasted twice, the total thickness of the solder resist dry film is the thickness of the solder resist dry film required by the substrate solder resist layer, so that the solder resist dry film is convenient to manufacture.
Further, in the method for manufacturing the package substrate in this embodiment, the thickness of the solder resist dry film pasted for the first time is equal to or greater than the thickness of the copper layer.
Specifically, if the total thickness of the copper-deposited layer and the copper-plated layer on the substrate 11 is about 15 μm, the thicknesses of the wire bonding finger 13, the solder ball pad 14 and the conductive circuit 12 formed on the substrate 11 after the copper layer is etched are about 15 μm. When a solder mask layer is manufactured, the thickness of the solder mask film 15 which is pasted for the first time is 15 μm or slightly larger than 15 μm, and when the solder mask film is vacuumized and leveled by hot pressing, the solder mask dry film 15 is filled in the gaps between the conducting circuits and the through holes of the base material to form the substrate shown in fig. 3; the thickness of the solder resist film 15 similarly applied for the second time is about 15 μm, and the substrate shown in FIG. 4 is formed.
Further, in the method for manufacturing a package substrate in this embodiment, the interval between the step S62 and the step S61 is less than 6 hours.
Specifically, when the solder mask is manufactured, the time interval of two times of film pasting needs to be controlled, the shorter the time interval of the two times of film pasting is, the better the time interval of the two times of film pasting is, and the maximum time interval between the second time of film pasting and the first time of film pasting is less than 6 hours.
Optionally, before step S3, the method for manufacturing a package substrate in this embodiment further includes the following steps:
s301, removing the glue residues.
Specifically, holes are drilled at the process positions of the base material in a mechanical or laser mode, and after a plurality of through holes are formed in the base material, the glue residue left in the drilling process on the base plate is removed, so that the drilling and the surface of the base plate are kept smooth, and the smooth proceeding of the subsequent processes is ensured.
In the present invention, unless otherwise explicitly specified or limited, the first feature "on" or "under" the second feature may be directly contacting the first feature and the second feature or indirectly contacting the first feature and the second feature through an intermediate.
Also, a first feature "on," "above," and "over" a second feature may mean that the first feature is directly above or obliquely above the second feature, or that only the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lower level than the second feature.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (6)
1. The manufacturing method of the chip packaging substrate is characterized by comprising the following steps of:
s1 providing a substrate;
s2 drilling holes on the base material;
s3, depositing copper on the surface of the base material and the hole wall of the drilled hole;
s4, electroplating copper on the surface of the base material and the drilled hole to form an electroplated copper layer;
s5, selectively etching the copper layer to form a conductive circuit, a routing finger and a solder ball pad;
s6, forming a solder mask, including:
s61, pasting a solder mask dry film for the first time;
s62, adhering the solder mask dry film for the second time to make the total thickness of the solder mask dry film reach the thickness of the solder mask dry film required by the solder mask layer;
s63 exposing and developing the solder resist dry film to form a solder resist pattern.
2. The method for manufacturing a package substrate according to claim 1, further comprising, after the step S6, the steps of:
and S7, performing surface treatment on the routing finger and the solder ball pad.
3. The method for manufacturing the package substrate according to claim 2, wherein in the steps S61 and S62, the thickness of the solder resist dry film pasted for the first time and the solder resist dry film pasted for the second time is 1/2 of the thickness of the solder resist dry film required by the solder resist layer.
4. The method for manufacturing the package substrate according to claim 3, wherein in step S61, the thickness of the solder resist dry film pasted for the first time is equal to or greater than the thickness of the copper layer.
5. The method of claim 3, wherein the interval between the step S62 and the step S61 is less than 6 hours.
6. The method for manufacturing a package substrate according to claim 1, further comprising, before the step S3, the steps of:
s301, removing the glue residues.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110924971.5A CN113823571A (en) | 2021-08-12 | 2021-08-12 | Manufacturing method of chip packaging substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110924971.5A CN113823571A (en) | 2021-08-12 | 2021-08-12 | Manufacturing method of chip packaging substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113823571A true CN113823571A (en) | 2021-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110924971.5A Pending CN113823571A (en) | 2021-08-12 | 2021-08-12 | Manufacturing method of chip packaging substrate |
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| Country | Link |
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| CN (1) | CN113823571A (en) |
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2021
- 2021-08-12 CN CN202110924971.5A patent/CN113823571A/en active Pending
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Address after: No. 9688, Songze Avenue, industrial park, Qingpu District, Shanghai, 201799 Applicant after: ChipMOS Technologies (Shanghai) Co.,Ltd. Address before: No. 9688, Songze Avenue, industrial park, Qingpu District, Shanghai, 201799 Applicant before: UNIMOS MICROELECTRONICS(SHANGHAI) Ltd. |
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