JP2010194337A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine which can surely reproduce a game operation before a power source interruption even if a power supply voltage when applying a power source and when the power source is restored is instable. <P>SOLUTION: A main control part mainly executing a game control operation is provided with: an input part for receiving a voltage drop signal ABN outputted from a voltage monitoring part: determination processing for obtaining data from the input part for every prescribed time and detecting a power failure; and a saving processing for stopping subsequent game control and storing a backup flag BFL being set to 5AH into a flag storage area of a RAM. In a system reset processing of the main control part started based on the restoration and application of the power supply voltage, the backup flag BFL in the flag storage area is changed to set from 5AH to 00H, and then a subsequent processing is started, after confirming that there is no power failure based on the data obtained from the input part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a gaming machine configured with a computer circuit, and more particularly to a gaming machine that can reliably resume a gaming operation before power-off even when the power supply voltage is unstable when power is restored.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7-7-7, a big hit state is established, and the big winning opening is repeatedly opened to generate a profit state advantageous to the player.

In such a gaming machine, a backup process is provided so that even if a sudden power failure occurs, the profit state for the player does not disappear. Specifically, when the AC power supply is cut off, the CPU has a non-maskable interrupt (NMI: non maskable interrupt).
) And the value of the internal register of the CPU is stored in the stack area in the NMI interrupt processing until the DC power supply completely drops. Even after the DC power supply is cut off, the backup power is supplied to the RAM.

  For this reason, the data in the work area can be maintained at the value before the power is cut off by the backup power supply, and the interrupted gaming state can be resumed only by restoring the value of the internal register of the CPU from the stack area after the power is restored ( For example, Patent Document 1).

Japanese Patent Application No. 2006-233614

  However, in the invention described in Patent Document 1, since the NMI processing is unconditionally started in response to the power supply voltage drop, the stack area is used by the NMI processing whenever the power supply voltage drops repeatedly at the time of power recovery. As a result, there is a possibility that the work area of the RAM adjacent to the stack area is eventually damaged.

  In addition, since it is impossible to predict at what timing during the game operation the power supply voltage will drop, it is necessary to construct NMI processing at power-down and return processing after power-return in consideration of all possibilities. It was very difficult to achieve perfect operation with simple processing.

  Note that the above points are basically the same even when a maskable interrupt is used instead of the NMI. In view of this, it is conceivable to adopt a flag sense method (polling method) instead of the interrupt method and periodically check for the presence or absence of power interruption.

  However, in this type of gaming machine, in order to detect illegal modification of the control program, a security check process unrelated to the CPU process is usually executed before the execution of the control program. If simply polling, it may not be possible to deal with power failure. That is, since the security check process requires a considerable amount of processing time, for example, when the power supply voltage drops again when power is restored, the DC power supply voltage drops completely before the polling process is executed, The backup process may not be in time.

  The present invention has been made in view of the above problems, and a gaming machine that can reliably reproduce a gaming operation before power-off even when the power supply voltage is unstable when power is turned on or restored. The purpose is to provide.

In order to achieve the above object, the present invention is a gaming machine provided with a voltage monitoring unit that outputs a voltage drop signal when the power supply voltage drops, and a backup power supply that maintains the memory contents after the power supply voltage is cut off. An input unit that receives a voltage drop signal output from the voltage monitoring unit, a determination process that acquires data from the input unit every predetermined time to detect a power supply abnormality, and a power supply abnormality is detected by the determination process Then, the subsequent game control is stopped, and a save process for saving the specific data set to the first level in the flag storage area of the RAM is provided in the main control unit mainly responsible for the game control operation, In the system reset process of the main control unit that is activated based on voltage restoration or input, after confirming that there is no power supply abnormality based on the acquired data from the input unit, the flag storage area The specific data is changed from the first level to the second level, and the process after the interruption is started.

In the present invention, after confirming that there is no power supply abnormality based on the acquired data from the input unit, the specific data in the flag storage area is changed from the first level to the second level, while the subsequent processing is performed when the power supply is abnormal Since it does not shift to, power supply abnormality can be handled appropriately. In the embodiment, the first level is 5AH and the second level is 00H, but it is not always necessary to change it in a binary manner.

  It should be noted that the present invention is suitably applied to a gaming machine having a configuration that generates a profitable state advantageous to the player through a lottery determination, and more preferably a ball game machine such as a pachinko machine or a slot machine. It should be applied to a spinning machine.

  In the present invention, preferably, the value of the stack pointer that specifies the top address of the data group in the stack area to be retained even after the power is shut off is not changed before and after the save processing (however, it does not need to be continued). Stored in the address storage area. In addition, the operation of the main control unit includes a system reset process that is activated based on restoration or input of a power supply voltage, and a maskable timer interrupt process that is activated at regular intervals, and an unmaskable interrupt process. It is preferable that the save process is provided in the timer interrupt process. Further, the system reset process and the save process are provided with a calculation process for executing the same calculation for a specific data group in the RAM, and if the respective calculation results do not match, While the contents are erased, if the respective calculation results match, it is preferable to be configured to return to a fixed fixed process.

  Preferably, the voltage monitoring unit monitors an abnormality in the AC voltage input to the power supply circuit and an abnormality in the DC voltage output from the power supply circuit, and outputs a voltage drop signal based on any abnormality. It is configured. According to this configuration, since the interruption of the AC input power supply can be detected quickly, a sufficient time can be ensured before the start of the backup process (evacuation process). Therefore, there is no problem even if the flag sense method is adopted instead of the interrupt method. Rather, since the interrupt method is not adopted, it is possible to fix the process to be resumed when the power is restored, and to simplify the backup process to the limit. Therefore, it is not necessary to react sensitively to the instantaneous interruption of the AC power supply, and the gaming operation can be continued until immediately before the DC power supply voltage drops to the limit point.

  According to the above-described present invention, it is possible to realize a gaming machine that can reliably reproduce a gaming operation before power-off even when the power supply voltage is unstable when the power is turned on or when the power is restored.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated in detail the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. The circuit configuration of the power supply board and the internal configuration of the one-chip microcomputer are illustrated. It is a circuit diagram which shows a part of power supply board | substrate in detail. It is a flowchart explaining the system reset process of a main control part. It is a flowchart explaining the timer interruption process of a main control part. It is a flowchart explaining a part of timer interruption process. It is a flowchart which illustrates the example of a change.

  Hereinafter, the present invention will be described in detail based on a ball game machine according to an embodiment. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be freely opened and closed.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. An upper plate 8 for storing game balls for launch is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowing from or extracted from the upper plate 8 and a launch handle 10 are mounted at the bottom of the front frame 3. And are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, the game board 5 is provided with a guide rail 13 formed of a metal outer rail and an inner rail in an annular shape, and a liquid crystal color display DISP is provided at the approximate center of the game area 5a inside. Is arranged. In addition, at a suitable place in the game area 5a, a symbol starting port 15, a big winning port 16, a plurality of normal winning ports 17 (four on the right and left sides of the big winning port 16), and a gate 18 serving as two passing ports are arranged. Has been. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  The liquid crystal display DISP is a device that variably displays a specific symbol related to a big hit state and displays a background image and various characters in an animated manner. This liquid crystal display DISP has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. The special symbol display portions Da to Dc execute a reach effect that expects a big hit state to be invited, and the special symbol display portions Da to Dc and the surroundings perform a notice effect that informs the result of the determination indefinitely. The

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time, and the lottery extracted at the time when the game ball passes through the gate 18 is extracted. The stop symbol determined by the random number for use is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws 15a. When the stop symbol after the fluctuation of the normal symbol display unit 19 displays a winning symbol, the symbol start port 15 is opened and closed. The claw 15a is opened for a predetermined time.

On the other hand, when a game ball wins at the symbol start port 15, the display symbols of the special symbol display portions Da to Dc change for a predetermined time, and are determined based on the lottery result corresponding to the winning timing of the game ball at the symbol start port 15. Stop at the stop symbol. In addition, in special symbol display parts Da-Dc and its circumference, a notice effect may be performed between a series of symbol effects.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. Broken lines in the figure mainly indicate DC voltage lines.

  As shown in the figure, the pachinko machine GM includes a power supply board 20 that receives 24V AC and outputs various DC voltages and a system reset signal SYS, a main control board 21 that is centrally responsible for game control operations, and a main control board 21. The effect control board 22 for executing the lamp effect and the sound effect based on the control command CMD received from the effect interface board 23 for transmitting the signal received from the effect control board 22 to each part, and the effect interface board 23 The liquid crystal control board 24 that drives the liquid crystal display DISP based on the control command CMD ′ and the payout control board 25 that pays out the game ball by controlling the payout motor M1 based on the control command CMD ″ received from the main control board 21 And a launch control board 26 that launches a game ball in response to a player's operation.

  Here, the main control board 21, the effect control board 22, the liquid crystal control board 24, and the payout control board 25 are each mounted with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the main control board 21, the production control board 22, the liquid crystal control board 24, the circuits mounted on the payout control board 25, and the operations realized by the circuits are collectively referred to as functions. The control unit 21, the production control unit 22, the liquid crystal control unit 24, and the payout control unit 25 may be referred to. All or part of the effect control unit 22, the liquid crystal control unit 24, and the payout control unit 25 are sub-control units.

  As shown in the figure, the main control unit 21 is connected to the command relay board 29 and is connected to each game component of the game board 5 via the game board relay board 27. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. Note that the switch signal from the symbol start port 15 is received directly by the main control unit 21 without going through the game board relay board 27.

  The main control unit 21 transmits a control command CMD ″ to the payout control unit 25 in one direction, while the payout control unit 25 receives a prize ball count signal indicating a game ball payout operation and a payout operation. The status signal CON related to the abnormality is received, and the status signal CON includes, for example, a replenishment out signal, a payout shortage error signal, and a lower plate full signal.

By the way, a backup power supply BU of DC 5V is supplied from the power supply board 20 to the one-chip microcomputer of the main control unit 21 and the payout control unit 25. Therefore, even after the AC power supply 24V is shut off due to the end of business or a power failure, the RAM data in the one-chip microcomputer is retained. In this embodiment, the storage contents of the RAM are designed to be retained for at least several days.

  Further, the power supply board 20 is configured to output a voltage drop signal ABN to the main control unit 21 and the payout control unit 25 when the AC power supply 24V is shut off. In this embodiment, the voltage drop signal ABN is supplied not to the interrupt terminal of each one-chip microcomputer but to the input port (PIO unit). The main control unit 21 and the payout control unit 25 grasp the level drop of the voltage drop signal ABN by the flag sense method, and then save necessary data in the RAM. Therefore, coupled with the operation of the backup power supply BU described above, the main control unit 21 and the payout control unit 25 can resume the operation before the power shutoff at the start of business or at the time of recovery from a power failure. However, since the backup power supply BU is not supplied to the other control boards, the operation in the initial state is started regardless of the operation before the power is shut off at the time of starting business or recovering from the power failure.

  FIG. 4 illustrates the internal configuration of the one-chip microcomputer 30 mounted on the main control board 21, the circuit configuration of the power supply board 20, and the connection relationship between both boards.

  As shown in the figure, the power supply substrate 20 includes a rectifying unit 50 that receives AC 24V and converts it into a pulsating voltage (effective value 24V), and a first voltage converting unit that uses a stabilized power supply IC that converts the pulsating voltage into DC 5V. 51, a second voltage conversion unit 52 that converts the pulsating voltage to DC 12V, a third voltage conversion unit 53 that converts the pulsating voltage to DC 32V, and a power storage that stores the output voltage of the first voltage conversion unit 51. And a voltage monitoring unit 55 that detects a power-on state and a power-off state and outputs a system reset signal SYS and a voltage drop signal ABN.

  As shown in the figure, the power storage unit 54 includes a capacitor C having a large capacity (for example, about 1 farad), limiting resistors r1 and r2 for overcurrent, and a diode D for blocking reverse current. The voltage BU across the capacitor C is supplied to the built-in RAM of the one-chip microcomputer 30, and the stored contents of the built-in RAM are held for at least several days even when the power supply voltage is cut off.

  FIG. 5 is a circuit diagram showing the voltage monitoring unit 55 in more detail. The voltage monitoring unit 55 includes a voltage drop detection unit FALL and a power-on detection unit RST.

  The voltage drop detection unit FALL receives the AC voltage 24V, switches ON / OFF, detects the ON / OFF state of the switching unit SW, detects the DET1, and outputs the detection unit DET1 with delay. A delay unit DLY1, a first output unit OT1 that receives an output from the delay unit DLY1, and performs an ON / OFF operation; a detection unit DET2 that detects a voltage drop of DC5V; and a delay unit that delays and transmits the output of the detection unit DET2 It is composed of DLY2 and a second output unit OT2 that receives the output of the delay unit DLY2 and performs ON / OFF operation. The voltage drop signal ABN is output from the first output unit OT1 and the second output unit OT2.

  The switching unit SW is mainly configured by a rectifying unit including a resistor R1 and a capacitor C1, and a transistor Q1 that performs an ON / OFF operation based on an output value of the capacitor C1. When AC24V is normally supplied, the transistor Q1 is turned on, and the output of the switching unit SW becomes L level. On the other hand, when the voltage of AC24V decreases and the output of the capacitor C1 decreases, the transistor Q1 is turned off and the output of the switching unit SW becomes H level.

The detection unit DET1 includes voltage dividing resistors R4 and R5, a reference voltage Er1, and a comparator AP1. Since the voltage dividing resistor R5 is connected in parallel to the transistor Q1, when the transistor Q1 is in the ON state, R5 is short-circuited, and the output of the detection unit DET1 is at the H level. Conversely, when the transistor Q1 is in the OFF state, the output of the detection unit DET1 is at the L level.

  The delay unit DLY1 includes transistors Q2 and Q3 that perform ON / OFF operation, a constant current source A1 of about 5 μA, a Schmitt trigger type inverting amplifier AP2, and a capacitor C2 that is charged by the constant current source A1. . When the transistor Q2 changes to the OFF state, charging of the capacitor C2 is started by the constant current source A1. Therefore, the transmission of the H level output of the transistor Q2 is delayed until the voltage across the capacitor C2 to be charged changes from the L level to the H level. Note that when the transistor Q2 changes to the ON state, the charge of the capacitor C2 is quickly discharged, so that the L level output of the transistor Q2 is immediately transmitted.

  The first output unit OT1 includes voltage dividing resistors R6 to R8, an ON / OFF transistor Q4, and a load resistor R9 of the transistor Q4. The second output unit OT2 includes voltage dividing resistors R12 to R14, a transistor Q7 that performs ON / OFF operation, and a load resistor R9 of the transistor Q7. Here, since the transistor Q4 and the transistor Q7 are connected in parallel, a wired OR logic is realized together with the load resistor R9. That is, when at least one of the transistor Q4 and the transistor Q7 is turned on, the outputs (voltage drop signal ABN) of the output units OT1 and OT2 become L level.

  The detection unit DET2 includes voltage dividing resistors R10 and R11, a reference voltage Er2, and a comparator AP3. Therefore, when the power supply voltage (DC5V) is lowered, the output of the detection unit DET2 becomes H level. Conversely, if the power supply voltage is a normal value, the output of the detection unit DET2 is at the L level.

  The delay unit DLY2 includes transistors Q5 and Q6 that perform ON / OFF operation, a constant current source A3 of about 5 μA, a Schmitt trigger type non-inverting amplifier AP4, and a capacitor C3 that is charged by the constant current source A3. Yes. When the transistor Q5 changes to the OFF state, charging of the capacitor C3 is started by the constant current source A3. Therefore, the transmission of the H level output of the transistor Q5 is delayed until the voltage across the capacitor C3 to be charged changes from the L level to the H level.

  As described above, the voltage drop detection unit FALL includes the switching unit SW and the detection unit DET1 that monitor the voltage value of AC 24V, and the detection unit DET2 that monitors the voltage value of DC 5V. When any one of the voltage values decreases from the normal value, the voltage drop signal ABN changes to the L level. Therefore, the CPU of the main control unit can determine the drop in the power supply voltage based on the level of the voltage drop signal ABN.

  As a precaution, the operation content at the time of AC voltage drop will be described. First, in response to the voltage drop of 24V AC due to power interruption, the transistor Q1 constituting the switch unit SW is turned off, and the inverting input to the comparator AP1. The voltage increases. Therefore, the output of the comparator AP1 changes from the H level to the L level, and the transistor Q2 changes to the OFF state.

Then, charging of the capacitor C2 is started by the constant current source A1 (see arrow), and becomes the H level voltage after a predetermined delay time from the L level voltage. When the voltage across the capacitor C2 becomes H level, the output of the inverting amplifier AP2 becomes L level. As a result, the transistor Q3 changes from the ON state to the OFF state, and the transistor Q4 changes from the OFF state to the ON state. In the present embodiment, (a) the voltage drop signal ABN is monitored by the flag sense method, (b) the power supply monitoring process (ST31) is extremely simple, and (c) the power supply monitoring process (ST31). Is executed every short time (4 mS), the delay unit D
The delay time of LY1 can be set extremely long.

  In any case, as a result of the above-described operation, the voltage drop signal ABN falls from the H level to the L level in response to the power interruption. Note that the comparator AP3, the non-inverting amplifier AP4, and the transistors Q5 to Q7 are understood to invert the operation after the fall of the voltage drop signal ABN accompanying the decrease in AC24V. However, the transistor Q7 performs wired logic together with the transistor Q4. Since it is configured, the voltage drop signal ABN is not changed.

  As described above, the voltage drop detection unit FALL of this embodiment includes a circuit that monitors a voltage drop of 24 VAC and a circuit that monitors a voltage drop of 5 VDC. This is because, for example, the rectifying unit 50 is operating normally, but the first voltage conversion unit 51 may fail and only the DC voltage DC5V may be reduced. This is because the operating state of the gaming machine can be correctly backed up and saved.

  On the other hand, the power-on detection unit RST shown in FIG. 5 also has a substantially similar circuit configuration, a detection unit DET3 that detects a voltage change of DC5V, a delay unit DLY3 that delays and transmits the output of the detection unit DET3, and a delay The third output unit OT3 that performs ON / OFF operation in response to the output of the unit DLY3.

  The detection unit DET3 includes voltage dividing resistors R17 and R18, a reference voltage Er3, and a comparator AP5. The delay unit DLY3 includes transistors Q8 and Q9 that perform ON / OFF operation, a constant current source A5 of about 5 μA, a Schmitt trigger type inverting amplifier AP6, and a capacitor C6 that is charged by the constant current source A5. . The third output unit OT3 includes a load resistor R19 of the transistor Q9, a noise absorbing capacitor C7, and two inverters G4 and G5.

  When the power is turned on, the power supply voltage (DC5V) rises with an inclination. In accordance with this, the output of the comparator AP5 becomes L level, and the transistor Q8 is turned off. Therefore, the capacitor C6 is charged by the constant current source A5 (see the arrow), and becomes the H level voltage after the delay time td from the L level voltage. Then, after this delay time td, the transistor Q9 changes from the ON state to the OFF state, and the output of the third output unit OT3 changes from the L level to the H level.

  As described above, the system reset signal SYS is at the L level for a predetermined time td due to the start of the supply of the AC voltage 24V. On the other hand, the voltage drop signal ABN is fixedly at the L level when the AC voltage 24V drops or the power supply abnormality where the DC 5V drops is abnormal. Therefore, there is no problem even if the flag sense method is adopted.

  Next, returning to FIG. 4, the internal configuration of the one-chip microcomputer 30 of the main control unit 21 will be described. This one-chip microcomputer 30 includes a CPU core 31 equivalent to Z80 (Zilog), a clock generator 32 for generating a system clock, a reset circuit 33 for receiving a system reset signal SYS from the outside, an external bus interface circuit 34, , A Z80CTC (Counter Timer Circuit) unit 35, an address decoder 36, a Z80 PIO (Parallel Input Output) unit 37, a watchdog timer 38, a built-in RAM 39, a built-in ROM 40, and a security check circuit 41 are built in. Has been.

In this embodiment, the 4 mS cycle timer signal generated by the Z80 CTC unit 35 is supplied to the interrupt terminal INT of the CPU core 31. CPU core 31 interrupt terminal IN
T is a maskable interrupt terminal, and when the CPU core 31 executes a DI (Disable interrupt) instruction or when the CPU core 31 accepts an interrupt, the EI (enable interrupt) instruction is newly issued. The interrupt signal is not accepted unless. Conversely, if the CPU core 31 is in the interrupt acceptance state, an interrupt signal is accepted every 4 mS, and a timer interrupt process described later is started.

  When the reset circuit 33 receives the system reset signal SYS, the security check circuit 41 is configured to continuously access the built-in ROM 40 and start a check operation. This check operation does not involve the CPU core 31, and a predetermined operation is performed over a plurality of addresses of the built-in ROM 40 by the hardware function of the security check circuit 41, and check data stored in the built-in ROM 40 in advance. Consistency with is confirmed.

This confirmation operation (security check operation) is an operation for detecting illegal modification of the control program. Then, the process of reading the control program stored in the built-in ROM 40 and the determination process that has undergone a predetermined calculation are executed, so that, for example, about 1,420,000 system clocks are consumed. When the confirmation operation that consumes a certain amount of time ends normally, the program counter of the CPU core 31 becomes 0000H, and the execution of the control program stored in the internal ROM 40 starting from address 0 is started. As described above, the CPU core 31 does not function from the power-on to the end of the security check operation, and the address bus and data bus of the one-chip microcomputer 30 are in a high impedance (Hi-Z) state.

  By the way, in this embodiment, as shown in FIG. 4, a clear signal is supplied from the output port of the PIO unit 37 to the watchdog timer 38 every predetermined time. This operation prevents the watchdog timer 38 from timing out. However, if the program runs away and the clear signal is interrupted, the watchdog timer 38 times out and the CPU core 31 is reset. A reset signal is supplied to the terminal RESET. When the reset signal is supplied, the program counter of the CPU is automatically rewritten to 0000H, and the control program is re-executed from the initial state.

6 to 8 are flowcharts showing a control program of the main control unit 21. The control program of the main control unit 21 includes a system reset process (FIG. 6) that is activated based on the restoration or input of the power supply voltage, and a maskable timer interrupt process that is activated at predetermined time intervals (4 mS) (FIG. 7: TIMER INT). Note that even if the voltage drop signal ABN is supplied from the power supply board 20, the interrupt process (NMI interrupt) is not started.

  Hereinafter, the system reset processing program (main processing) will be described with reference to FIG. The main process starts when the initialization switch (not shown) is turned off and the power is turned on, such as when recovering from a power outage, and when the game hall is opened. May be turned on to turn on the power. In some cases, the watchdog timer 38 is activated and the CPU core 31 is forcibly reset due to a runaway control program. In FIG. 6, in order to distinguish between the two, the former is system reset and the latter is This is called user reset.

  As described above, in the system reset state in which the system reset signal SYS is supplied from the power supply board 20, the security check circuit 41 starts the security check operation before the CPU core 31 functions. When the security check operation ends normally, the program counter of the CPU core 31 becomes 0000H, and the initial setting process in step ST1 is started as in the case of the user reset state.

  In the initial setting process (ST1), each part of the one-chip microcomputer including the Z80 CPU core 31 is initialized, but the CPU core 31 is in an interrupt disabled state (DI). Therefore, all the timer interrupt signals supplied from the CTC unit 35 to the interrupt terminal INT are ignored. Thereafter, the value of the RAM clear signal is determined (ST2). The RAM clear signal is a signal for determining whether or not to initialize all areas of the built-in RAM, and has a value corresponding to the ON / OFF state of the initialization switch operated by the staff.

  Here, assuming that the RAM clear signal is in the ON state, following the determination in step ST2, the entire area of the built-in RAM is cleared to zero (ST10). Therefore, the value of the backup flag BFL at address BFL shown in FIG. 8C becomes zero together with other checksum values.

  Next, a RAM clear command CMD for notifying that the RAM area has been cleared to zero is output to the effect control unit 22 (ST11). Thereafter, on condition that the voltage drop signal ABN is not at the L level (ST12 to ST13), the CPU is set to the interrupt enabled state by executing the EI command (ST14).

  Since the voltage drop signal ABN is constantly supplied to the input port of the PIO unit 37 of the one-chip microcomputer 30 (see FIG. 4), the processing of ST12 to ST13 is performed in an infinite loop unless the level is normal. Repeat. Therefore, in the event of an abnormality such as when the power source that has been turned on is immediately shut off, the start of the gaming operation is prohibited and the occurrence of an abnormal gaming operation is prevented in advance.

  On the other hand, if the voltage drop signal ABN is at a normal level, after executing the EI command (ST14), counter update processing is executed in an infinite loop (ST15). The counter to be updated includes a missed symbol counter. This missed symbol counter can be used when the missed symbol determination process in the special symbol process (ST45) in FIG. It is a counter for deciding whether to produce the off-game of such a mode.

  Hereinafter, the description will be continued by returning to the determination process of step ST2. When the CPU is forcibly reset (user reset state), or when the initialization switch (RAM clear signal) is in an OFF state, such as when recovering from a power failure state, the determination at step ST2 follows. Thus, the content of the backup flag BFL is determined (ST3). The backup flag BFL is data indicating whether or not the save processing (ST53 to 56) shown in FIG. 8 has been normally completed. In this embodiment, the backup flag BFL is set to 5AH in the power supply monitoring processing (ST55). It is cleared to zero in the process of step ST9.

  When the power is turned on or when the power is restored from the power failure state, the content of the backup flag BFL is 5AH. However, if the program goes into a runaway state for some reason and a CPU reset operation is caused by the watchdog timer, the backup flag BFL = 00H. Therefore, when BFL ≠ 5AH (normally BFL = 00H), the process proceeds from step ST3 to step ST10 to return the operation of the gaming machine to the initial state.

  On the other hand, if the backup flag BFL = 5AH, a checksum operation for calculating a checksum value is executed (ST4). Here, the checksum operation is an 8-bit addition operation on the work area of the internal RAM (see FIG. 8C). When the checksum value is calculated, the calculation result is compared with the stored value at the SUM address in the RAM (ST5).

  In the SUM address, the checksum value by the same checksum calculation is stored in the saving process (ST53 to ST56 in FIG. 8) executed when the voltage drops. The stored calculation result is maintained by the backup power supply BU together with other data of the built-in RAM. Therefore, the two should be matched by the determination in step ST5.

  However, the data in the work area may be corrupted between the execution of the checksum calculation (ST54) in the power monitoring process and the execution of the checksum calculation (ST4) in the main process. In step ST5, the determination result is inconsistent. If data corruption is detected due to a discrepancy in the determination result, the gaming state before the power supply voltage drop can no longer be resumed normally, so the process proceeds to step ST10 to execute the RAM clear process, The operation of the gaming machine is returned to the initial state.

  On the other hand, if it is determined in step ST5 that the checksum value obtained by the checksum calculation (ST4) matches the stored value at the SUM address, the data in the built-in RAM is normally maintained by the backup power supply BU. Can be considered. Therefore, next, the gaming state before power-off is resumed, but in this embodiment, the level of the voltage drop signal ABN is checked before the game is resumed (ST6 to ST7).

  This is in order to appropriately cope with an abnormal situation in which the power supply voltage is shut off again immediately after the power is turned on. For example, assume a case where a power outage suddenly occurs during business. In such a case, the game before the power failure should be able to be resumed correctly through the power supply monitoring process (ST31) described later. However, if the power supply is cut off immediately after the power supply is restored, the CPU operates due to a drop in the power supply voltage immediately after rewriting the backup flag BFL to 00H after processing time such as security check processing. It may be impossible. In such a case, even if the power supply is restored after that, since the backup flag BFL = 00H, the RAM is cleared (ST10), and the gaming operation before the power failure can no longer be resumed.

  Therefore, in this embodiment, in order to prevent such a situation from occurring, the voltage drop signal ABN is acquired from the PIO unit 37 of the one-chip microcomputer 30 (ST6), and unless the level is normal, step ST6 The process of ~ ST7 is repeated in an infinite loop. Therefore, the backup flag BFL is not rewritten when the power is shut off, and the processing of steps ST4 to ST9 is executed again when the power is restored thereafter, so that the gaming operation before the power shutoff is resumed correctly.

  On the other hand, when the voltage drop signal ABN is at a normal H level, the numerical value stored in the SP storage area of the RAM (see FIG. 8C) is written into the stack pointer SP inside the CPU core 31 ( ST8). Further, the value of the backup flag BFL is reset to zero (ST9), and the process jumps to the start address XXYY of the random number generation process in step ST32. In this state, the CPU core 31 remains in the interrupt disabled (DI) state.

  In the SP storage area, the head address of the save register area (the register value storage area saved in the process of step ST30) shown in FIG. 8C is stored in the power supply monitoring process (ST53). Therefore, after executing a series of timer interrupt processes after step ST32 in the DI state, the value of the save register is correctly returned to the CPU core by the process of step ST49, and the execution of the RETI instruction after execution of the EI instruction (ST50) To return to the infinite loop processing (ST15) before the timer interruption.

Next, a timer interrupt processing program (FIG. 7) started every 4 mS by interrupting the above infinite loop processing (ST15) of FIG. 6 will be described. When a timer interrupt occurs, the contents of each register are saved in the stack area (ST30), and then a power supply monitoring process is first executed (ST31). Note that, due to the timer interrupt, the CPU core 31 enters an interrupt disabled state.

  FIG. 8A is a flowchart specifically showing the contents of the power supply monitoring process. First, the voltage drop signal ABN is acquired from the PIO unit 37 of the one-chip microcomputer 30 (ST51), and its level is determined (ST52). If the voltage drop signal ABN is a normal value of H level, the subroutine processing is finished as it is. On the other hand, if voltage drop signal ABN is at L level, it is determined that AC power supply AC24V is in a cut-off state. Note that, as described in detail with reference to FIG. 5, the interruption state of the AC power supply AC24V is quickly detected at an appropriate timing, so that the DC power supply voltage (DC5V) is maintained for a while thereafter. (ST53 to ST56) becomes possible.

In the saving process, first, a numerical value obtained by adding +2 to the value of the stack pointer SP at that time is stored in the SP storage area of the RAM (ST53). Now, in the process of step ST30 (FIG. 7), it is assumed that instructions are executed in the order of PUSH AF → PUSH BC → PUSH DE → PUSH HL. Further, in the processing of steps ST31 and ST32, CALL CHECK → CAL
Assume that instructions are executed in the order of L RANDOM. It is assumed that the CALL RANDOM machine language instruction is stored after the XXYY address.

In such a case, at the start of the power supply monitoring process (ST31), the stack area is as shown in FIG. That is, the stack pointer SP points to the top of the stack area taking FILO (First In Last Out), and the top of the stack area has a lower address value (XYLY) of the return address XXYY of the subroutine processing (CALL CHECK). = YY) is stored. Further, a return address HHLL after the end of the timer interrupt process (TIMER INT) is stored following the group of register values stored by executing the instruction of PUSH AF →... → PUSH HL. Note that this return address HHLL means a storage address of one group of instructions for realizing the process of step ST15.

As described above, in this embodiment, at the beginning of the save process (ST53 to ST56), a value obtained by adding 2 to the value of the stack pointer SP is stored in the SP storage area of the RAM (ST53). Therefore, the return address (= XXYY) after execution of the CALL CHECK instruction disappears, but after the save processing (ST53 to ST56) ends, the CPU core becomes inoperative and the power supply voltage (DC5V) disappears. And after the power is restored, the random number generation process (ST32) is started through the JP XXYY instruction, so there is no problem.

  When the process of step ST53 is completed, the same checksum calculation as step ST4 of the main process is executed (ST54). Specifically, 8-bit addition is continuously performed on the work area of the internal RAM (see FIG. 8C), and the addition result is stored as a checksum value at the SUM address. Since it is preferable that the area to be subjected to 8-bit operation is wide, the entire area of the RAM excluding the SUM address and the BFL address (backup flag BFL) is used here.

  Thereafter, after storing the flag value 5AH at the address BFL (ST55), access to the RAM is prohibited, and the CPU waits for the power supply voltage to drop and the CPU to become inoperative (ST56). After that, the CPU becomes inoperative, but the backed up data is maintained as it is because the backup power BU is supplied to the RAM.

The power monitoring process (ST31) in FIG. 7 has been described with respect to the case where the voltage drop signal ABN is at the L level. Normally, since the voltage drop signal ABN is at the H level, the process proceeds to step ST4 and the random number is changed. Creation processing is executed (ST32). The random number generation processing includes update processing of the winning counter RG and the big hit counter CT used in the lottery operation in the normal symbol processing ST40 and the special symbol processing ST45.

  When the random number generation process (ST32) ends, a timer subtraction process is performed for the timer that manages the time of each game operation (ST33). The timer to be subtracted here is mainly used for managing the opening time of the electric tulip and the special winning opening and other game effect times. At this time, a clear signal is supplied to a watchdog timer (not shown) to prevent the CPU from being forcibly reset.

  Subsequently, ON / OFF signals of various switches including a winning detection switch of the symbol start opening 15 and the big winning opening 16 are inputted, and the ON / OFF signals are stored in the work area (ST34). Based on the stored information, for example, when there is a winning at the symbol start opening and the information can be held, necessary information based on detection such as a command for displaying the hold is transmitted. If an unreasonable ON signal is detected, an illegal winning command is transmitted (ST35). The illegal winning command is transmitted, for example, when an ON signal is obtained from the detection switch of the special winning opening 16 even though the special game is not being performed.

  Next, error management processing is performed (ST36). The error management process is a determination as to whether or not an abnormality has occurred inside the device, such as whether or not the supply of game balls has stopped or the game balls are clogged. Next, after creating a control command for the payout control board (ST37), the control command generated in each of the above processes is transmitted to the corresponding sub-control board (ST38).

  Next, normal symbol processing is performed on the condition that the current operation mode is not the hit mode (ST40). The normal symbol processing means determination as to whether or not to operate an ordinary electric accessory such as an electric tulip. Specifically, when it is determined that the game ball has passed the gate based on the switch input result in step ST34, the winning counter RG updated in the random number generation process (ST32) is compared with the winning winning value. Done. If the comparison result is a winning state, the operation mode is changed to the winning operation mode. Further, if it is hit, a process for operating an ordinary electric accessory such as an electric tulip is performed (ST42).

  Subsequently, necessary control commands are transmitted to the corresponding sub control board (ST43), and special symbol processing is performed on the condition that the current operation mode is not a big hit (ST45). The special symbol process is a determination as to whether or not to operate a special electric accessory such as the special prize opening 16. Specifically, when it is determined from the switch input result in step ST34 that the game ball has passed the symbol start port, the big hit counter CT updated in the random number generation process (ST32) is used as the big win winning value Hit. In contrast to. Then, if the comparison result is a winning state, the operation mode is changed to the big hit mode. If it is a big hit, a process for operating a special electric accessory such as a big prize opening is performed (ST47).

  Thereafter, the control command generated in each of the above processes is transmitted to the corresponding sub-control board (ST48). For example, when the special symbol process (ST45) is executed, regardless of the lottery result, the symbol variation operation is started in the liquid crystal display DISP when the control command is transmitted. In any case, when the process of step ST48 is completed, the register saved in the process of step ST30 is restored (ST49), the EI instruction is executed, and the interrupt process is completed (ST50). As a result, normally, the routine returns from the interrupt processing routine to the infinite loop processing (ST15 in FIG. 6) of the main processing.

As described above, in this embodiment, the process at the time of power-off is executed without using an interrupt process such as NMI (non maskable interrupt). Therefore, save processing (ST53-ST
56) becomes extremely simple, and the evacuation process can be surely completed.

  In addition, since the processing time of the saving process is short, it is possible to effectively cope with an instantaneous power interruption. That is, since the delay time of the delay unit DLY1 of the power supply monitoring unit can be set extremely long, the game operation can be continued as it is without stopping the game operation if there is a certain momentary power interruption. It is sufficient that at least 4 + α time, which is the sum of the timer interruption period (= 4 mS) and the power monitoring process time (= α), can be secured. In Japan, momentary power interruptions that cannot be perceived by humans occur every day, so the configuration of this example is especially in game halls that are not equipped with UPS (Uninterrupted Power Supply). It is valid.

  Further, in this embodiment, since the NMI process is not used, there is no possibility that the stack area is used up or the work area is eroded even when the AC power supply after power recovery is unstable. In addition, since the first command to be resumed after power recovery is fixedly determined, the processing after power recovery is simplified.

  In addition, in this embodiment, after restarting the power supply, before restarting the game process, the voltage drop signal ABN is checked to confirm that the AC power supply is normal. Even if the abnormal time is repeated, the gaming operation can be resumed correctly if the power supply is stabilized thereafter.

  For example, in the present embodiment, after the process of step ST8 → ST9, the power supply monitoring process (ST31) is executed after the interrupt cycle (= 4 ms), so even if the AC power supply is shut off at the timing of step ST8. (Even if the voltage drop signal ABN is switched from the H level to the L level), the saving process (ST53 to ST56) can be executed reliably. When the AC power supply is interrupted during steps ST1 to ST7 (when the voltage drop signal ABN is switched from the H level to the L level), the value of the backup flag BFL remains 5AH. Only the same process (ST1 to ST7) is repeated later, and no problem occurs.

  By the way, the check process (ST12 to ST13) of the voltage drop signal ABN after the RAM clear process (ST10) is executed can be omitted. That is, in the present embodiment, since the power supply monitoring process (ST31) is executed at the head of the timer interrupt, even if the above check processes (ST12 to ST13) are omitted, in the subsequent interrupt permission state (see ST14), it is quick. This is because a power supply abnormality can be detected.

However, before starting the first timer interrupt processing (Timer INT), the DC power supply voltage (DC5
When V) is cut off, the save process (ST53 to ST56) is not executed, so that the original process cannot be resumed after the power is restored. However, the original process that cannot be resumed is simply a counter update process, and the problem here is that all past game information has been lost by the RAM clear process and immediately after the power is restored. Since the power supply is shut off again, there is no substantial adverse effect on the original process cannot be resumed.

  As mentioned above, although the structure and effect of the Example of this invention were demonstrated concretely, the concrete description content does not limit this invention at all, and various modifications are possible. For example, in the embodiment, normality / abnormality is determined by a single level determination of the voltage drop signal ABN, but whether the input data to the PIO unit is garbled or not is determined by multiple determinations. It is preferable to FIG. 9A shows this embodiment. When the normal level is reached N times consecutively, the process proceeds to the next process. This configuration is used in place of ST6 to ST7 and ST12 to ST13 of the system reset process. On the other hand, it is preferable to adopt the configuration shown in FIG. 9B instead of steps ST51ST52 of the power supply monitoring process. In this case, when the abnormality level is continuously N times, the process proceeds to the next process. Yes.

In the embodiment, for convenience of explanation, a jump instruction (JP XX) is provided after step ST9.
YY) is executed, but a RET instruction (return instruction) can be used instead. When the RET instruction is used, in step ST53, the SP storage area stores not the SP + 2 value but the stack pointer value SP at that time.

21 Main Control Unit 55 Voltage Monitoring Unit GM Game Machine ABN Voltage Drop Signal BU Backup Power Supply PIO Input Unit ST52 Determination Process ST55 Evacuation Process

Claims (5)

A gaming machine provided with a voltage monitoring unit that outputs a voltage drop signal when the power supply voltage drops, and a backup power supply that maintains the stored contents of the memory even after the power supply voltage is cut off,
An input unit that receives a voltage drop signal output from the voltage monitoring unit, a determination process that acquires data from the input unit every predetermined time to detect a power supply abnormality, and a power supply abnormality is detected by the determination process The subsequent game control is stopped, and the specific data set to the first level is
A save process to be stored in the M flag storage area is provided in the main control unit mainly responsible for the game control operation,
In the system reset process of the main control unit that is activated based on the restoration or input of the power supply voltage, it is confirmed that there is no power supply abnormality based on the acquired data from the input unit, and then the specific data in the flag storage area is A game machine characterized by starting processing after being interrupted after changing the setting from the first level to the second level.   2. The gaming machine according to claim 1, wherein a value of a stack pointer that specifies a start address of a data group in a stack area to be held even after power-off is stored in an address storage area of a RAM before and after the saving process. The operation of the main control unit includes a system reset process that is started based on the restoration or input of the power supply voltage, and a maskable timer interrupt process that is started at regular intervals, and uses an unmaskable interrupt process. Configured without
The gaming machine according to claim 1, wherein the save process is provided in the timer interrupt process.   The system reset process and the save process are provided with a calculation process for executing the same calculation for a specific data group in the RAM. If the calculation results do not match, the contents of the RAM are changed in the system reset process. 4. The gaming machine according to claim 3, wherein the game machine is configured to return to a fixed fixed process when the calculation results coincide with each other.   The voltage monitoring unit is configured to monitor an abnormality in the AC voltage input to the power supply circuit and an abnormality in the DC voltage output from the power supply circuit, and output a voltage drop signal based on any abnormality. The gaming machine according to claim 1.

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