JP2010074193A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2010074193A JP2010074193A JP2009298268A JP2009298268A JP2010074193A JP 2010074193 A JP2010074193 A JP 2010074193A JP 2009298268 A JP2009298268 A JP 2009298268A JP 2009298268 A JP2009298268 A JP 2009298268A JP 2010074193 A JP2010074193 A JP 2010074193A
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- Prior art keywords
- conductors
- resin package
- semiconductor device
- conductor
- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
【解決手段】半導体チップ1と、この半導体チップ1の電極に電気的に接続された複数の導体2A,2Bと、これら複数の導体2A,2Bおよび半導体チップ1を封止する樹脂パッケージ3と、を有しており、導体2A,2Bは、厚みが相違する厚肉部21a,21bと薄肉部22a,22bとを有し、かつ厚肉部21a,21bの下面部が樹脂パッケージ3の底面から露出した面実装用の端子部23a,23bとされている、半導体装置Aであって、複数の導体2A,2Bのうちの少なくとも1つの厚肉部21a,21bは、その全体または一部の幅が不均一な非矩形状に形成されている。
【選択図】 図1
Description
本願発明のその他の特徴および利点については、以下に行う発明の実施の形態の説明から、より明らかになるであろう。
1 半導体チップ
2A,2B,2B’ 導体
3 樹脂パッケージ
10a 電極
21a,21b 厚肉部
22a,22b 薄肉部
23a,23b 端子部
25a,25b 凹部
30b 底面(樹脂パッケージの)
30c,30d 第1の側面(樹脂パッケージの)
30e,30f 第2の側面(樹脂パッケージの)
Claims (4)
- 半導体チップと、この半導体チップの電極に電気的に接続された複数の導体と、これら複数の導体および半導体チップを封止する樹脂パッケージと、を有しており、
上記各導体は、厚みが相違する厚肉部と薄肉部とを有し、かつ上記厚肉部の下面部が上記樹脂パッケージの底面から露出した面実装用の端子部とされている、半導体装置であって、
上記複数の導体のうちの少なくとも1つの厚肉部は、その全体または一部の幅が不均一な非矩形状に形成されていることを特徴とする、半導体装置。 - 上記樹脂パッケージは、x方向に間隔を隔てた一対の第1の側面と、x方向に直交するy方向に間隔を隔てた一対の第2の側面とを有しているとともに、
上記複数の導体は、それらの端子部がx方向に間隔を隔てて対をなすように設けられており、かつ、
上記非矩形状に形成された厚肉部は、上記樹脂パッケージの中央寄りになるほどy方向の幅が小さくなる先細形状部を有している、請求項1に記載の半導体装置。 - 上記先細形状部は、略台形状、略三角形状、または略半円状である、請求項2に記載の半導体装置。
- 上記各導体は、上記第1の側面から露出した端部を有しており、かつこの端部には凹部が形成されている、請求項1ないし3のいずれかに記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009298268A JP5171803B2 (ja) | 2009-12-28 | 2009-12-28 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009298268A JP5171803B2 (ja) | 2009-12-28 | 2009-12-28 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006200425A Division JP4476977B2 (ja) | 2006-07-24 | 2006-07-24 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010074193A true JP2010074193A (ja) | 2010-04-02 |
JP5171803B2 JP5171803B2 (ja) | 2013-03-27 |
Family
ID=42205628
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009298268A Expired - Lifetime JP5171803B2 (ja) | 2009-12-28 | 2009-12-28 | 半導体装置 |
Country Status (1)
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JP (1) | JP5171803B2 (ja) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04137754A (ja) * | 1990-09-28 | 1992-05-12 | Sanyo Electric Co Ltd | リードフレーム |
JPH09260568A (ja) * | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH09298256A (ja) * | 1996-03-07 | 1997-11-18 | Matsushita Electron Corp | 電子部品とその製造方法及びそれに用いるリードフレームと金型 |
JPH10313082A (ja) * | 1997-03-10 | 1998-11-24 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP2001028420A (ja) * | 1999-07-14 | 2001-01-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2001077283A (ja) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
-
2009
- 2009-12-28 JP JP2009298268A patent/JP5171803B2/ja not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04137754A (ja) * | 1990-09-28 | 1992-05-12 | Sanyo Electric Co Ltd | リードフレーム |
JPH09298256A (ja) * | 1996-03-07 | 1997-11-18 | Matsushita Electron Corp | 電子部品とその製造方法及びそれに用いるリードフレームと金型 |
JPH09260568A (ja) * | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JPH10313082A (ja) * | 1997-03-10 | 1998-11-24 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP2001028420A (ja) * | 1999-07-14 | 2001-01-30 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2001077283A (ja) * | 1999-09-01 | 2001-03-23 | Matsushita Electronics Industry Corp | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 |
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JP5171803B2 (ja) | 2013-03-27 |
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