JP2010027703A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a metal layer of a VIA hole sidewall from being diffused to a semiconductor layer. <P>SOLUTION: A semiconductor device includes: a gate finger electrode 2, a source finger electrode 3 and a drain finger electrode 4 disposed on a first surface of a semi-insulating substrate 11; a ground conductor 26 disposed on a second surface on the opposite side from the first surface; a gate terminal electrode 14, a source terminal electrode 18 and a drain terminal electrode 12 formed by bundling a plurality of fingers for each of the gate finger electrode 2, source finger electrode 3 and drain finger electrode 4; an operating layer formed on the semi-insulating substrate 11 below the gate finger electrode 2, source finger electrode 3 and drain finger electrode 4; an insulating film 44 disposed on an internal wall surface of a VIA hole 30 nearby the operating layer; and a ground electrode 46 formed on the insulating layer 44 and a second surface of the semi-insulating substrate 11 and connected to the source terminal electrode 18 from the second surface side. Also there is disclosed a method of manufacturing the semiconductor device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device used in a high frequency band and a manufacturing method thereof, and more particularly, to a semiconductor device characterized by a via (VIA) hole structure in forming a ground electrode of an element which is difficult to be thinned such as GaN / SiC and a manufacturing method thereof About.

  A semiconductor device used in a high frequency band, for example, a microwave power amplifying device is composed of an active element such as a field effect transistor, a passive element such as a resistor or a capacitor, and a circuit element such as a microstrip line that transmits a high frequency signal.

  These circuit elements are formed on, for example, a semi-insulating substrate. A grounding electrode is formed on the back surface of the semi-insulating substrate. When the circuit element is grounded, for example, the circuit element provided on the semi-insulating substrate and the grounding electrode formed on the back surface of the semi-insulating substrate are electrically connected via a VIA hole penetrating the semi-insulating substrate. Connected to.

  The VIA hole has a structure in which a hole penetrating from one surface of the semi-insulating substrate to the other surface is provided, and a ground electrode is formed on the inner wall surface of the VIA hole. The VIA hole is formed by, for example, etching, and the ground electrode is formed by plating or vapor deposition. The VIA hole having the above-described configuration has already been disclosed (for example, see Patent Document 1 and Patent Document 2).

  On the other hand, a semiconductor device having a contact plug or a peer plug made of tungsten (W) and a method for manufacturing the same, and a lower layer of the barrier metal film even when the barrier metal film in the contact plug or the peer plug is thinly formed. A semiconductor device and a method for manufacturing the same that are less likely to affect the above have already been disclosed (for example, see Patent Document 3).

In Patent Document 3, a barrier metal film such as a TiN film is formed in a contact hole or a VIA hole. Thereafter, a W nucleation film is formed on the barrier metal film by a CVD method in which WF ₆ gas is reduced by B ₂ H ₆ gas. Then, a W plug is formed as a contact plug or a VIA plug on the W nucleation film by the CVD method.

  In the conventional VIA hole structure, the inner wall surface of the VIA hole is roughened, and the reaction between the metal layer disposed on the inner wall surface of the VIA hole and the semi-insulating substrate is easily promoted.

  Since the metal layer on the side wall of the VIA hole diffuses into the semiconductor layer, the generation of carriers from the ground electrode formed in the VIA hole is induced by the strong electric field region such as the drain region formed in the vicinity of the VIA hole, and the drain Leakage current is likely to increase between a strong electric field region such as a region and the ground electrode. In particular, during high-temperature operation, the electric field concentrates on the roughened portion in the VIA hole, and a short circuit is likely to occur between the strong electric field region such as the drain region and the ground electrode.

Further, when a barrier metal film is disposed on the inner wall surface of the VIA hole, an ohmic contact is made between the barrier metal film and the semi-insulating substrate due to a reaction between the disposed barrier metal film and the semi-insulating substrate. There is also a problem that the barrier height of the diode characteristic between the metal layer disposed on the barrier metal film and the semi-insulating substrate is increased.
JP-A-2-288409 JP 2001-28425 A JP 2007-194468 A

  An object of the present invention is to provide a semiconductor device that prevents the metal layer on the sidewall of the VIA hole from diffusing into the semiconductor layer and prevents the occurrence of a short circuit between the strong electric field region and the ground electrode, and a method for manufacturing the same. .

  According to one aspect of the present invention for achieving the above object, a semi-insulating substrate on a semiconductor chip, a gate finger electrode and a source disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers A finger electrode and a drain finger electrode; a ground conductor disposed on a second surface opposite to the first surface of the semi-insulating substrate; and a gate finger electrode disposed on the first surface of the semi-insulating substrate; A gate terminal electrode formed by bundling a plurality of fingers for each of the source finger electrode and the drain finger electrode, a source terminal electrode and a drain terminal electrode, and a lower part of the gate finger electrode, the source finger electrode and the drain finger electrode An operating layer formed on a semi-insulating substrate and a VIA hole near the operating layer An insulating film disposed on the inner wall surface of the VIA hole; and formed on a second surface of the insulating film and the semi-insulating substrate, and is formed on the semi-insulating substrate with respect to the source terminal electrode near the operation layer. A semiconductor device including a ground electrode connected from the second surface side is provided.

  According to another aspect of the present invention, a semi-insulating substrate on a semiconductor chip, and a gate finger electrode, a source finger electrode, and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers And a plurality of ground conductors arranged on the second surface opposite to the first surface of the semi-insulating substrate and a predetermined interval on one side of the plurality of finger electrode arrays A plurality of drain terminal electrodes arranged between the plurality of source terminal electrodes, a plurality of drain terminal electrodes arranged between the plurality of source terminal electrodes, and a plurality of fingers arranged at a predetermined interval on the other side of the plurality of finger electrode arrays. A gate terminal electrode; a VIA hole disposed in the semi-insulating substrate below the source terminal electrode; an insulating film disposed on an inner wall surface of the VIA hole; A semiconductor device is provided that includes a ground electrode formed on the second surface of the semi-insulating substrate and connected to the source terminal electrode from the second surface side of the semi-insulating substrate.

  According to another aspect of the present invention, a semi-insulating substrate on a semiconductor chip, and a gate finger electrode, a source finger electrode, and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers A ground conductor disposed on a second surface opposite to the first surface of the semi-insulating substrate, and a gate finger electrode, the source finger electrode, and the ground finger disposed on the first surface of the semi-insulating substrate. A gate terminal electrode, a source terminal electrode and a drain terminal electrode formed by bundling a plurality of fingers for each drain finger electrode, and a semi-insulating substrate below the gate finger electrode, the source finger electrode and the drain finger electrode The formed operation layer, the small-diameter VIA hole in the vicinity of the operation layer, and the ground conductor A multi-stage VIA hole comprising a large-diameter VIA hole on the side, an insulating film disposed on an inner wall surface of the multi-stage VIA hole, and an operating layer formed on the second surface of the insulating film and the semi-insulating substrate There is provided a semiconductor device including a ground electrode connected to the source terminal electrode in the vicinity from the second surface side of the semi-insulating substrate.

  According to another aspect of the present invention, a step of forming a highly perpendicular VIA hole on a semi-insulating substrate in advance using a mask layer without a taper as a mask, and an insulating film on the inner wall surface of the VIA hole, There is provided a method for manufacturing a semiconductor device, comprising a step of forming and a step of forming a ground electrode on the insulating film.

  According to another aspect of the present invention, a step of forming an inclined VIA hole with a mask layer having a taper as a mask is formed on a semi-insulating substrate, and an insulating film is formed on the inner wall surface of the VIA hole. There is provided a method for manufacturing a semiconductor device, comprising: a step of forming a ground electrode on the insulating film.

  According to another aspect of the present invention, a step of forming a mask layer made of a material having an etching rate lower than that of the semi-insulating substrate on the second surface of the semi-insulating substrate having electrodes formed on the first surface; Forming a resist layer on the mask layer; irradiating the resist layer with light through a first mask pattern provided with a light-transmitting region; and forming a first opening in the resist layer; Heating the resist layer in which the opening is formed to form a first tapered region having a thickness that decreases toward the first opening side around the first opening of the resist layer; and the first opening of the resist layer. The mask layer is etched to form a second opening in which a part of the second surface of the semi-insulating substrate is exposed, and the second opening is thickened around the second opening toward the second opening side. Forming a second taper region where the thickness is reduced A step of removing the resist layer remaining on the mask layer; etching the semi-insulating substrate using the second opening; and a portion located on the second surface side of the semi-insulating substrate Forming a VIA hole having a third taper region having a larger inner diameter width than the inner diameter width of the portion located on the first surface side, and forming an insulating film on the inner wall surface of the VIA hole There is provided a method for manufacturing a semiconductor device, comprising an eighth step and a ninth step of forming a ground electrode on the insulating film.

  According to the present invention, it is possible to provide a semiconductor device that prevents the metal layer on the side wall of the VIA hole from diffusing into the semiconductor layer and prevents the occurrence of a short circuit between the strong electric field region and the ground electrode, and a method for manufacturing the same. .

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
A schematic planar pattern configuration of the semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. 1A, and a schematic bird's-eye view in the vicinity of the VIA hole is shown in FIG. 1B. It is expressed in

  A schematic cross-sectional structure of the vertical VIA hole 30 formed in the semiconductor device according to the first embodiment is expressed as shown in FIG. A schematic cross-sectional structure of the tapered VIA hole 30 formed in the semiconductor device according to the first embodiment is expressed as shown in FIG.

  The semiconductor device according to the first embodiment is disposed on the semi-insulating substrate 11 on the semiconductor chip 10 and the first surface of the semi-insulating substrate 11 as shown in FIGS. , Gate finger electrode 2, source finger electrode 3 and drain finger electrode 4 each having a plurality of fingers, ground conductor 26 disposed on the second surface opposite to the first surface of semi-insulating substrate 11, and semi-insulating Gate terminal electrodes 14, 14-1, 14-2, 14 arranged on the first surface of the conductive substrate 11 and formed by bundling a plurality of fingers for each of the gate finger electrode 2, the source finger electrode 3 and the drain finger electrode 4. -3, 14-4, ..., source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5, ... and the drain terminal electrode 12, and the gate finger electrode 2, An operation layer formed on the semi-insulating substrate below the source finger electrode 3 and the drain finger electrode 4, and VIA holes 30, 30-1, 30-2, 30-3, 30-4, 30 in the vicinity of the operation layer. -5, ..., the insulating film 44 disposed on the inner wall surface 30a of the VIA holes 30, 30-1, 30-2, 30-3, 30-4, 30-5, ..., the insulating film 44 and the half The semi-insulating substrate 11 is formed on the second surface of the insulating substrate 11 with respect to the source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5,. And a ground electrode 46 connected from the second surface side.

  Examples of the semi-insulating substrate 11 include a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or Any of the diamond substrates can be applied.

When a SiC substrate or a GaN substrate is used as the semi-insulating substrate 11, for example, an Al ₂ O ₃ film or an HfO ₂ film can be applied as the insulating film 44.

  When a GaAs substrate is used as the semi-insulating substrate 11, any of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof can be applied as the insulating film 44.

  In the semiconductor device according to the first embodiment, the portions of the gate finger electrode 2, the source finger electrode 3, and the drain finger electrode 4 form a heat generating portion 16 as shown in FIG. In the example of FIG. 1A, the gate terminal electrodes 14, 14-1, 14-2, 14-3, 14-4 and the source terminal electrodes 18, 18-1, 18-2, 18-3 are arranged at one end. , 18-4, 18-5, and the drain terminal electrode 12 is arranged at the other end.

  In the vicinity of the surface of the semi-insulating substrate 11, an operation layer is formed on the semi-insulating substrate 11 below the gate finger electrode 2, the source finger electrode 3 and the drain finger electrode 4. The operation layer forms the heat generating portion 16.

  In the semiconductor device according to the first embodiment, the VIA hole 30 is formed in the source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, and 18-5 in the vicinity of the operation layer. .

  The gate terminal electrodes 14, 14-1, 14-2, 14-3, and 14-4 are connected to the peripheral input side matching circuit substrate 22 by bonding wires or the like, and the drain terminal electrode 12 is also bonded to the bonding wires. Etc. to be connected to the peripheral output side matching circuit board 24. Further, for the source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5,..., As shown in FIG. A VIA hole 30 is formed, and an insulating film 44 is formed on the inner wall surface 30a of the VIA hole. Further, a ground electrode 46 is formed on the insulating film 44 on the inner wall surface 30 a of the VIA hole 30.

  A ground conductor 26 is formed on the back surface of the semi-insulating substrate 11. When the circuit element is grounded, the circuit element provided on the semi-insulating substrate 11 and the ground conductor 26 formed on the back surface of the semi-insulating substrate 11 through the VIA hole 30 penetrating the semi-insulating substrate 11 Are electrically connected.

  In the semiconductor device according to the first embodiment, the grounding conductor 26 via the VIA hole 30 is, as shown in FIG. 1B, the insulating film 44 formed on the inner wall surface 30a of the conical VIA hole 30. And connected to the source terminal electrode 18 through the ground electrode 46.

  A more detailed schematic cross-sectional structure of the tapered VIA hole 30 formed in the semiconductor device according to the first embodiment is expressed as shown in FIG.

  In the structure of the VIA hole 30 of the semiconductor device according to the first embodiment, the surface of the inner wall surface 30a of the VIA hole 30 is a rough surface 45 as shown in detail in FIG. Therefore, in the structure of the VIA hole 30 of the semiconductor device according to the first embodiment, the reaction between the ground electrode 46 and the semi-insulating substrate 11 is performed by the insulating film 44 disposed on the inner wall surface 30a of the VIA hole 30. And the metal layer on the side wall of the VIA hole 30 can be prevented from diffusing into the semiconductor layer. The insulating film 44 suppresses the induction of carriers from the ground electrode 46 in the VIA hole 30 by the strong electric field region such as the drain region 42 formed in the vicinity of the VIA hole 30, and the strong electric field such as the drain region 42. An increase in leak current generated between the region and the ground electrode 46 can also be prevented. In particular, during high-temperature operation, the electric field concentrates on the rough surface 45 in the VIA hole 30, and the short-circuit state between the strong electric field region such as the drain region 42 and the ground electrode 46 is also suppressed and stable. High temperature operation is realized.

  Further, when the barrier metal film is disposed by disposing the insulating film 44 on the inner wall surface 30 a of the VIA hole 30, the barrier metal film is reacted by the reaction between the disposed barrier metal film and the semi-insulating substrate 11. The formation of an ohmic contact between the film and the semi-insulating substrate 11 is also prevented, and the diode characteristic barrier height between the metal layer disposed on the barrier metal film and the semi-insulating substrate 11 is increased. The point can also be eliminated.

(VIA hole formation process)
A schematic cross-sectional structure for explaining in detail the process of forming the VIA hole 30 applied in a part of the method for manufacturing the semiconductor device according to the first embodiment is expressed as shown in FIG. 5A is a photolithography process diagram, FIG. 5B is a process diagram for forming the first opening 34a, FIG. 5C is a process diagram for forming the first tapered region 34b, and FIG. 5D. FIG. 5E is a process diagram for forming the third opening 31c by etching the semi-insulating substrate 31 using the mask layer 33. FIG. 5F is a process diagram for forming the third opening 31c. A process diagram for forming the VIA hole by forming the insulating film 44, the ground electrode 46, and the ground conductor 26 is shown.

  A formation process of the VIA hole 30 applied in a part of the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to the process diagram of FIG.

(A) First, as shown in FIG. 5A, an electrode 32 having a certain area is formed on the first surface 31 a of the semi-insulating substrate 31, for example, the surface of the semi-insulating substrate 31. The semi-insulating substrate 31 is, for example, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond Any of the substrates can be applied. The electrode 32 is made of Ni or the like. For example, a source terminal electrode of a circuit element (not shown) formed on the first surface 31 a of the semi-insulating substrate 31 is connected to the electrode 32.

  On the second surface 31 b of the semi-insulating substrate 31, for example, the back surface of the semi-insulating substrate 31, a mask layer 33 made of a metal such as Al is formed. As the metal for forming the mask layer 33, a metal having a characteristic that the etching rate by the etching gas used when dry etching the semi-insulating substrate 31 is smaller than that of the semi-insulating substrate 31 is used. . A resist layer 34 is formed on the mask layer 33.

  A mask pattern 35 is disposed above the semi-insulating substrate 31 on which the mask layer 33 and the resist layer 34 are formed. A part of the mask pattern 35 is formed with, for example, a through hole 35a that transmits light. The mask pattern 35 is arranged so that the through hole 35a and the electrode 32 face each other. A light source 36 is arranged above the mask pattern 35, for example, on the opposite side of the semi-insulating substrate 31 with respect to the mask pattern 35.

(B) Next, as shown in FIG. 5 (b), the resist layer 34 is irradiated with light from the light source 36 through the mask pattern 35, and thereafter development processing is performed. The first opening 34a is formed at the facing position. At this time, the mask layer 33 is exposed at the bottom of the first opening 34a. Note that the area of the first opening 34 a is smaller than the area of the electrode 32. Here, a case of a positive resist is described. However, a negative resist can also be used.

(C) Next, as shown in FIG. 5C, the resist layer 34 is heated. By this heating, a convex portion at the upper edge of the edge surrounding the first opening 34a is formed, and a first taper region 34b whose thickness decreases toward the first opening 34a is formed, for example, in an annular shape around the first opening 34a. Is done.

(D) Next, as shown in FIG. 5D, the mask layer 33 is etched using the first openings 34 a of the resist layer 34. Etching is performed by dry etching using, for example, Ar gas or a halogen-based gas such as F or Cl. By this etching, the second opening 33a is formed in the mask layer 33, and the second front surface (back surface) 31b of the semi-insulating substrate 31 is exposed at the bottom of the second opening 33a.

  When the mask layer 33 is etched, the resist layer 34 functioning as a mask has a first tapered region 34b around the first opening 34a (see FIG. 5C). Therefore, when the mask layer 33 is etched, the first taper region 34b is also etched in order from the thin inner side near the first opening 34a to the outer side as time passes, and the diameter of the first opening 34a gradually increases. Expand to.

  Therefore, in the etching of the mask layer 33, the portion exposed to the bottom of the first opening 34a is first etched. Thereafter, as the diameter of the first opening 34a of the resist layer 34 increases, the mask layer 33 is gradually etched from the inside to the outside, and the diameter of the second opening 33a gradually increases. At this time, etching proceeds more inside the mask layer 33 than outside. Accordingly, the second tapered region 33b whose thickness gradually decreases toward the second opening 33a, for example, is formed around the second opening 33a, for example, in an annular shape.

(E) Next, as shown in FIG. 5E, the resist layer 34 is removed, and then the semi-insulating substrate 31 is etched using the mask layer 33. The semi-insulating substrate 31 is etched by dry etching using, for example, Ar gas or a halogen-based gas such as F or Cl.

(F) The etching of the semi-insulating substrate 31 starts first in a portion surrounded by a dotted line d6 perpendicular to the surface exposed to the bottom of the second opening 33a, for example, the surface of the semi-insulating substrate 31. Thereafter, as shown in FIG. 5F, a third opening (VIA hole) 31c penetrating the semi-insulating substrate 31 is formed by the progress of etching.

  At this time, similarly to the case of the resist layer 34 described with reference to FIG. 5D, the etching proceeds in order from the thin inner side to the thick outer side also in the second tapered region 33b of the mask layer 33, and the second opening 33a. The caliber is enlarged. Therefore, in the semi-insulating substrate 31, as the diameter of the second opening 33a increases, the width of the inner diameter of the third opening 31c, for example, in the upper part of the drawing is gradually increased in parallel with the formation of the third opening 31c. Become. In this case, for example, a portion of the third opening 31c located on the upper side in the figure, for example, on the other second surface 31b side, advances the etching faster. For this reason, as shown by a dotted line d5, for example, the inner diameter width W5 of the opening opened in the second surface 31b of the semi-insulating substrate 31 is larger than the inner diameter of the opening opened in the first surface 31a of the semi-insulating substrate 31. It becomes larger than the width W6.

  Accordingly, for example, a third opening 31c having a third tapered region 31d with a gradually decreasing inner diameter width is formed from the second surface 31b of the semi-insulating substrate 31 toward the first surface 31a of the semi-insulating substrate 31. The

Next, as shown in FIG. 5F, the mask layer 33 is removed, and an insulating film 44 is formed on the inner wall surface of the VIA hole 30 in the third tapered region 31d of the third opening 31c. When a SiC substrate or a GaN substrate is used as the semi-insulating substrate 11, for example, an Al ₂ O ₃ film or an HfO ₂ film can be applied as the insulating film 44. In this case, a SiC substrate or a GaN substrate is used as the semi-insulating substrate 11. In addition, as the insulating film 44, any of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof can be applied. In this case, a GaAs substrate is used as the semi-insulating substrate 11.

  Thereafter, the insulating film 44 in the third opening 31c and the ground electrode 46 made of a metal such as Au are formed on the back surface of the electrode 32 facing the third opening 31c by a method such as vapor deposition or electroless plating. The ground conductor 26 is formed on the second surface 31b of the substrate 31, and the VIA hole 30 is completed.

  At this time, the electrode 32 has a shape in which the opening of the hole constituting the VIA hole 30 is closed, for example.

  With respect to the VIA hole forming step applied in a part of the method of manufacturing the semiconductor device according to the first embodiment, the third opening 31c is entirely in the depth direction as shown by a dotted line d5 in FIG. Is the third taper region 31d.

  In order to reliably form the ground electrode 46, it is desirable that the entire depth direction is a tapered region. However, a tapered region may be provided only in a part of the third opening 31c, for example, a partial region above the third opening 31c continuous from the second surface 31b of the semi-insulating substrate 31. In this case, although the effect is small as compared with the case where the whole is a tapered region, the effect of reliably forming the ground electrode 46 via the insulating film 44 can be obtained.

  Further, when the ground electrode 46 is formed on the inner surface of the third opening 31c via the insulating film 44, the mask layer 33 is removed. However, the ground electrode 37 can be formed on the mask layer 33 without removing the mask layer 33.

(Configuration of etching equipment)
In the manufacturing method of the semiconductor device according to the first embodiment, a schematic configuration of an etching apparatus applied to the process of forming the VIA hole 30 on the semi-insulating substrate 31 is expressed as shown in FIG.

  A cathode 122 is disposed, for example, below the chamber 121. An anode 123 is disposed above the cathode 122 at a position facing the cathode 122. For example, a high frequency power source 124 is connected to the anode 123, and the cathode 122 is grounded.

  A semi-insulating substrate 31 for performing etching is mounted on the cathode 122, for example. A supply port 125 for supplying an etching gas such as Ar gas or a gas containing a halogen element such as F or Cl is provided above the chamber 121. A discharge port 126 for discharging the gas in the chamber 121 is provided below the chamber 121.

  With the above configuration, an etching gas is sent from the supply port 125 into the chamber 121. The etching gas is excited by a high frequency generated by the high frequency power supply 124, and the semi-insulating substrate 31 is etched by the action of, for example, accelerated ions.

  According to the configuration of the VIA hole 30 formed by the process of forming the VIA hole 30 described above, the tapered region is provided on the inner surface of the VIA hole 30 of the semi-insulating substrate 31. In this case, one opening of the VIA hole 30 becomes large, and the inclination of the inner surface of the VIA hole 30 receives the metal forming the ground electrode 46. Therefore, when the ground electrode 46 is formed by a method such as vapor deposition or electroless plating, the ground electrode 46 is reliably formed, and disconnection is prevented.

  Further, when a GaN substrate, SiC substrate, sapphire substrate, diamond substrate or the like is used as the semi-insulating substrate 31, these substances have poor reactivity when etching to form the VIA hole 30, and the VIA hole 30. It is difficult to form a tapered region on the inner surface of the substrate.

  For example, since SiC is difficult to chemically etch, it becomes physical etching with strong sputter properties such as dry etching. Therefore, when forming a VIA hole, it is difficult to form a tapered region, and a vertical VIA hole tends to be formed.

  However, if a masked mask layer made of Al or the like is used, a tapered region can be easily formed on the inner surface of the VIA hole 30 even on a GaN substrate or an SiC substrate, and the VIA hole 30 without any step is obtained. .

  Further, even if one opening of the hole forming the VIA hole 30 is large, the opening on the electrode 32 side is small. Therefore, it is not necessary to increase the size of the electrode 32, and the circuit can be prevented from being enlarged.

  According to the first embodiment of the present invention, a semiconductor device that prevents the metal layer on the side wall of the VIA hole from diffusing into the semiconductor layer and prevents the occurrence of a short circuit between the strong electric field region and the ground electrode, and its manufacture A method can be provided.

[Second Embodiment]
A schematic planar pattern configuration of the semiconductor device according to the second embodiment is expressed as shown in FIG. Also, a schematic bird's-eye view of the semiconductor device according to the second embodiment is expressed as shown in FIG.

  The semiconductor device according to the second embodiment is arranged on a semi-insulating substrate 11 on a semiconductor chip 10 and a first surface of the semi-insulating substrate 11 as shown in FIGS. Gate finger electrode 2 having fingers, source finger electrode 3 and drain finger electrode 4, ground conductor 26 disposed on the second surface opposite to the first surface of semi-insulating substrate 11, and a plurality of finger electrode arrays , And a plurality of source terminal electrodes 18, 18-1, 18-2,... Arranged at a predetermined interval on one side of the plurality of source terminal electrodes 18, 18-1, 18-2,. And a plurality of gate terminals arranged at a predetermined interval on the other side of the plurality of finger electrode arrays. Electrodes 14, 14-1, 14-2, 1 4-3, 14-4,... And VIA holes 30, 30-1, 30-2,... Disposed in the semi-insulating substrate 11 below the source terminal electrodes 18, 18-1, 18-2,. Are formed on the inner surfaces of the VIA holes 30, 30-1, 30-2,..., The second surface of the insulating film 44 and the semi-insulating substrate 11, and the source terminal electrodes 18, .., And ground electrode 46 connected from the second surface side of the semi-insulating substrate 11.

  Further, as shown in FIGS. 7 and 8, the semiconductor device according to the second embodiment has a predetermined number of source finger electrodes 3 on a plurality of source terminal electrodes 18, 18-1, 18-2,. Electrode electrode lines (LS, NS, M), and a plurality of drain terminal electrodes 12, 12-1, 12-2,... ND, P) and a plurality of gate terminal electrodes 14, 14-1, 14-2, 14-3, 14-4,..., And a gate electrode wiring LG that connects a predetermined number of gate finger electrodes 2. .

  Further, the source electrode wiring (LS, NS, M) and the drain electrode wiring (LD, ND, P) have an overlay or air bridge wiring portion 15 in which one crosses over the other.

  The semi-insulating substrate 11 is a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond substrate. Either may be applied.

When a SiC substrate or a GaN substrate is applied as the semi-insulating substrate 11, the insulating film 44 can be an Al ₂ O ₃ film or an HfO ₂ film.

  When a GaAs substrate is applied as the semi-insulating substrate 11, any one of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof can be applied as the insulating film 44.

  7 and 8, the gate terminal electrodes 14-1, 14-2, 14-3, 14-4,... Arranged adjacent to each other on the semiconductor chip 10 are arranged adjacent to each other. The input side matching circuit board 22, the wire 9 connecting the output terminal 22-1 on the input side matching circuit board 22 and the gate terminal electrode 14, and a plurality of source terminal electrodes 18 arranged on the semiconductor chip 10. And an output side matching circuit board 24 disposed adjacent to the array side of the plurality of drain terminal electrodes 12, a wire 7 connecting the input terminal 24-1 on the output side matching circuit board 24 and the drain terminal electrode 12, A plurality of VIA holes 30 penetrating the semiconductor chip 10 and connected to the plurality of source terminal electrodes 18-1, 18-2,..., The semiconductor chip 10, the input side matching circuit substrate 22, and the output side matching circuit substrate 4 are arranged in common on the back surface of the ground conductor 26 and connected to the plurality of source terminal electrodes 18-1, 18-2,... Via the plurality of VIA holes 30-1, 30-2,. Prepare.

  In the semiconductor device according to the second embodiment, as shown in FIGS. 7 and 8, the source terminal electrodes 18-1, 18-2,... Are connected to the source terminal electrodes 18-1, 18-2,. .. Are connected to the ground conductor 26 via the VIA holes 30-1, 30-2,... Formed in the lower semiconductor chip 10.

  In the semiconductor device according to the second embodiment, the positions of the source terminal electrodes 18-1, 18-2,... Are located at the positions of the drain terminal electrodes 12 in the semiconductor device according to the first embodiment shown in FIG. Since the VIA holes 30-1, 30-2,... Are formed in the source terminal electrodes 18-1, 18-2,..., The strong electric field region such as the drain region 42 is in the vicinity of the VIA hole 30. The structure is formed. For this reason, in the semiconductor device according to the second embodiment, the insulating film 44 is disposed on the inner wall surface 30a of the VIA hole 30, and the ground electrode 46 is formed on the insulating film 44. The effect based on it appears more prominently than in the first embodiment.

  A more detailed schematic cross-sectional structure of the tapered VIA hole 30 formed in the semiconductor device according to the second embodiment is expressed similarly to FIG.

  In the structure of the VIA hole 30 of the semiconductor device according to the second embodiment, the surface of the inner wall surface 30a of the VIA hole 30 is a rough surface 45 as shown in detail in FIG. Therefore, in the structure of the VIA hole 30 of the semiconductor device according to the second embodiment, the reaction between the ground electrode 46 and the semi-insulating substrate 11 is performed by the insulating film 44 disposed on the inner wall surface 30a of the VIA hole 30. And the metal layer on the side wall of the VIA hole 30 can be prevented from diffusing into the semiconductor layer. The insulating film 44 suppresses the induction of carriers from the ground electrode 46 in the VIA hole 30 by the strong electric field region such as the drain region 42 formed in the vicinity of the VIA hole 30, and the strong electric field such as the drain region 42. An increase in leak current generated between the region and the ground electrode 46 can also be prevented. In particular, during high-temperature operation, the electric field concentrates on the rough surface 45 in the VIA hole 30, and the short-circuit state between the strong electric field region such as the drain region 42 and the ground electrode 46 is also suppressed and stable. High temperature operation is realized.

  Further, when the barrier metal film is disposed by disposing the insulating film 44 on the inner wall surface 30 a of the VIA hole 30, the barrier metal film is reacted by the reaction between the disposed barrier metal film and the semi-insulating substrate 11. The formation of an ohmic contact between the film and the semi-insulating substrate 11 is also prevented, and the diode characteristic barrier height between the metal layer disposed on the barrier metal film and the semi-insulating substrate 11 is increased. The point can also be eliminated.

  Other configurations are the same as those in FIGS. The manufacturing method is also the same as that in the first embodiment.

  In the semiconductor device according to the second embodiment, the positions of the source terminal electrodes 18-1, 18-2,... Are located at the positions of the drain terminal electrodes 12 in the semiconductor device according to the first embodiment shown in FIG. Since the VIA holes 30-1, 30-2,... Are formed in the source terminal electrodes 18-1, 18-2,..., The gate terminal electrodes 14-1, 14-2, 14-3 are replaced. , 14-4,... And the gate finger electrode 2 can be shortened.

  In addition, since the gate finger electrode 2 is not overlaid with the other source finger electrodes 3 and drain finger electrodes 4, the stray capacitance of the gate finger electrode 2 can be reduced, so that the influence on the frequency characteristics of the FET can be reduced.

  According to the second embodiment of the present invention, since the wire length for connecting the gate terminal electrode and the input matching circuit can be short, a semiconductor device with low input inductance can be provided.

  According to the second embodiment of the present invention, the semiconductor layer prevents the metal layer on the side wall of the VIA hole from diffusing into the semiconductor layer and prevents the occurrence of a short circuit between the strong electric field region such as the drain region and the ground electrode. An apparatus and a manufacturing method thereof can be provided.

[Third embodiment]
The planar pattern configuration of the semiconductor device according to the third embodiment is expressed as shown in FIG. 9A, and is schematically in the vicinity of a multistage VIA hole including a small-diameter VIA hole 30 and a large-diameter VIA hole 20. The bird's eye view is represented as shown in FIG.

  A three-dimensional schematic configuration of a multistage VIA hole including a small diameter VIA hole 30 and a large diameter VIA hole 20 formed in the semiconductor device according to the third embodiment is expressed as shown in FIG.

  The configuration of the semiconductor device according to the semi-third embodiment includes a semi-insulating substrate 11 on the semiconductor chip 10 and a first surface of the semi-insulating substrate 11 as shown in FIGS. A gate finger electrode 2, a source finger electrode 3 and a drain finger electrode 4 each having a plurality of fingers, and a ground conductor 26 disposed on a second surface opposite to the first surface of the semi-insulating substrate 11 The gate terminal electrodes 14, 14-1, 14-arranged on the first surface of the semi-insulating substrate 11 and formed by bundling a plurality of fingers for each of the gate finger electrode 2, the source finger electrode 3 and the drain finger electrode 4. 2, 14-3, 14-4,..., Source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5,. An operation layer formed on the semi-insulating substrate 11 below the electrode 2, the source finger electrode 3 and the drain finger electrode 4, a small-diameter VIA hole 30 near the operation layer, and a large-diameter VIA hole near the ground conductor 26. 20 formed on the second surface of the insulating film 44 and the semi-insulating substrate 11 on the inner wall surface (20b, 30a) of the multi-stage VIA hole, the insulating film 44 and the semi-insulating substrate 11 , And ground electrode 46 connected from the second surface side of the semi-insulating substrate 11 to the source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5,. .

  The semi-insulating substrate 11 is a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond substrate. Either can be formed.

When a SiC substrate or a GaN substrate is used as the semi-insulating substrate 11, an Al ₂ O ₃ film or an HfO ₂ film can be applied as the insulating film 44.

  When a semi-insulating substrate is 11 and a GaAs substrate is used, any of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof can be applied as the insulating film 44.

  In the semiconductor device according to the third embodiment, as shown in FIGS. 9 to 11, the center of the large-diameter VIA hole 20 is closer to the peripheral direction of the semiconductor chip 10 than the center of the small-diameter VIA hole 30. Is eccentric.

  Further, a schematic cross-sectional structure of a multistage VIA hole formed of a small-diameter VIA hole 30 and a large-diameter VIA hole 20 formed in the semiconductor device according to the third embodiment is as shown in FIGS. A semi-insulating substrate 11 having a source terminal electrode 18 formed on the first surface and a multi-stage VIA hole formed of a VIA hole 30 and a VIA hole 20 penetrating the second surface opposite to the first surface; An insulating film 44 formed on the inner wall surfaces 30a and 20b of the multistage VIA hole including the VIA hole 30 and the VIA hole 20, and a ground electrode 46 formed on the insulating film 44 and electrically connected to the source terminal electrode 18; The VIA hole 30 has a tapered region in which the inner diameter width W1 of the portion located on the second surface side is larger than the inner diameter width W0 of the portion located on the first surface side. In both cases, the VIA hole 20 has a tapered region in which the inner diameter width W2 of the portion located on the second surface side is larger than the inner diameter width of the portion located on the first surface side.

  As shown in FIGS. 9A and 9B, the gate terminal electrodes 14, 14-1, 14-2, 14-3, 14-4,... Further, the drain terminal electrode 12 is also connected to the peripheral output side matching circuit board 24 by a bonding wire or the like. For the source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5,..., As shown in FIGS. And a ground conductor 26 is formed on the back surface of the semi-insulating substrate 11. And when grounding a circuit element, via the multi-stage VIA hole (refer FIG. 10) which consists of the VIA hole 30 which penetrates the semi-insulating board | substrate 11, and the VIA hole 20 formed to the middle of the semi-insulating board | substrate 11. The circuit element provided on the semi-insulating substrate 11 and the ground conductor 26 formed on the back surface of the semi-insulating substrate 11 are electrically connected.

  In the structure of the VIA hole (20, 30) of the semiconductor device according to the third embodiment, the inner wall surface of the VIA hole (20, 30) is rough as in FIG. Therefore, also in the structure of the VIA hole (20, 30) of the semiconductor device according to the third embodiment, the insulating film 44 disposed on the inner wall surface (20b, 30a) of the VIA hole (20, 30) The reaction between the ground electrode 46 and the semi-insulating substrate 11 is prevented, and the metal layer on the side wall of the VIA hole (20, 30) is prevented from diffusing into the semiconductor layer. The insulating film 44 suppresses the induction of carriers from the ground electrode 46 in the VIA hole (20, 30) by a strong electric field region such as a drain region formed in the vicinity of the VIA hole (20, 30). An increase in leakage current generated between the strong electric field region such as the drain region and the ground electrode 46 can also be prevented. In particular, during high temperature operation, the electric field concentrates on the rough surface portion in the VIA hole (20, 30), and the short-circuit state between the strong electric field region such as the drain region and the ground electrode 46 is easily suppressed. The point which implement | achieves stable high temperature operation is the same as that of the 1st-2nd embodiment.

  Further, when the barrier metal film is arranged by arranging the insulating film 44 on the inner wall surface (20b, 30a) of the VIA hole (20, 30), the arranged barrier metal film and the semi-insulating substrate are arranged. 11 prevents the formation of an ohmic contact between the barrier metal film and the semi-insulating substrate 11, and the diode characteristic between the metal layer disposed on the barrier metal film and the semi-insulating substrate 11 is reduced. The problem of an increased barrier height can also be solved.

  In the configuration of the multistage VIA hole in the semiconductor device according to the third embodiment, the ground conductor 26 via the multistage VIA hole is formed in a conical one-stage VIA hole 30 as shown in FIGS. Further, a VIA hole 20 is further formed and grounded via a ground electrode 46 on an insulating film 44 formed on the inner wall surface 20b of the VIA hole 20 and the inner wall surface 30a of the VIA hole 30.

  With such a structure, the VIA hole 30 is further miniaturized as the source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18-5,. By combining the VIA hole 20 and the multistage configuration, a contact electrode that suppresses the generation of parasitic inductance can be formed even in the semiconductor chip of the thick semi-insulating substrate 11.

  In a GaN HEMT (High Electron Mobility Transistor) using SiC which is difficult to be thinned, the length of the VIA hole 30 reaches 100 μm, but the configuration of the multistage VIA hole in the semiconductor device according to the third embodiment. By applying, it is possible to form a ground electrode in which the generation of parasitic inductance is suppressed.

  Further, in the configuration of the multistage VIA hole in the semiconductor device according to the third embodiment, as shown in FIGS. 9A and 9B, the VIA hole 30 near the operation layer and the VIA near the ground conductor 26 are provided. In a multistage VIA hall comprising holes 20, 20-1, 20-2, 20-3, 20-4, 20-5,..., VIA holes 20, 20-1, 20-2, 20-3, 20- 4, 20-5,... Are eccentric from the center of the VIA hole 30 toward the periphery of the semiconductor chip 10.

  If the VIA holes 20, 20-1, 20-2, 20-3, 20-4, 20-5,... On the other hand, with such a configuration, thermal conductivity can be ensured without hindering thermal diffusion directly under the heat generating portion 16.

(Multistage VIA hole formation process 1)
In the method of manufacturing a semiconductor device according to the third embodiment, in the step of forming the VIA hole 30, before forming the ground electrode 46, the VIA hole 20 having a larger diameter is further formed to form a multistage VIA hole. Thereafter, an insulating film 44 and a ground electrode 46 are formed (see, for example, FIG. 12C).

  In the multi-stage VIA hole forming process applied to the semiconductor device manufacturing method according to the third embodiment, the small-diameter VIA hole 30 forming process is expressed as shown in FIG. The formation process of the VIA hole 20 is expressed as shown in FIG. 12B, and the formation process of the insulating film 44 and the ground electrode 46 is expressed as shown in FIG.

(A) First, as shown in FIG. 12A, after forming the electrode 32 on the first surface of the semi-insulating substrate 11, the VIA hole 30 is formed by the process of forming the small-diameter VIA hole 30 described above. To do. By using the above-described tapered mask layer made of Al or the like, a tapered region can be easily formed on the inner surface of the VIA hole 30 even on the semi-insulating substrate 11 made of a GaN substrate or SiC substrate. Further, the width W1 of one opening of the hole forming the VIA hole 30 is large, and the width W0 of the opening on the electrode 32 side is small. Therefore, it is not necessary to increase the size of the electrode 32, and an increase in the size of the circuit is prevented.

(B) Next, as shown in FIG. 12B, a large-diameter VIA hole 20 is formed by the same process as the VIA hole 30 formation process. The difference from the step of forming the VIA hole 30 is that the mask pattern 35 (FIG. 5A) is formed wider. By using the above-described tapered mask layer made of Al or the like, a tapered region can be easily formed on the inner surface of the large-diameter VIA hole 20 even on the semi-insulating substrate 11 made of a GaN substrate or SiC substrate. . The width W2 of one opening of the hole forming the large diameter VIA hole 20 is large, and the width of the opening on the electrode 32 side is larger than W0. By controlling the etching time, it is possible to leave only the depth D1 of the small diameter VIA hole 30 and set the depth of the large diameter VIA hole 20 to D2.

(C) Next, as shown in FIG. 12C, the insulating film 44 is formed on the inner wall surface 20b of the large diameter VIA hole 20 and the inner wall surface 30a of the small diameter VIA hole 30 by a method such as sputtering or CVD. Form.

(D) Next, as shown in FIG. 12C, a metal such as Au is formed on the second surface (back surface) of the semi-insulating substrate 11 and the insulating film 44 by a method such as vapor deposition or electroless plating. A ground electrode 46 is formed to complete a multistage VIA hole.

  At this time, the electrode 32 has a shape in which the opening of the hole constituting the VIA hole 30 is closed, for example.

  In order to reliably form the insulating film 44 and the ground electrode 46, it is desirable that the entire depth direction of the multistage VIA hole including the small diameter VIA hole 30 and the large diameter VIA hole 20 is a tapered region. .

  According to the method of manufacturing a semiconductor device according to the third embodiment to which the above-described multi-stage VIA hole forming step 1 is applied, as shown in FIG. The source terminal electrodes 18, 18-1, 18-2, 18-3, 18-connected to the ground electrode 46 by increasing the diameter in the vicinity of the ground conductor 26. The inductance of 4,18-5 can be suppressed.

  Furthermore, as shown in FIGS. 9 to 11, by decentering the large-diameter VIA hole 20 to the outside of the semiconductor chip 10, the cavity due to the VIA hole (20, 30) is not expanded just below the heat generation area, The efficiency of heat dissipation can be improved.

  Furthermore, as shown in FIG. 12 (c), the entire depth direction of the multi-stage VIA hole composed of the small-diameter VIA hole 30 and the large-diameter VIA hole 20 is a taper region. Etc. can be prevented.

(Multistage VIA hole formation process 2)
Another process of the multistage VIA hole forming process applied to the semiconductor device manufacturing method according to the third embodiment is expressed as shown in FIG. That is, the process of forming the groove having the depth D1 to be the small-diameter VIA hole 30 is represented as shown in FIG. 13A, and the process of forming the large-diameter VIA hole 20 is as shown in FIG. 13B. The formation process of the ground electrode 46 is expressed as shown in FIG.

(A) First, as shown in FIG. 13A, a groove having a width W7 and a depth D1 is formed on the first surface of the semi-insulating substrate 11 by a dry etching process. Further, the insulating film 43 and the electrode 32 are formed. In this step, the etching apparatus shown in FIG. 6 can be applied.

(B) Next, as shown in FIG. 13B, the large-diameter VIA hole 20 is formed by the same process as the small-diameter VIA hole forming process described in FIG. The difference from the small diameter VIA hole forming step is that the mask pattern 35 (FIG. 5A) is formed wider. By using a tapered mask layer made of Al or the like, a tapered region can be easily formed on the inner surface of the large-diameter VIA hole 20 even for the semi-insulating substrate 11 made of a GaN substrate or SiC substrate. Further, the width W4 of one opening of the hole forming the large-diameter VIA hole 20 is large, and the width of the opening on the electrode 32 side is larger than W7. By controlling the etching time, only the depth D1 remains in the vicinity of the first surface of the semi-insulating substrate 11, and the depth of the large diameter VIA hole 20 can be set to D2. As a result, as shown in FIG. 13B, the bottom of the electrode 32 is etched by the step of forming the large-diameter VIA hole 20, and an opening having a width W3 is formed. As a result, a small diameter VIA hole having a depth D1 is formed by the opening hole forming the width W3. At this time, the electrode 32 is configured to cover the inner wall of the opening hole forming the width W3.

(C) Next, as shown in FIG. 13C, an insulating film 44 is formed on the inner wall surface of the VIA hole 20. When a SiC substrate or a GaN substrate is used as the semi-insulating substrate 11, for example, an Al ₂ O ₃ film or an HfO ₂ film can be applied as the insulating film 44. In this case, a SiC substrate or a GaN substrate is used as the semi-insulating substrate 11. In addition, as the insulating film 44, any of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof can be applied. In this case, a GaAs substrate is used as the semi-insulating substrate 11.

  Thereafter, as shown in FIG. 13C, a ground electrode 46 made of a metal such as Au is formed on the insulating film 44 of the large-diameter VIA hole 20 by a method such as vapor deposition or electroless plating. A ground conductor 26 made of a metal such as Au is formed on the second surface (back surface) of the insulating substrate 11 to complete a multistage VIA hole.

  At this time, the electrode 32 covering the inner wall of the opening hole constituting the width W3 is connected to the ground electrode 46.

  In order to reliably form the ground electrode 46, the entire depth direction of the multi-stage VIA hole including the small-diameter VIA hole 30 having the opening of the depth D1 and the width W3 and the large-diameter VIA hole 20 is a tapered region. It is desirable that

  According to the semiconductor device manufacturing method according to the third embodiment to which the above-described multi-stage VIA hole forming step 2 is applied, a small-diameter VIA hole 30 is formed in the vicinity of the operation layer as shown in FIG. The source terminal electrodes 18, 18-1, 18-2, 18-3, 18-4, 18 connected to the ground electrode 46 by connecting the surface electrode 32 with a fine area and increasing the diameter near the ground. -5 inductance can be suppressed.

  Furthermore, as shown in FIGS. 9 to 11, the large-diameter VIA hole 20 is eccentric to the outside of the semiconductor chip, thereby improving the efficiency of heat dissipation without expanding the cavity due to the VIA hole immediately below the heat generation region. be able to.

  Further, as shown in FIG. 13 (c), since the entire depth direction of the multistage VIA hole composed of the large diameter VIA hole 20 in contact with the small diameter VIA hole 30 at the bottom is a tapered region, Step breakage can be prevented.

  According to the semiconductor device and the manufacturing method thereof according to the third embodiment, a small-diameter VIA hole is used in the vicinity of the operation layer to connect with the surface electrode in a fine area, and in the vicinity of the ground, the diameter is increased to increase the grounding. The inductance of the source terminal electrode connected to the working electrode can be suppressed.

  Further, according to the semiconductor device and the manufacturing method thereof according to the third embodiment, the large-diameter VIA hole is not expanded just below the heat generating region by decentering the large-diameter VIA hole to the outside of the semiconductor chip. Thus, the efficiency of heat dissipation can be improved.

  Furthermore, according to the semiconductor device and the manufacturing method thereof according to the third embodiment, the taper region in which the inner diameter varies is formed on the inner wall surface of the multistage VIA hole including the small-diameter VIA hole and the large-diameter VIA hole. Thus, the conductive layer is surely formed on the inner wall surface of the VIA hole, and a VIA hole without disconnection can be formed.

  According to the third embodiment of the present invention, the semiconductor layer prevents the metal layer on the side wall of the VIA hole from diffusing into the semiconductor layer and prevents the occurrence of a short circuit between the strong electric field region such as the drain region and the ground electrode. An apparatus and a manufacturing method thereof can be provided.

[Other embodiments]
As described above, the present invention has been described according to the first to third embodiments. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. should not do. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  Needless to say, the amplifying elements are not limited to FETs and HEMTs, but can be applied to other amplifying elements such as LDMOS (Lateral Doped Metal-Oxide-Semiconductor Field Effect Transistor) and HBT (Hetero-junction Bipolar Transistor).

  As described above, the present invention includes various embodiments not described herein.

  The semiconductor device and the manufacturing method thereof according to the present invention are applied to a semiconductor device that is difficult to be thinned, such as a SiC substrate or a GaN wafer substrate. It has a wide range of application fields such as amplifiers and millimeter wave power amplifiers.

1A is a schematic configuration of a semiconductor device according to a first embodiment of the present invention, and FIG. 1A is a schematic plan pattern configuration diagram, and FIG. 2B is a schematic bird's-eye view near a VIA hole. 1 is a schematic cross-sectional structure diagram of a vertical VIA hole 30 formed in a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a schematic cross-sectional structure diagram of a tapered VIA hole 30 formed in the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a more detailed schematic cross-sectional structure diagram of a tapered VIA hole 30 formed in the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional structure diagram for explaining in detail a VIA hole forming process applied in a part of the method of manufacturing a semiconductor device according to the first embodiment of the present invention, wherein (a) a photolithography process diagram; (B) Forming process of first opening 34a, (c) Forming process of first tapered region 34b, (d) Etching process of mask layer 33, (e) Semi-insulating substrate using mask layer 33 31 is a process diagram for forming a third opening 31c by etching 31, and (f) a process diagram for forming a VIA hole by forming an insulating film 44, a ground electrode 46, and a ground conductor 26. FIG. FIG. 2 shows a schematic configuration diagram of an etching apparatus applied to a VIA hole forming process for a semi-insulating substrate in the method for manufacturing a semiconductor device according to the first embodiment of the present invention. The typical plane pattern block diagram of the semiconductor device which concerns on the 2nd Embodiment of this invention. The typical bird's-eye view in the VIA hole 30 vicinity of the semiconductor device which concerns on the 2nd Embodiment of this invention. 4A and 4B are schematic configurations of a semiconductor device according to a third embodiment of the present invention, where FIG. 5A is a plan pattern configuration diagram, and FIG. 5B is a schematic bird's-eye view in the vicinity of a VIA hole 20 and a VIA hole 30. FIG. 5 is a three-dimensional schematic configuration diagram of a multistage VIA hole including a large-diameter VIA hole 20 and a small-diameter VIA hole 30 formed in a semiconductor device according to a third embodiment of the present invention. FIG. 6 is a schematic cross-sectional structure diagram of a multistage VIA hole including a large-diameter VIA hole 20 and a small-diameter VIA hole 30 formed in a semiconductor device according to a third embodiment of the present invention. It is explanatory drawing of the multistage VIA hole formation process applied to the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention, Comprising: (a) Formation process figure of VIA hole 30 of small diameter, (b) Large FIG. 6 is a process diagram for forming a VIA hole 20 having a diameter, and FIG. It is explanatory drawing of another process of the multistage VIA hole formation process applied to the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention, Comprising: (a) It has the insulating film 43 and the electrode 32, FIG. 4B is a process diagram of forming a small diameter VIA hole 30 having a groove of D1, (b) a process diagram of forming a large diameter VIA hole 20, and (c) a process diagram of forming an insulating film 44, a ground electrode 46 and a ground conductor 26.

Explanation of symbols

2 ... Gate finger electrode 3 ... Source finger electrode 4 ... Drain finger electrode 7,9 ... Wire 10 ... Semiconductor chip 11, 31 ... Semi-insulating substrate 12 ... Drain terminal electrodes 14, 14-1, 14-2, 14-3 , 14-4... Gate terminal electrode 15... Overlay or air bridge wiring section 16... Heat generating section 18, 18-1, 18-2, 18-3, 18-4, 18-5. , 20-2, 20-3, 20-4, 20-5, 30 ... VIA hole 20b ... Inner wall surface 22 of VIA hole 20 ... Input side matching circuit board 24 ... Output side matching circuit board 26 ... Grounding conductor 30a ... VIA Inner wall surface 31a of hole 30 ... first surface 31b of semi-insulating substrate ... second surface (back surface) of semi-insulating substrate
31c ... third opening 31d ... third taper region 32 ... electrode 33 ... mask layer 33a ... second opening 33b ... second taper region 34 ... resist layer 34a ... first opening 34b ... first taper region 35 ... mask pattern 35a ... Through hole 36 ... Light source 42 ... Drain region 43, 44 ... Insulating film 45 ... Rough surface 46 ... Ground electrode W0, W1, W3, W5, W6 ... Inside diameter of VIA hole 30 W2, W4 ... Inside diameter of VIA hole 20 Width 121 ... Chamber 122 ... Cathode 123 ... Anode 124 ... High frequency power supply 125 ... Supply port 126 ... Discharge port

Claims (23)

A semi-insulating substrate on a semiconductor chip;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A ground conductor disposed on a second surface opposite to the first surface of the semi-insulating substrate;
A gate terminal electrode, a source terminal electrode, and a drain terminal electrode, which are disposed on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode, and the drain finger electrode; ,
An operating layer formed on a semi-insulating substrate below the gate finger electrode, the source finger electrode and the drain finger electrode;
A VIA hole near the operating layer;
An insulating film disposed on the inner wall surface of the VIA hole;
A ground electrode formed on the second surface of the insulating film and the semi-insulating substrate, and connected to the source terminal electrode in the vicinity of an operation layer from the second surface side of the semi-insulating substrate. A semiconductor device.   The semi-insulating substrate is an SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond substrate. The semiconductor device according to claim 1, wherein the semiconductor device is any one. The semiconductor device according to claim 1, wherein the semi-insulating substrate is a SiC substrate or a GaN substrate, and the insulating film is an Al ₂ O ₃ film or a HfO ₂ film.   2. The semiconductor device according to claim 1, wherein the semi-insulating substrate is a GaAs substrate, and the insulating film is any one of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof. A semi-insulating substrate on a semiconductor chip;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A ground conductor disposed on a second surface opposite to the first surface of the semi-insulating substrate;
A plurality of source terminal electrodes arranged at predetermined intervals on one side of the plurality of finger electrode arrays;
A plurality of drain terminal electrodes arranged between the plurality of source terminal electrodes;
A plurality of gate terminal electrodes arranged at a predetermined interval on the other side of the plurality of finger electrode arrays;
A VIA hole disposed in the semi-insulating substrate below the source terminal electrode;
An insulating film disposed on the inner wall surface of the VIA hole;
And a ground electrode formed on the second surface of the semi-insulating substrate and connected to the source terminal electrode from the second surface side of the semi-insulating substrate. . Source electrode wiring connecting the predetermined number of source finger electrodes to the plurality of source terminal electrodes;
A drain electrode wiring connecting a predetermined number of the drain finger electrodes to the plurality of drain terminal electrodes;
The semiconductor device according to claim 5, further comprising: a gate electrode wiring that connects a predetermined number of the gate finger electrodes to the plurality of gate terminal electrodes.   6. The semiconductor device according to claim 5, wherein the source electrode wiring and the drain electrode wiring have an overlay or an air bridge wiring portion where one of them straddles the other.   The semi-insulating substrate is an SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond substrate. It is either, The semiconductor device of any one of Claims 5-7 characterized by the above-mentioned. The semiconductor according to claim 5, wherein the semi-insulating substrate is a SiC substrate or a GaN substrate, and the insulating film is an Al ₂ O ₃ film or an HfO ₂ film. apparatus.   8. The semiconductor device according to claim 5, wherein the semi-insulating substrate is a GaAs substrate, and the insulating film is any one of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof. The semiconductor device according to item. A semi-insulating substrate on a semiconductor chip;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A ground conductor disposed on a second surface opposite to the first surface of the semi-insulating substrate;
A gate terminal electrode, a source terminal electrode, and a drain terminal electrode, which are disposed on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode, and the drain finger electrode; ,
An operating layer formed on a semi-insulating substrate below the gate finger electrode, the source finger electrode and the drain finger electrode;
A multistage VIA hole comprising a small-diameter VIA hole near the working layer and a large-diameter VIA hole near the ground conductor;
An insulating film disposed on the inner wall surface of the multistage VIA hole;
A ground electrode formed on the second surface of the insulating film and the semi-insulating substrate, and connected to the source terminal electrode in the vicinity of an operation layer from the second surface side of the semi-insulating substrate. A semiconductor device.   The semi-insulating substrate is an SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond substrate. The semiconductor device according to claim 11, wherein the semiconductor device is any one. The semiconductor device according to claim 11, wherein the semi-insulating substrate is a SiC substrate or a GaN substrate, and the insulating film is an Al ₂ O ₃ film or an HfO ₂ film.   12. The semiconductor device according to claim 11, wherein the semi-insulating substrate is a GaAs substrate, and the insulating film is an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof.   12. The semiconductor device according to claim 11, wherein the center of the large-diameter VIA hole is eccentric from the center of the small-diameter VIA hole toward the periphery of the semiconductor chip. Forming a highly perpendicular VIA hole on a semi-insulating substrate in advance using a mask layer without a taper as a mask;
Forming an insulating film on the inner wall surface of the VIA hole;
Forming a ground electrode on the insulating film. A method for manufacturing a semiconductor device, comprising: Forming a sloped VIA hole with a mask layer having a taper as a mask on a semi-insulating substrate;
Forming an insulating film on the inner wall surface of the VIA hole;
Forming a ground electrode on the insulating film. A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 16, wherein a material of the mask layer is aluminum. Forming a mask layer made of a material having an etching rate smaller than that of the semi-insulating substrate on the second surface of the semi-insulating substrate having electrodes formed on the first surface;
Forming a resist layer on the mask layer;
Irradiating the resist layer with light through a first mask pattern provided with a region through which light passes, and forming a first opening in the resist layer;
Heating the resist layer in which the first opening is formed, and forming a first taper region whose thickness decreases toward the first opening side around the first opening of the resist layer;
The mask layer is etched using the first opening of the resist layer to form a second opening in which a part of the second surface of the semi-insulating substrate is exposed, and a second is formed around the second opening. Forming a second tapered region whose thickness decreases toward the opening side;
Removing the resist layer remaining on the mask layer;
The semi-insulating substrate is etched using the second opening, and the inner diameter of the portion located on the second surface side of the semi-insulating substrate is smaller than the inner diameter of the portion located on the first surface side. Forming a VIA hole having a third taper region larger than the width;
An eighth step of forming an insulating film on the inner wall surface of the VIA hole;
And a ninth step of forming a ground electrode on the insulating film.   The method for manufacturing a semiconductor device according to claim 19, wherein a material of the mask layer is aluminum.   The semi-insulating substrate is an SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / GaAlN is formed on the SiC substrate, a sapphire substrate, or a diamond substrate. 21. The method of manufacturing a semiconductor device according to claim 16, wherein the method is any one of the above. Said semi-insulating substrate is a SiC substrate or a GaN substrate, the insulating film, a semiconductor according to any one of claims 16 to 20, characterized in that the the Al ₂ O ₃ film or HfO ₂ film Device manufacturing method.   21. The one of claims 16 to 20, wherein the semi-insulating substrate is a GaAs substrate, and the insulating film is any one of an oxide film, a nitride film, an oxynitride film, or a multilayer film thereof. A method for manufacturing the semiconductor device according to the item.

Images