CN115440655A

CN115440655A - Manufacturing method of high-power radio frequency device

Info

Publication number: CN115440655A
Application number: CN202211145998.5A
Authority: CN
Inventors: 李海滨; 樊永辉; 许明伟; 樊晓兵
Original assignee: Shenzhen Huixin Communication Technology Co ltd
Current assignee: Shenzhen Huixin Communication Technology Co ltd
Priority date: 2022-09-20
Filing date: 2022-09-20
Publication date: 2022-12-06

Abstract

The invention provides a manufacturing method of a high-power radio frequency device, which comprises the following steps: first, a high power radio frequency semiconductor structure is provided, which includes: a first region of a substrate and a first electrode, a second electrode and a third electrode; then, forming a first blind hole and a second blind hole in the substrate from the front surface, forming a fourth electrode in the first blind hole and forming a fifth electrode in the second blind hole; forming a metal interconnection layer on the fourth electrode, the fifth electrode, the second region of the substrate and the high-power radio-frequency semiconductor structure, wherein the metal interconnection layer comprises a grounding electrode electrically connected with the second electrode, an input electrode electrically connected with the first electrode and the fourth electrode and an output electrode electrically connected with the third electrode and the fifth electrode; then forming a grounding pad electrically connected with the grounding electrode on the metal interconnection layer; and then thinning the substrate from the back until the fourth electrode and the fifth electrode are exposed, and forming an input bonding pad electrically connected with the fourth electrode and an output bonding pad electrically connected with the fifth electrode. Reduce the thermal resistance of the device, reduce the process cost and improve the yield.

Description

Method for manufacturing high-power radio frequency device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a high-power radio-frequency device.

Background

High power radio frequency devices, such as radio frequency power amplifiers, are important components of various wireless transmitters, and in transmission systems, the output power of a radio frequency power amplifier can be as large as several hundred watts. Therefore, the heat dissipation effect of the rf power amplifier determines the reliability and cost of the whole amplifier operation.

In the related art, a third-generation high-quality semiconductor gallium nitride material is directly grown and deposited on a silicon substrate, and the manufacturing cost of a gallium nitride device can be greatly reduced by means of a large-size and low-cost silicon wafer and an automatic process line thereof. However, since silicon has poor thermal conductivity, even if the gallium nitride wafer based on the silicon substrate is thinned as much as possible, the thermal resistance is still high, and it is difficult to obtain excellent heat dissipation performance. In addition, because the mismatch between the silicon substrate lattice and the gallium nitride lattice is relatively large, the thinning degree of the gallium nitride wafer based on the silicon substrate is limited, which causes that the gallium nitride radio frequency power amplifier chip based on the silicon substrate is difficult to be used in a radio frequency power amplifier for a new generation of wireless communication base station due to the problem of poor heat dissipation.

Disclosure of Invention

The invention aims to provide a manufacturing method of a high-power radio frequency device, which can obtain lower device thermal resistance while ensuring the high-frequency performance of the device.

In order to achieve the above object, the present invention provides a method for manufacturing a high power rf device, comprising:

providing a high power radio frequency semiconductor structure, the high power radio frequency semiconductor structure comprising: the display device comprises a first area of a substrate, and a first electrode, a second electrode and a third electrode which are positioned on the front surface of the first area, wherein the second electrode and the third electrode are positioned on two sides of the first electrode;

forming a first blind hole and a second blind hole in the substrate from the front surface of the substrate; forming a fourth electrode at least in the first blind hole and a fifth electrode at least in the second blind hole;

forming a metal interconnection layer on the fourth electrode, the fifth electrode, the second region of the substrate and the high-power radio-frequency semiconductor structure; the metal interconnection layer comprises a grounding electrode, an input electrode and an output electrode; the grounding electrode is electrically connected with the second electrode, the input electrode is electrically connected with the first electrode and the fourth electrode, and the output electrode is electrically connected with the third electrode and the fifth electrode;

forming a grounding pad on one side of the metal interconnection layer far away from the substrate, wherein the grounding pad is electrically connected with the grounding electrode;

thinning the substrate from the back surface until the fourth electrode and the fifth electrode are exposed; and forming an input bonding pad and an output bonding pad on the back surface of the substrate, wherein the input bonding pad is electrically connected with the fourth electrode, and the output bonding pad is electrically connected with the fifth electrode.

Optionally, the high-power radio-frequency semiconductor structure is an LDMOS structure or an HEMT structure, the first electrode is a gate, the second electrode is a source, and the third electrode is a drain.

Optionally, the high-power radio-frequency semiconductor structure is an HBT structure, the first electrode is a base electrode, the second electrode is a collector electrode, and the third electrode is an emitter electrode.

Optionally, the metal interconnect layer comprises a second dielectric layer; before the step of forming the grounding pad, covering a third dielectric layer on one side of the metal interconnection layer far away from the substrate, wherein the grounding pad is formed on the third dielectric layer; the dielectric constant of the third dielectric layer is less than the dielectric constant of the second dielectric layer, and the thermal conductivity of the third dielectric layer is greater than the thermal conductivity of the substrate.

Optionally, the dielectric constant of the third dielectric layer is less than the dielectric constant of the substrate.

Optionally, the substrate comprises: at least one of single crystal silicon, single crystal diamond, silicon carbide, gallium nitride, and sapphire; and/or the material of the second dielectric layer is at least one of silicon dioxide, silicon nitride and silicon oxynitride; and/or the material of the third dielectric layer is at least one of polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide and amorphous silicon carbide.

Optionally, the thickness of the third dielectric layer ranges from 5 μm to 20 μm.

Optionally, the third dielectric layer is formed by at least one of microwave plasma chemical vapor deposition, inductively coupled plasma chemical vapor deposition, pulsed laser deposition, and electron magnetic resonance chemical vapor deposition, and the deposition temperature is less than or equal to 400 ℃.

Optionally, the substrate includes the first region and the second region, and an orthogonal projection of the fourth electrode, the fifth electrode, the input electrode, and the output electrode on a plane where the substrate is located in the second region.

Optionally, the ground electrode is electrically connected to the second electrode through the metal interconnection layer, the input electrode is electrically connected to the first electrode and the fourth electrode through the metal interconnection layer, and the output electrode is electrically connected to the third electrode and the fifth electrode through the metal interconnection layer.

Optionally, the high power radio frequency semiconductor structure comprises: a first dielectric layer covering the front surface of the substrate, the first electrode, the second electrode, and the third electrode; the first and second blind vias are formed in the substrate and the first dielectric layer.

Optionally, the step of forming a fourth electrode at least in the first blind via and a fifth electrode at least in the second blind via includes:

forming a metal layer on one side of the first dielectric layer far away from the substrate and on the whole surface in the first blind hole and the second blind hole;

and polishing the metal layer until the first dielectric layer is exposed, wherein the metal layer remained in the first blind hole forms the fourth electrode, and the metal layer remained in the second blind hole forms the fifth electrode.

Optionally, the metal layer fills the first blind hole and the second blind hole, or the metal layer is formed on inner walls of the first blind hole and the second blind hole.

Optionally, between the step of covering the third dielectric layer and the step of forming the ground pad, the method for manufacturing the high-power radio-frequency device further includes: and covering a passivation layer on the third dielectric layer, wherein the thickness ratio of the passivation layer to the second dielectric layer ranges from 0.025 to 0.3.

Optionally, the passivation layer is of a single-layer structure, and the single-layer structure is made of silicon nitride; or the passivation layer is of a laminated structure, and the laminated structure sequentially comprises a silicon dioxide layer and a silicon nitride layer in the direction departing from the second dielectric layer.

Optionally, the manufacturing method of the high-power radio-frequency device further includes:

providing a packaging tube shell;

and the grounding bonding pad is attached to the packaging tube shell, and the input bonding pad and the output bonding pad are led out of the packaging tube shell through metal leads.

Compared with the prior art, the invention has the beneficial effects that:

1. manufacturing a grounding bonding pad on one side of the front surface of the substrate, and manufacturing an input bonding pad and an output bonding pad on one side of the back surface of the substrate; during packaging, the grounding bonding pad is only required to be attached to the packaging tube shell, and the input bonding pad and the output bonding pad are led out of the packaging tube shell in a routing mode. The heat dissipation capacity of the high-power radio-frequency device is larger than that of the substrate by controlling the arrangement, the type and the thickness of each layer of the multilayer structure positioned on one side of the front surface of the substrate, so that the heat resistance of heat generated in the working process of the high-power radio-frequency device in the process of conducting through the heat conduction path of the multilayer structure on the front surface of the substrate → the tube shell is smaller than that of the heat generated in the process of conducting through the heat conduction path of the substrate → the tube shell, and the high-frequency performance of the device is ensured.

2. The input pad on the back surface of the substrate is electrically connected with the first electrode through: firstly, forming a first blind hole in a substrate from the front surface, and forming a fourth electrode at least in the first blind hole; forming a metal interconnection layer on the front surface of the substrate, wherein the metal interconnection layer comprises an input electrode electrically connected with the first electrode and the fourth electrode; and then thinning the substrate from the back surface until the fourth electrode is exposed, and forming an input bonding pad which is electrically connected with the fourth electrode on the back surface of the substrate. The output pad on the back surface of the substrate is electrically connected with the third electrode through: firstly, forming a second blind hole in the substrate from the front surface, and forming a fifth electrode at least in the second blind hole; forming a metal interconnection layer on the front surface of the substrate, wherein the metal interconnection layer comprises an output electrode electrically connected with the third electrode and the fifth electrode; and then thinning the substrate from the back surface until the fifth electrode is exposed, and forming an output bonding pad which is electrically connected with the fifth electrode on the back surface of the substrate. Forming a metal interconnection layer on the front surface of the substrate, wherein the metal interconnection layer comprises an input electrode and an output electrode, the input electrode is electrically connected with the first electrode, and the output electrode is electrically connected with the third electrode; then, a first through hole and a second through hole are formed in the substrate and the metal interconnection layer from the back surface of the substrate, the first through hole exposes the input electrode, and the second through hole exposes the output electrode; then, forming a process circuit for electrically connecting the input pad of the input electrode and the output pad of the output electrode on the back surface of the substrate, wherein the process circuit has the advantages that:

1) Double-sided overlay is not needed, and equipment and process cost is reduced;

2) The thermal budget of the substrate backside process can be reduced. In the process of etching through holes on the back, a high-power plasma etching process is generally needed, and a large amount of heat is generated in a substrate; if the heat dissipation capability is limited, the adhesive layer (different materials have different denaturation temperatures, generally lower than 250 ℃) for adhering the substrate and the carrier plate is denatured, so that denatured organic matters remain on the surface of the substrate after the carrier plate is subsequently removed, and the device is contaminated to cause failure;

3) Deterioration in reliability of electrical connection between the input electrode and the output electrode can be avoided. In the process of etching the through hole on the back, a high-power plasma etching process is generally needed, and the high-power over-etching can cause the input electrode and the output electrode to be etched through, thereby affecting the reliability.

3. The grounding pad is arranged on one side of the front surface of the substrate for grounding, so that the grounding inductance of the radio frequency device can be reduced, the gain and cut-off frequency of the radio frequency device are improved, and the high-frequency characteristic of the radio frequency device is improved.

Drawings

Fig. 1 is a flow chart of a method of fabricating a high power rf device according to a first embodiment of the present invention;

fig. 2 to 10 are schematic intermediate structures corresponding to the manufacturing method of fig. 1;

fig. 11 to 13 are schematic intermediate structures corresponding to a manufacturing method of a high-power rf device according to a second embodiment of the invention;

fig. 14 to 15 are schematic intermediate structural diagrams corresponding to a manufacturing method of a high-power rf device according to a third embodiment of the invention;

fig. 16 is a schematic intermediate structure diagram corresponding to a manufacturing method of a high-power rf device according to a fourth embodiment of the invention;

fig. 17 is a schematic intermediate structure diagram corresponding to the manufacturing method of the high-power rf device according to the fifth embodiment of the invention.

To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:

first region 10a of substrate 10

Second region 10b front face 10c

Back side 10d high power RF semiconductor structure 101

First electrode, gate 101a, second electrode, source 101b

Fourth electrode, drain 101c heterojunction structure 101d

P-type semiconductor layer 101e first dielectric layer 1011

First blind hole 102 and second blind hole 103

Fourth electrode 111 of metal layer 11

Fifth electrode 112 metal interconnect layer 12

Second dielectric layer 120 ground electrode 121

Input electrode 122 and output electrode 123

Third dielectric layer 13 ground pad 141

Input pad 142 output pad 143

Passivation layer 15 packaging tube shell 20

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 is a flow chart of a method of fabricating a high power rf device according to a first embodiment of the present invention; fig. 2 to 10 are schematic intermediate structures corresponding to the manufacturing method of fig. 1.

First, referring to step S1 and fig. 2 in fig. 1, a high power rf semiconductor structure 101 is provided, where the high power rf semiconductor structure 101 includes: the first region 10a of the substrate 10 and the first electrode 101a, the second electrode 101b and the third electrode 101c located on the front surface 10c of the first region 10a, the second electrode 101b and the third electrode 101c are located at two sides of the first electrode 101a.

The material of the substrate 10 may be monocrystalline silicon, monocrystalline diamond, sapphire, silicon carbide, gallium nitride, or the like.

Referring to fig. 1, a substrate 10 includes a first region 10a and a second region 10b, and the second region 10b may be disposed around the first region 10a.

A high power radio frequency semiconductor structure 101 is formed in the first region 10a. In this embodiment, the high power rf semiconductor structure 101 is an LDMOS structure or an HEMT structure. Correspondingly, the first electrode 101a is a gate, the second electrode 101b is a source, and the third electrode 101c is a drain.

Taking the HEMT semiconductor structure as an example, the first region 10a may have a heterojunction structure 101d formed thereon. The heterojunction structure 101d may include a channel layer close to the substrate 10 and a barrier layer far from the substrate 10. The interface between the channel layer and the barrier layer may form a two-dimensional electron gas. The channel layer and the barrier layer can be made of GaN-based materials, and the forbidden band width of the barrier layer is larger than that of the channel layer. The barrier layer may be AlGaN, and the channel layer may be GaN.

The heterojunction structure 101d includes a gate region, and source and drain regions on both sides of the gate region. The gate region may have a P-type semiconductor layer 101e thereon to consume excess two-dimensional electron gas in the channel to form an enhancement mode HEMT device. The P-type semiconductor layer 101e may have a gate electrode 101a on a side thereof away from the substrate 10 to control turning off or on a channel region.

The source 101b contacts a source region of the heterojunction structure, and the drain 101c contacts a drain region of the heterojunction structure. The source and drain

electrodes

101b and 101c may contact a channel layer of the heterojunction structure.

In other embodiments, the high power rf semiconductor structure 101 may also be an HBT structure. Correspondingly, the first electrode 101a is a base, the second electrode 101b is a collector, and the third electrode 101c is an emitter. In addition, in some embodiments, the high power rf semiconductor structure 101 may also be more than two of a HEMT structure, an LDMOS structure and an HBT structure.

In this embodiment, referring to fig. 1, the high power rf semiconductor structure 101 further includes: a first dielectric layer 1011, the first dielectric layer 1011 covers the front surface 10c, the source 101b, the drain 101c and the gate 101a of the substrate 10.

The surface of the first dielectric layer 1011 remote from the substrate 10 is planar. The material of the first dielectric layer 1011 may be one or a combination of silicon dioxide, silicon nitride and silicon oxynitride, or the first dielectric layer 1011 is a stacked structure composed of different material layers.

In other embodiments, the first dielectric layer 1011 may be omitted.

Next, referring to step S2 in fig. 1 and fig. 3, a first blind via 102 and a second blind via 103 are opened in the substrate 10 from the front surface 10c of the substrate 10; referring to fig. 5, a fourth electrode 111 is formed in the first blind via 102 and a fifth electrode 112 is formed in the second blind via 103.

The first blind via 102 and the second blind via 103 can be formed by dry etching using patterned photoresist as a mask.

The depth of the first blind via 102 and the second blind via 103 may range from 100 μm to 300 μm. The numerical ranges in this embodiment include the endpoints.

In this embodiment, the first blind via 102 and the second blind via 103 are located at one side of the high power rf semiconductor structure 101. In other embodiments, the first blind via 102 and the second blind via 103 may also be disposed around the high power rf semiconductor structure 101.

In this embodiment, the orthographic projection of the first blind via 102 and the second blind via 103 on the plane of the substrate 10 is located in the second region 10b. In other embodiments, the orthographic projection of the first blind via 102 and the second blind via 103 on the plane of the substrate 10 may also partially overlap with the first region 10a without affecting the performance of the high power rf semiconductor structure 101.

The steps S21 and S22 may be specifically included in forming the fourth electrode 111 and the fifth electrode 112.

Step S21: referring to fig. 4, a metal layer 11 is formed on the side of the first dielectric layer 1011 away from the substrate 10 and in the entire first blind via 102 and the second blind via 103.

In this embodiment, referring to fig. 4, the metal layer 11 fills the first blind via 102 and the second blind via 103. The material of the metal layer 11 may be at least one of aluminum, copper and tungsten. Before the step of forming the metal layer 11, an adhesion layer may be formed on the entire surface, and the material may be at least one of titanium, titanium nitride, and nickel. The entire surface of the metal layer 11 may be formed by sputtering or chemical vapor deposition.

Step S22: referring to fig. 5, the metal layer 11 is polished until the first dielectric layer 1011 is exposed, the metal layer 11 remaining in the first blind via 102 forms the fourth electrode 111, and the metal layer 11 remaining in the second blind via 103 forms the fifth electrode 112.

The polished metal layer 11 may be a chemical mechanical polishing method.

For the embodiment without the metal first dielectric layer 1011, before forming the metal layer 11, the high power rf semiconductor structure 101 may be covered with a photoresist layer, and the metal layer 11 may be patterned to form the fourth electrode 111 and the fifth electrode 112. Thereafter, the excess photoresist layer may be removed by ashing.

Thereafter, referring to step S3 in fig. 1 and fig. 6, a metal interconnection layer 12 is formed on the fourth electrode 111, the fifth electrode 112, the second region 10b and the high power rf semiconductor structure 101; the metal interconnection layer 12 includes a ground electrode 121, an input electrode 122, and an output electrode 123; the ground electrode 121 is electrically connected to the second electrode 101b, the input electrode 122 is electrically connected to the first electrode 101a and the fourth electrode 111, and the output electrode 123 is electrically connected to the third electrode 101c and the fifth electrode 112.

In this embodiment, the metal interconnect layer 12 includes a second dielectric layer 120. The ground electrode 121 is electrically connected to the source 101b through the metal interconnection layer 12, the input electrode 122 is electrically connected to the gate 101a and the fourth electrode 111 through the metal interconnection layer 12, and the output electrode 123 is electrically connected to the drain 101c and the fifth electrode 112 through the metal interconnection layer 12.

The second dielectric layer 120 may be an interlayer dielectric layer (ILD). The material of the interlayer dielectric layer can be silicon dioxide, silicon nitride or silicon oxynitride, and is formed by a physical vapor deposition method or a chemical vapor deposition method correspondingly.

The ground electrode 121, the input electrode 122, and the output electrode 123 may be made of at least one of aluminum, gold, copper, and silver, and may be formed by a sputtering method or a chemical vapor deposition method.

In this embodiment, the grounding electrode 121, the input electrode 122 and the output electrode 123 are located on one side of the high power rf semiconductor structure 101. In other embodiments, the ground electrode 121, the input electrode 122, and the output electrode 123 may also be disposed around the high power rf semiconductor structure 101.

In this embodiment, the orthographic projection of the ground electrode 121, the input electrode 122 and the output electrode 123 on the plane of the substrate 10 is located in the second region 10b. In other embodiments, the orthographic projection of the ground electrode 121, the input electrode 122 and the output electrode 123 on the plane of the substrate 10 may also partially overlap with the first region 10a without affecting the performance of the high-power rf semiconductor structure 101.

Next, referring to step S4 in fig. 1 and fig. 8, a ground pad 141 is formed on the side of the metal interconnection layer 12 away from the substrate 10, and the ground pad 141 is electrically connected to the ground electrode 121.

The step S4 specifically includes steps S41 and S42.

Step S41: referring to fig. 7, a third dielectric layer 13 is covered on the side of the metal interconnect layer 12 remote from the substrate 10.

In this embodiment, the dielectric constant of the third dielectric layer 13 is smaller than that of the second dielectric layer 120, and the thermal conductivity of the third dielectric layer 13 is greater than that of the substrate 10. Compared with the embodiment in which the third dielectric layer 13 and the second dielectric layer 120 are made of the same material, the present embodiment can achieve further reduction in the thermal resistance of the device while ensuring the high-frequency performance of the device. The reason is that: because the thermal resistance of the substrate 10 is large, the heat dissipation path from the back side of the substrate 10 has poor heat dissipation performance, so that the heat dissipation path from the front side of the substrate 10 is considered for heat dissipation; this requires a thinner thickness of the third dielectric layer 13 to reduce thermal resistance, but a thinner thickness increases parasitic capacitance, which limits the high-frequency performance of the device; the third dielectric layer 13 is made of a material with a large thermal conductivity and a small dielectric constant, and the heat dissipation performance of the device can be greatly improved due to the large thermal conductivity, so that the thickness can be thicker, and the parasitic capacitance can be reduced due to the small dielectric constant. The method is particularly suitable for high-frequency power semiconductor devices and radio frequency/millimeter wave monolithic integrated circuits with strict requirements on heat dissipation capacity and parasitic electrical parameters.

When the dielectric constant of the third dielectric layer 13 is smaller than that of the substrate 10, the parasitic capacitance can be further reduced.

The material of the third dielectric layer 13 satisfying the above condition may be at least one of polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide and amorphous silicon carbide, and is correspondingly formed by using one or more combinations of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), plasma Enhanced Chemical Vapor Deposition (PECVD) and inductively coupled plasma chemical vapor deposition (ICP-CVD). Preferably, the dielectric layer is formed by using one or more of Microwave Plasma Chemical Vapor Deposition (MPCVD), inductively coupled plasma chemical vapor deposition (ICP-CVD), pulsed Laser Deposition (PLD), and electron magnetic resonance chemical vapor deposition (ECR-CVD). The deposition temperature of the above process may be low, for example, less than or equal to 400 ℃, without affecting the performance of the high power rf semiconductor structure 101.

The third dielectric layer 13 may also be a laminated structure of the following different material layers: polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide and amorphous silicon carbide.

The thickness of the third dielectric layer 13 ranges from 5 μm to 20 μm, preferably from 10 μm to 20 μm.

Step S42: referring to fig. 8, a ground pad 141 is formed on a side of the third dielectric layer 13 remote from the substrate 10, the ground pad 141 electrically connecting the ground electrode 121.

In this embodiment, forming the ground pad 141 may include: a via hole is opened in the third dielectric layer 13, exposing the ground electrode 121; filling the via and forming a ground pad 141 on the side of the third dielectric layer 13 remote from the substrate 10.

The via hole may be formed using a dry etching method. The ground pad 141 may be formed on the entire surface by a physical vapor deposition method or an electroplating method, and may be made of metal such as Au, ag, cu, or Al, and may have a thickness of 3 μm or more.

Thereafter, referring to step S5 and fig. 9 in fig. 1, the substrate 10 is thinned from the back surface 10d until the fourth electrode 111 and the fifth electrode 112 are exposed; referring to fig. 10, an input pad 142 and an output pad 143 are formed on the back surface 10d of the substrate 10, the input pad 142 being electrically connected to the fourth electrode 111, and the output pad 143 being electrically connected to the fifth electrode 112.

Before thinning the substrate 10, the ground pad 141 may be adhered to the carrier, and the material of the adhesion layer may be paraffin, thermal curing glue or UV curing glue.

The thinned substrate 10 may be ground by a grinding process, such as grinding by a grinding wheel.

The input pad 142 and the output pad 143 may be formed by a physical vapor deposition method or an electroplating method, and may be made of metal such as Au, ag, cu, or Al, and may have a thickness of 3 μm or more.

When substrate 10 is a non-insulating semiconductor material, such as doped monocrystalline silicon, non-insulating silicon carbide, or non-insulating gallium nitride, an insulating layer may be formed on back surface 10d of substrate 10 prior to forming input pads 142 and output pads 143. The material of the insulating layer can be silicon nitride or silicon dioxide, and the thickness can be greater than or equal to 0.5 μm. The input pad 142 and the output pad 143 are formed on the insulating layer.

When the substrate 10 is an insulating material, such as a material of single crystal diamond, sapphire, or the like, the insulating layer may be omitted, and the input pads 142 and the output pads 143 are directly formed on the back surface 10d of the substrate 10.

The thinner the thickness of the substrate 10 is, the better the heat dissipation performance is, but too thin the thickness may cause the substrate 10 to be broken in the thinning process.

In this embodiment, the high power rf device may be used for a high power rf amplifier, a communication base station, a vehicle radar, and the like.

Fig. 11 to fig. 13 are schematic intermediate structural diagrams corresponding to the manufacturing method of the high power rf device according to the second embodiment of the present invention.

Referring to fig. 11 to 13, a manufacturing method of the high power rf device of the second embodiment is substantially the same as the manufacturing method of the high power rf device of the first embodiment, and only differs therefrom: referring to fig. 11, in step S21, the metal layer 11 formed on the whole surface is thin, does not fill the first blind via 102 and the second blind via 103, and only covers inner walls of the first blind via 102 and the second blind via 103; referring to fig. 12, after polishing the metal layer 11 until the first dielectric layer 1011 is exposed, the metal layer 11 on the inner wall of the first blind via 102 forms the fourth electrode 111, and the metal layer 11 on the inner wall of the second blind via 103 forms the fifth electrode 112.

In other words, the fourth electrode 111 and the fifth electrode 112 in the present embodiment are annular on the surface of the first dielectric layer 1011 away from the substrate 10.

Referring to fig. 13, the first recess region surrounded by the fourth electrode 111 and the second recess region surrounded by the fifth electrode 112 may be filled with the second dielectric layer 120 when the metal interconnection layer 12 is formed in step S3.

In other embodiments, referring to fig. 11, a fourth dielectric layer (not shown) may also be formed on the entire surface of the metal layer 11, where the fourth dielectric layer fills a first recess region and a second recess region surrounded by the metal layer 11, the first recess region corresponds to the first blind via 102, and the second recess region corresponds to the second blind via 103; the fourth dielectric layer and the metal layer 11 are polished until the first dielectric layer 1011 is exposed. Or, referring to fig. 12, a fourth dielectric layer (not shown) is formed on the entire surface of the fourth electrode 111, the fifth electrode 112 and the first dielectric layer 1011, and the fourth dielectric layer fills the first recess region surrounded by the fourth electrode 111 and the second recess region surrounded by the fifth electrode 112; the fourth dielectric layer is then polished until the first dielectric layer 1011 is exposed. The metal interconnection layer 12 is formed on the first dielectric layer 1011, the fourth electrode 111, the fifth electrode 112, and the fourth dielectric layer.

The metal interconnection layer 12 may be connected to the entire turn of the fourth electrode 111, or may be connected to a certain annular section of the fourth electrode 111; and/or the metal interconnection layer 12 may be connected to the entire turn of the fifth electrode 112, or may be connected to a certain annular section of the fifth electrode 112.

Fig. 14 to fig. 15 are schematic intermediate structures corresponding to the manufacturing method of the high power rf device according to the third embodiment of the invention.

Referring to fig. 14 to 15, a manufacturing method of the high-power rf device in the third embodiment is substantially the same as the manufacturing method of the high-power rf device in the second embodiment, and only differs from the manufacturing method of the high-power rf device in the second embodiment in that: referring to fig. 14, in step S22, a patterning process is applied to the metal layer 11 instead of the polishing method. After the metal layer 11 is patterned, a first section and a second section which are distributed in a separated manner are formed; the first section is located on the inner wall of the first blind hole 102 and the surface of the first dielectric layer 1011 away from the substrate 10, and the second section is located on the inner wall of the second blind hole 103 and the surface of the first dielectric layer 1011 away from the substrate 10.

The first section of the first dielectric layer 1011 located on the surface remote from the substrate 10 forms the fourth electrode 111, and the second section of the first dielectric layer 1011 located on the surface remote from the substrate 10 forms the fifth electrode 112.

The patterning process for the metal layer 11 may be implemented by performing dry etching using the patterned photoresist as a mask.

Referring to fig. 15, the metal interconnection layer 12 is connected to the fourth electrode 111 and the fifth electrode 112, respectively.

Fig. 16 is a schematic intermediate structure diagram corresponding to the manufacturing method of the high-power rf device according to the fourth embodiment of the invention.

Referring to fig. 16, a manufacturing method of the high power rf device of the fourth embodiment is substantially the same as the manufacturing method of the high power rf devices of the first to third embodiments, and the differences are only that: between step S41 and step S42, the method further includes: a passivation layer 15 is applied to the third dielectric layer 13 on the side facing away from the substrate 10.

The ratio of the thicknesses of the passivation layer 15 and the third dielectric layer 13 may range from 0.025 to 0.3. The numerical ranges in this embodiment include the endpoints.

In this embodiment, the passivation layer 15 has a single-layer structure, and the single-layer structure is made of silicon nitride. In other embodiments, the passivation layer 15 may also be a stacked structure, and the stacked structure sequentially includes a silicon dioxide layer and a silicon nitride layer toward a direction away from the third dielectric layer 13. The passivation layer 15 may prevent attack by chemicals such as moisture, salt spray, metal ions, etc., which may cause the chip to fail.

In this embodiment, the ground pad 141 is electrically connected to the ground electrode 121 through a via hole opened in the passivation layer 15 and the third dielectric layer 13.

The passivation layer 15 is formed by physical vapor deposition or chemical vapor deposition.

Referring to fig. 17, the high power rf device and the manufacturing method thereof in the fifth embodiment are substantially the same as those in the first to fourth embodiments, and the differences are only: further comprising:

step S6: providing a package envelope 20;

step S7: the ground pad 141 is attached to the package 20, and the input pad 142 and the output pad 143 are led out of the package 20 through metal wires (not shown).

The package of the high-power radio-frequency device can be in the forms of ceramic package, metal package or plastic package.

The ground pad 141 may be attached to the package case 20 by a bonding method or a soldering method. The welding material can be SnAu, snAg, pbSnAg or SnAgCu and other materials.

In the manufacturing method of the high-power radio-frequency device of the embodiment, the heat dissipation capability of each layer of the multilayer structure on the front surface 10c side of the substrate is controlled to be larger than the heat dissipation capability of the substrate 10 itself by controlling the types of materials and the thickness of the layers, so that the thermal resistance Tjc from a junction of the device to the package case 20 is reduced, the heat dissipation capability of the device/circuit is remarkably improved, and the device has higher output power level and higher reliability.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims

1. A method for manufacturing a high power radio frequency device, comprising:

2. The method for manufacturing a high power radio frequency device according to claim 1, wherein the high power radio frequency semiconductor structure is an LDMOS structure or an HEMT structure, the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode;

or the high-power radio-frequency semiconductor structure is an HBT structure, the first electrode is a base electrode, the second electrode is a collector electrode, and the third electrode is an emitter electrode.

3. The method of fabricating a high power radio frequency device according to claim 1, wherein the metal interconnect layer comprises a second dielectric layer; before the step of forming the grounding pad, covering a third dielectric layer on one side of the metal interconnection layer far away from the substrate, wherein the grounding pad is formed on the third dielectric layer; the dielectric constant of the third dielectric layer is less than the dielectric constant of the second dielectric layer, and the thermal conductivity of the third dielectric layer is greater than the thermal conductivity of the substrate.

4. The method for manufacturing a high power radio frequency device according to claim 3, wherein the dielectric constant of the third dielectric layer is smaller than the dielectric constant of the substrate.

5. Method for manufacturing a high power radio frequency device according to claim 3 or 4, characterized in that the substrate comprises: at least one of single crystal silicon, single crystal diamond, silicon carbide, gallium nitride, and sapphire; and/or the material of the second dielectric layer is at least one of silicon dioxide, silicon nitride and silicon oxynitride; and/or the material of the third dielectric layer is at least one of polycrystalline diamond, amorphous diamond, polycrystalline silicon carbide and amorphous silicon carbide.

6. The method for manufacturing a high power radio frequency device according to claim 3 or 4, wherein the thickness of the third dielectric layer is in a range of 5 μm to 20 μm.

7. The method for manufacturing a high power radio frequency device according to claim 3 or 4, wherein the third dielectric layer is formed by at least one of microwave plasma chemical vapor deposition, inductively coupled plasma chemical vapor deposition, pulsed laser deposition, and electromagnetic resonance chemical vapor deposition, and the deposition temperature is less than or equal to 400 ℃.

8. The method for manufacturing a high power radio frequency device according to claim 1, wherein the substrate includes the first region and the second region, and an orthographic projection of the fourth electrode, the fifth electrode, the input electrode and the output electrode on a plane of the substrate is located in the second region.

9. The method for manufacturing a high power radio frequency device according to claim 1, wherein the ground electrode is electrically connected to the second electrode through the metal interconnection layer, the input electrode is electrically connected to the first electrode and the fourth electrode through the metal interconnection layer, and the output electrode is electrically connected to the third electrode and the fifth electrode through the metal interconnection layer.

10. The method for manufacturing a high power radio frequency device according to claim 1, wherein the high power radio frequency semiconductor structure comprises: a first dielectric layer covering the front surface of the substrate, the first electrode, the second electrode, and the third electrode; the first and second blind vias are formed in the substrate and the first dielectric layer.

11. The method of claim 10, wherein the step of forming a fourth electrode in at least the first blind via and a fifth electrode in at least the second blind via comprises:

12. The method of claim 11, wherein the metal layer fills the first and second blind holes, or is formed on inner walls of the first and second blind holes.

13. The method for manufacturing a high power radio frequency device according to claim 3 or 4, wherein between the step of covering the third dielectric layer and the step of forming the ground pad, further comprising: and covering a passivation layer on the third dielectric layer, wherein the thickness ratio of the passivation layer to the third dielectric layer ranges from 0.025 to 0.3.

14. The method for manufacturing a high power radio frequency device according to claim 1, further comprising:

providing a packaging tube shell;