JP2005197398A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2005197398A
JP2005197398A JP2004000994A JP2004000994A JP2005197398A JP 2005197398 A JP2005197398 A JP 2005197398A JP 2004000994 A JP2004000994 A JP 2004000994A JP 2004000994 A JP2004000994 A JP 2004000994A JP 2005197398 A JP2005197398 A JP 2005197398A
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wiring
drain
region
gate
source
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Kenichi Nakura
健一 那倉
Kingo Kurotani
欣吾 黒谷
Terukazu Nagakura
輝和 長倉
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a feedback capacity, an output capacity and an on-state resistance. <P>SOLUTION: The semiconductor device is provided with an FET wherein a source area and a drain area are formed on the main surface of a semiconductor substrate and a gate electrode is formed thereon. A connection layer connecting electrically in a semiconductor substrate is formed adjacent to the source area; and the source area, the drain area, the gate electrode, and the connection layer are formed like a stripe extending continuously in a vertical direction in a single continuous active area. Then gate wiring and drain wiring are formed extending continuously on the active area in a vertical direction, on an interlayer insulating film covering the main surface of the semiconductor substrate. The gate wiring are arranged on the connection layer and connects a branching part and the gate electrode branching horizontally at a plurality of places by plugs, and the drain wiring is arranged on the drain area, and the drain wiring and the drain area are connected by plugs continuing in the nearly entire active area. Then the source wiring is divided and arranged between the branching parts of the gate wiring, and they are connected with the source area and the connection layer by plugs. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に関し、特に、高周波信号を電力増幅する高周波電力増幅器の増幅素子を有する半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to a semiconductor device having an amplifying element of a high frequency power amplifier that amplifies a high frequency signal.

高周波電力増幅器の増幅素子の半導体装置に形成されたＦＥＴは、高周波・高出力の信号を処理するために、ＦＥＴのゲート幅の拡大を目的としてマルチフィンガ等の構成が採用されている。マルチフィンガでは、複数並設されたゲートが一体化されてゲートパッドに接続され、同様に複数並設されたドレインがドレイン配線によって一体化されてドレインパッドに接続されている。複数並設されたソースはソース配線によって一体化されて裏面電極に接続されている。   The FET formed in the semiconductor device of the amplifying element of the high frequency power amplifier employs a configuration such as a multi-finger for the purpose of expanding the gate width of the FET in order to process a high frequency / high output signal. In the multi-finger, a plurality of gates arranged in parallel are integrated and connected to the gate pad, and similarly, a plurality of drains arranged in parallel are integrated by a drain wiring and connected to the drain pad. A plurality of sources arranged in parallel are integrated by source wiring and connected to the back electrode.

携帯電話基地局用送信アンプの高周波電力増幅に用いられる高周波パワーＦＥＴでは、多結晶シリコンにタングステンシリサイドを積層したゲート電極の低抵抗化を図るために、ゲートフィンガと並行に配置し、アルミニュウムを主としたゲート配線と前記ゲート電極とを所定間隔で接続して、ゲート抵抗を低減させている。ゲート抵抗の低減により、入力容量×ゲート抵抗の時定数を小さくし１ＧＨｚを超える周波数での動作を可能にし、高周波特性における電力利得、ドレイン効率の改善を行なっている。   In a high-frequency power FET used for high-frequency power amplification of a mobile phone base station transmission amplifier, in order to reduce the resistance of the gate electrode in which tungsten silicide is laminated on polycrystalline silicon, it is arranged in parallel with the gate finger, and aluminum is mainly used. The gate resistance is reduced by connecting the gate wiring and the gate electrode at a predetermined interval. By reducing the gate resistance, the time constant of input capacitance × gate resistance is reduced to enable operation at a frequency exceeding 1 GHz, and the power gain and drain efficiency in high frequency characteristics are improved.

図１に示すのは、本発明者等が製作した高周波パワーＭＩＳＦＥＴを示す平面図であり、図２に示すのは、図１中のａ‐ａ線に沿った部分拡大縦断面図であり、図３に示すのは、上層及び下層の配線を除いて半導体基板の状態を示す平面図であり、図４に示すのは、上層の配線を除いて下層配線と半導体基板の状態を示す平面図である。なお、本実施の形態では、図１中の上下方向を縦方向とし、図１中の左右方向を横方向として説明する。   FIG. 1 is a plan view showing a high-frequency power MISFET manufactured by the present inventors, and FIG. 2 is a partially enlarged longitudinal sectional view taken along line aa in FIG. FIG. 3 is a plan view showing the state of the semiconductor substrate except for the upper layer wiring and the lower layer wiring, and FIG. 4 is a plan view showing the state of the lower layer wiring and the semiconductor substrate except for the upper layer wiring. It is. In the present embodiment, the vertical direction in FIG. 1 is the vertical direction, and the horizontal direction in FIG. 1 is the horizontal direction.

本実施の形態のＭＩＳＦＥＴは、例えば単結晶シリコンからなるｐ＋型半導体基体１にｐ−型のエピタキシャル層２を形成した半導体基板主面に分離領域３を形成し、この分離領域３によって活性領域を横方向に延在する複数の領域に分割し、夫々の活性領域にチャネル形成のためのｐ型ウェル４を縦方向に延在させて形成し、このｐ型ウェル４の半導体基板主面上に、ゲート絶縁膜５を介して、多結晶シリコンにタングステンシリサイドを積層した積層膜からなるゲート電極６を設けている。   In the MISFET of the present embodiment, an isolation region 3 is formed on a main surface of a semiconductor substrate in which a p− type epitaxial layer 2 is formed on a p + type semiconductor substrate 1 made of, for example, single crystal silicon, and an active region is formed by the isolation region 3. Dividing into a plurality of regions extending in the horizontal direction, p-type wells 4 for forming channels are formed in the respective active regions so as to extend in the vertical direction, and the p-type wells 4 are formed on the main surface of the semiconductor substrate. A gate electrode 6 made of a laminated film in which tungsten silicide is laminated on polycrystalline silicon is provided through a gate insulating film 5.

このゲート電極６の一方の側に位置するｐ型ウェル４にｎ型ソース領域７層を形成し、他方の側に位置するｐ−型エピタキシャル層２にｎ−型層低濃度ドレイン領域８ａを形成し、この低濃度ドレイン領域８ａ内に高濃度ドレイン領域８ｂを形成してある。   An n-type source region 7 layer is formed in the p-type well 4 located on one side of the gate electrode 6, and an n − -type layer low concentration drain region 8 a is formed in the p − -type epitaxial layer 2 located on the other side. The high concentration drain region 8b is formed in the low concentration drain region 8a.

ソース領域７に隣接して、半導体基板内でエピタキシャル層２を貫通し、ｐ＋型半導体基体１と導通する高不純物濃度のｐ＋型接続層９及びこの接続層９のｐ＋型コンタクト領域１０を形成する。   Adjacent to the source region 7, a high impurity concentration p + type connection layer 9 that penetrates the epitaxial layer 2 in the semiconductor substrate and is electrically connected to the p + type semiconductor substrate 1 and a p + type contact region 10 of the connection layer 9 are formed. .

半導体基板主面は、酸化シリコンの層間絶縁膜１１によって覆い、ゲート電極６と高濃度ドレイン領域８ａとの間の層間絶縁膜１１中には、多結晶シリコンを用いたシールド電極１２を形成する。このシールド電極１２が、ゲート電極６とドレイン配線（後述する）との間の層間絶縁膜１１中に形成されることによって、ゲート電極‐ドレイン配線間の電界が緩和され、ドレイン耐圧が向上する。このため、低濃度ドレイン領域の不純物濃度を高めて低抵抗化し、オン抵抗Ｒｏｎを低減させることができる。   The main surface of the semiconductor substrate is covered with an interlayer insulating film 11 made of silicon oxide, and a shield electrode 12 using polycrystalline silicon is formed in the interlayer insulating film 11 between the gate electrode 6 and the high-concentration drain region 8a. By forming the shield electrode 12 in the interlayer insulating film 11 between the gate electrode 6 and the drain wiring (described later), the electric field between the gate electrode and the drain wiring is alleviated and the drain breakdown voltage is improved. For this reason, it is possible to increase the impurity concentration of the low-concentration drain region to lower the resistance, and to reduce the on-resistance Ron.

ｐ型ウェル４、ソース領域７、低濃度ドレイン領域８ａ、高濃度ドレイン領域８ｂ、ｐ型接続層９及びコンタクト領域１０は、夫々の活性領域内で、縦方向に連続して延在するストライプ状に形成してある。ゲート電極６及びシールド電極１２は、何れも、複数の活性領域にまたがって、縦方向に連続して延在するストライプ状に形成してある。この状態が図３に示されている。   The p-type well 4, the source region 7, the low-concentration drain region 8 a, the high-concentration drain region 8 b, the p-type connection layer 9, and the contact region 10 are striped continuously extending in the vertical direction in each active region. Is formed. Each of the gate electrode 6 and the shield electrode 12 is formed in a stripe shape extending continuously in the vertical direction across a plurality of active regions. This state is shown in FIG.

層間絶縁膜１１上には、図４に示すように、縦方向に複数の活性領域上を連続して延在するストライプ状にソース配線１３及び下層のドレイン配線１４を形成する。ソース配線１３は、コンタクト領域１０上に配置し、層間絶縁膜１１に設けられた開口によって、ソース配線１３を夫々の活性領域ごとにソース領域７及びコンタクト領域１０と接触導通させて接続している（図４中では接続部分を破線にて図示）。ソース領域７は、ソース配線１３、コンタクト領域１０、接続層９及び半導体基体１を順に介して、半導体基板裏面の半導体基体１に形成された裏面電極１５に、電気的に接続してある。   On the interlayer insulating film 11, as shown in FIG. 4, a source wiring 13 and a lower drain wiring 14 are formed in a stripe shape extending continuously in the vertical direction on a plurality of active regions. The source wiring 13 is disposed on the contact region 10 and is connected in contact with the source region 7 and the contact region 10 for each active region through an opening provided in the interlayer insulating film 11. (In FIG. 4, the connecting portion is indicated by a broken line). The source region 7 is electrically connected to the back electrode 15 formed on the semiconductor substrate 1 on the back surface of the semiconductor substrate through the source wiring 13, the contact region 10, the connection layer 9, and the semiconductor substrate 1 in this order.

下層のドレイン配線１４は、高濃度ドレイン領域８ｂ上に配置され、層間絶縁膜１１に設けられた開口によって、下層のドレイン配線１４を夫々の活性領域ごとに高濃度ドレイン領域８ｂと接触導通させて接続している（図４中では接続部分を破線にて図示）。ソース配線１３及び下層のドレイン配線１４はアルミニュウムを主成分とした同一の金属膜からパターニング形成され、上層の層間絶縁膜１６によって覆われている。   The lower-layer drain wiring 14 is disposed on the high-concentration drain region 8b, and the lower-layer drain wiring 14 is brought into contact with the high-concentration drain region 8b for each active region through an opening provided in the interlayer insulating film 11. They are connected (in FIG. 4, the connecting portion is indicated by a broken line). The source wiring 13 and the lower drain wiring 14 are formed by patterning from the same metal film mainly composed of aluminum, and are covered with an upper interlayer insulating film 16.

層間絶縁膜１６上には、縦方向に複数の活性領域上を連続して延在するストライプ状にゲート配線１７及び上層のドレイン配線１８を形成する。   On the interlayer insulating film 16, a gate wiring 17 and an upper drain wiring 18 are formed in a stripe shape extending continuously in the vertical direction over a plurality of active regions.

ゲート配線１７は、コンタクト領域１０上に配置し、分離領域上の複数箇所で横方向に分岐して層間絶縁膜１６上をゲート電極６近くまで延在し、層間絶縁膜１１，１６に設けた開口によって、ゲート配線１７の分岐部１７ａとゲート電極６とを分離領域３上で接触導通させて接続している（図１中では接続部分を破線にて図示）。縦方向に連続して延在する複数のゲート配線１７を活性領域外で横方向に延在する連結部１７ｂによって並列接続し、連結部１７ｂには接続のためのゲートボンディングパッド１７ｃを形成する。   The gate wiring 17 is disposed on the contact region 10, is laterally branched at a plurality of locations on the isolation region, extends on the interlayer insulating film 16 to the vicinity of the gate electrode 6, and is provided on the interlayer insulating films 11 and 16. Through the opening, the branch portion 17a of the gate wiring 17 and the gate electrode 6 are brought into contact with each other on the separation region 3 to be connected (in FIG. 1, the connection portion is indicated by a broken line). A plurality of gate wirings 17 extending in the vertical direction are connected in parallel by a connecting portion 17b extending in the horizontal direction outside the active region, and a gate bonding pad 17c for connection is formed in the connecting portion 17b.

上層のドレイン配線１８は、下層のドレイン配線１４上に配置され、層間絶縁膜１６に設けられた開口によって、上層のドレイン配線１８を下層のドレイン配線１４と接触導通させて接続している（図１中では接続部分を破線にて図示）。縦方向に連続して延在する複数の上層のドレイン配線１８を活性領域外で横方向に延在する連結部１８ｂによって並列接続し、連結部１８ｂには接続のためのドレインボンディングパッド１８ｃを形成する。ゲート配線１７、分岐部１７ａ、連結部１７ｂ、ゲートボンディングパッド１７ｃ及び上層のドレイン配線１８、連結部１８ｂ、ドレインボンディングパッド１８ｃはアルミニュウムを主成分とした同一の金属膜からパターニング形成されている。   The upper-layer drain wiring 18 is disposed on the lower-layer drain wiring 14, and is connected to the lower-layer drain wiring 14 in contact with the lower-layer drain wiring 14 through an opening provided in the interlayer insulating film 16 (FIG. In 1, the connecting portion is indicated by a broken line). A plurality of upper layer drain wirings 18 extending continuously in the vertical direction are connected in parallel by a connecting portion 18b extending in the lateral direction outside the active region, and a drain bonding pad 18c for connection is formed in the connecting portion 18b. To do. The gate wiring 17, the branching portion 17a, the connecting portion 17b, the gate bonding pad 17c and the upper layer drain wiring 18, the connecting portion 18b, and the drain bonding pad 18c are formed by patterning from the same metal film mainly composed of aluminum.

なお、マルチフィンガのＭＩＳＦＥＴについては、下記特許文献１あるいは非特許文献１に記載されている。   The multi-finger MISFET is described in the following Patent Document 1 or Non-Patent Document 1.

特開平１０−３３５６４２号公報JP-A-10-335642

「High-Frequency High-Power Si-MOSFET Device Technology」（２章 図２，３）"High-Frequency High-Power Si-MOSFET Device Technology" (Chapter 2, Figures 2 and 3)

前述した半導体装置では、ゲート電極６の低抵抗化のために上層の配線によって形成されたゲート配線１７と２層に形成されたドレイン配線１４，１８との間の容量である帰還容量Ｃｒｓｓが大きく、また、ソース配線１３と２層に形成されたドレイン配線１４，１８との間の容量である出力容量Ｃｏｓｓも大きくなる。このため、帰還容量Ｃｒｓｓ及び出力容量Ｃｏｓｓが高周波特性を悪化させる原因になっている。   In the semiconductor device described above, the feedback capacitance Crss, which is the capacitance between the gate wiring 17 formed by the upper layer wiring and the drain wirings 14 and 18 formed in the two layers for reducing the resistance of the gate electrode 6, is large. In addition, the output capacitance Coss, which is the capacitance between the source wiring 13 and the drain wirings 14 and 18 formed in two layers, also increases. For this reason, the feedback capacitor Crss and the output capacitor Coss cause the high frequency characteristics to deteriorate.

また、平面パターンについては、活性領域を分離領域３によって分割し、ゲート電極６とゲート配線１７との接続部分を分離領域３上に配置しているために、この分離領域３によって実効ゲート幅Ｗｇが小さくなり、このためオン抵抗Ｒｏｎが増大している。   As for the planar pattern, since the active region is divided by the isolation region 3 and the connection portion between the gate electrode 6 and the gate wiring 17 is disposed on the isolation region 3, the effective gate width Wg is determined by the isolation region 3. As a result, the on-resistance Ron increases.

本発明の課題は、これらの問題点を解決し、帰還容量Ｃｒｓｓ、出力容量Ｃｏｓｓ及びオン抵抗Ｒｏｎを低減させることが可能な技術を提供することにある。
本発明の前記ならびにその他の課題と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。 An object of the present invention is to provide a technique capable of solving these problems and reducing the feedback capacitance Crss, the output capacitance Coss, and the on-resistance Ron.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
半導体基板主面の活性領域に、ソース領域及びドレイン領域を形成し、半導体基板主面上にゲート電極を形成したＦＥＴを有し、前記ソース領域に隣接して、半導体基板内で導通する接続層を形成する半導体装置において、前記ソース領域、ドレイン領域、ゲート電極、接続層は、単一の連続した活性領域内に、縦方向に連続して延在するストライプ状に形成し、前記半導体基板主面を覆う層間絶縁膜上に、縦方向に活性領域上を連続して延在するゲート配線、ドレイン配線を形成し、前記ゲート配線は、前記接続層上に配置し、複数箇所で横方向に分岐する分岐部と前記ゲート電極とをプラグによって接続し、前記ドレイン配線は、前記ドレイン領域上に配置し、ドレイン配線とドレイン領域とは、活性領域の略全域に連続するプラグによって接続し、前記ソース配線は、前記ゲート配線とゲート電極との間に、ゲート配線の分岐部間に分割して配置し、ソース配線は、プラグによってソース領域及び接続層に接続する。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
A connection layer having an FET in which a source region and a drain region are formed in an active region of a main surface of a semiconductor substrate and a gate electrode is formed on the main surface of the semiconductor substrate, and is electrically connected in the semiconductor substrate adjacent to the source region The source region, the drain region, the gate electrode, and the connection layer are formed in a single continuous active region in a stripe shape extending continuously in the vertical direction, and the semiconductor substrate main body is formed. On the interlayer insulating film covering the surface, a gate wiring and a drain wiring continuously extending in the vertical direction on the active region are formed, and the gate wiring is disposed on the connection layer and is laterally arranged at a plurality of locations. The branching portion that branches off and the gate electrode are connected by a plug, the drain wiring is disposed on the drain region, and the drain wiring and the drain region are connected by a plug that continues substantially over the entire active region. Connect Te, the source wiring, between the gate wiring and the gate electrode, arranged divided between the branch portion of the gate wiring, source wiring, connected to the source region and the connecting layer by a plug.

また、その製造方法では、前記ソース領域、ドレイン領域、ゲート電極、接続層を、単一の連続した活性領域内に、縦方向に連続して延在するストライプ状に形成する工程と、前記半導体基板主面を覆う層間絶縁膜を形成し、ゲート電極と接続するプラグ、ドレイン領域と、活性領域の略全域に連続するプラグ、ソース領域及び接続層に接続するプラグを夫々形成する工程と、層間絶縁膜上に、縦方向に活性領域上を連続して延在するゲート配線、ドレイン配線を形成する工程とを有し、前記ゲート配線は、前記接続層上に配置し、複数箇所で横方向に分岐する分岐部が前記ゲート電極と接続するプラグに接続し、前記ドレイン配線は、前記ドレイン領域上に配置し、ドレイン領域と接続するプラグに接続し、前記ソース配線は、前記ゲート配線とゲート電極との間に、ゲート配線の分岐部間に分割して配置し、ソース配線は、ソース領域及び接続層に接続するプラグに接続する。   In the manufacturing method, the source region, the drain region, the gate electrode, and the connection layer are formed in a single continuous active region in a stripe shape extending continuously in the vertical direction, and the semiconductor Forming an interlayer insulating film covering the main surface of the substrate, forming a plug connected to the gate electrode, a drain region, a plug continuous over substantially the entire active region, a plug connected to the source region and the connection layer, and an interlayer Forming a gate wiring and a drain wiring continuously extending in the vertical direction on the active region on the insulating film, and the gate wiring is disposed on the connection layer and laterally arranged at a plurality of positions. A branch portion that branches into the gate electrode is connected to a plug connected to the gate electrode, the drain wiring is disposed on the drain region, connected to a plug connected to the drain region, and the source wiring is connected to the gate Between the line and the gate electrode, arranged divided between the branch portion of the gate wiring, source wiring, connected to the plug connected to the source region and the connection layer.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
（１）本発明によれば、帰還容量Ｃｒｓｓ及び出力容量Ｃｏｓｓを低減させることができるという効果がある。
（２）本発明によれば、上記効果（１）により、帰還容量Ｃｒｓｓが低減するのでミラー容量が減少し電力利得を向上させることができるという効果がある。
（３）本発明によれば、上記効果（１）により、出力容量Ｃｏｓｓが低減するので出力インピーダンスが増加し、整合が容易となるためドレイン効率を向上させることができるという効果がある。
（４）本発明によれば、ゲート電極とゲート配線とを活性領域上で接続し、活性領域吾分割する分離領域をなくしたので、実効ゲート幅Ｗｇが大きくなるという効果がある。
（５）本発明によれば、上記効果（４）により、オン抵抗Ｒｏｎを低減させ、ドレイン電流を増加させることができるという効果がある。
（６）本発明によれば、ドレイン配線とドレイン領域との接続に活性領域の全域に連続するプラグを用いているので、エレクトロマイグレーション寿命を向上させることができるという効果がある。 The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, there is an effect that the feedback capacitance Crss and the output capacitance Coss can be reduced.
(2) According to the present invention, due to the effect (1), the feedback capacitance Crss is reduced, so that the mirror capacitance is reduced and the power gain can be improved.
(3) According to the present invention, due to the effect (1), the output capacitance Coss is reduced, the output impedance is increased, and matching is facilitated, so that the drain efficiency can be improved.
(4) According to the present invention, since the gate electrode and the gate wiring are connected on the active region and the isolation region for dividing the active region is eliminated, there is an effect that the effective gate width Wg is increased.
(5) According to the present invention, the above-described effect (4) has an effect of reducing the on-resistance Ron and increasing the drain current.
(6) According to the present invention, since the plug that is continuous over the entire active region is used to connect the drain wiring and the drain region, the electromigration lifetime can be improved.

以下、本発明の実施の形態を説明する。なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
図５に示すのは、本発明の一実施の形態である高周波パワーＭＩＳＦＥＴを示す平面図であり、図６に示すのは、図５中のａ‐ａ線に沿った部分拡大縦断面図であり、図７に示すのは、配線を除いて半導体基板の状態を示す平面図である。なお、本実施の形態では、図５中の上下方向を縦方向とし、図５中の左右方向を横方向として説明する。 Embodiments of the present invention will be described below. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
FIG. 5 is a plan view showing a high-frequency power MISFET which is an embodiment of the present invention, and FIG. 6 is a partially enlarged longitudinal sectional view taken along the line aa in FIG. FIG. 7 is a plan view showing the state of the semiconductor substrate excluding the wiring. In the present embodiment, the vertical direction in FIG. 5 will be described as the vertical direction, and the horizontal direction in FIG. 5 will be described as the horizontal direction.

本実施の形態のＭＩＳＦＥＴは、例えば単結晶シリコンからなるｐ＋型半導体基体１にｐ−型のエピタキシャル層２を形成した半導体基板主面に分離領域３を形成し、この分離領域３によって囲まれた単一の連続した活性領域に、チャネル形成のためのｐ型ウェル４を縦方向に延在させて形成し、このｐ型ウェル４の半導体基板主面上に、ゲート絶縁膜５を介して、多結晶シリコンにタングステンシリサイドを積層した積層膜からなるゲート電極６を設けている。   In the MISFET of this embodiment, an isolation region 3 is formed on the main surface of a semiconductor substrate in which a p− type epitaxial layer 2 is formed on a p + type semiconductor substrate 1 made of, for example, single crystal silicon, and is surrounded by the isolation region 3. A p-type well 4 for forming a channel is formed in a single continuous active region so as to extend in the vertical direction. On the main surface of the semiconductor substrate of the p-type well 4, a gate insulating film 5 is interposed, A gate electrode 6 made of a laminated film in which tungsten silicide is laminated on polycrystalline silicon is provided.

このゲート電極６の一方の側に位置するｐ型ウェル４にｎ型ソース領域７層を形成し、他方の側に位置するｐ−型エピタキシャル層２にｎ−型層低濃度ドレイン領域８ａを形成し、この低濃度ドレイン領域８ａ内に高濃度ドレイン領域８ｂを形成してある。   An n-type source region 7 layer is formed in the p-type well 4 located on one side of the gate electrode 6, and an n − -type layer low concentration drain region 8 a is formed in the p − -type epitaxial layer 2 located on the other side. The high concentration drain region 8b is formed in the low concentration drain region 8a.

ソース領域７に隣接して、半導体基板内でエピタキシャル層２を貫通し、ｐ＋型半導体基体１と導通する高不純物濃度のｐ＋型接続層９及びｐ＋型コンタクト領域１０を形成する。   Adjacent to the source region 7, a high impurity concentration p + type connection layer 9 and a p + type contact region 10 that penetrate the epitaxial layer 2 in the semiconductor substrate and are electrically connected to the p + type semiconductor substrate 1 are formed.

半導体基板主面は、酸化シリコンの層間絶縁膜１１によって覆い、ゲート電極６と高濃度ドレイン領域８ｂとの間の層間絶縁膜１１中には、多結晶シリコンを用いたシールド電極１２を形成する。このシールド電極によって、ゲート電極‐ドレイン配線（後述する）間の電界が緩和され、ドレイン耐圧が向上する。このため、低濃度ドレイン領域の不純物濃度を高めて低抵抗化し、オン抵抗Ｒｏｎを低減させることができる。   The main surface of the semiconductor substrate is covered with an interlayer insulating film 11 made of silicon oxide, and a shield electrode 12 made of polycrystalline silicon is formed in the interlayer insulating film 11 between the gate electrode 6 and the high-concentration drain region 8b. By this shield electrode, the electric field between the gate electrode and the drain wiring (described later) is relaxed, and the drain breakdown voltage is improved. For this reason, it is possible to increase the impurity concentration of the low-concentration drain region to lower the resistance, and to reduce the on-resistance Ron.

ｐ型ウェル４、ソース領域７、低濃度ドレイン領域８ａ、高濃度ドレイン領域８ｂ、ゲート電極６、ｐ型接続層９、コンタクト領域１０及びシールド電極１２は、何れも、活性領域内に、縦方向に連続して延在するストライプ状に形成してある。この状態を図７に示すが、図７には後述するプラグも図示している。   The p-type well 4, the source region 7, the low-concentration drain region 8a, the high-concentration drain region 8b, the gate electrode 6, the p-type connection layer 9, the contact region 10 and the shield electrode 12 are all in the vertical direction in the active region. Are formed in stripes extending continuously. FIG. 7 shows this state, and FIG. 7 also shows a plug described later.

層間絶縁膜１１上には、縦方向に活性領域上を延在するストライプ状にゲート配線１７及びドレイン配線１８を形成し、ゲート配線１７とドレイン配線１８との間にソース配線１３を配置してある。   On the interlayer insulating film 11, the gate wiring 17 and the drain wiring 18 are formed in stripes extending in the vertical direction on the active region, and the source wiring 13 is disposed between the gate wiring 17 and the drain wiring 18. is there.

ゲート配線１７は、コンタクト領域１０上に配置し、複数箇所で横方向に分岐して層間絶縁膜１１上をゲート電極６近くまで延在し、層間絶縁膜１１を貫通するプラグ１９によって、この分岐部１７ａとゲート電極６とを接続している。縦方向に連続して延在する複数のゲート配線１７を活性領域外で横方向に延在する連結部１７ｂによって並列接続し、連結部１７ｂには接続のためのゲートボンディングパッド１７ｃを形成する。   The gate wiring 17 is arranged on the contact region 10, branches in a lateral direction at a plurality of locations, extends on the interlayer insulating film 11 to the vicinity of the gate electrode 6, and is branched by a plug 19 penetrating the interlayer insulating film 11. The portion 17a and the gate electrode 6 are connected. A plurality of gate wirings 17 extending in the vertical direction are connected in parallel by a connecting portion 17b extending in the horizontal direction outside the active region, and a gate bonding pad 17c for connection is formed in the connecting portion 17b.

ドレイン配線１８は、高濃度ドレイン領域８ｂ上に配置され、活性領域の略全域に連続するプラグ２０によって高濃度ドレイン領域８ｂと接続し、縦方向に連続して延在する複数のドレイン配線１８を活性領域外で横方向に延在する連結部１８ｂによって並列接続し、連結部１８ｂには接続のためのドレインボンディングパッド１８ｃを形成する。   The drain wiring 18 is disposed on the high-concentration drain region 8b, is connected to the high-concentration drain region 8b by a plug 20 that extends substantially throughout the active region, and includes a plurality of drain wirings 18 that extend continuously in the vertical direction. A connecting portion 18b extending in the lateral direction outside the active region is connected in parallel, and a drain bonding pad 18c for connection is formed in the connecting portion 18b.

ソース配線１３は、ゲート配線１７とゲート電極６との間に、ゲート配線１７の分岐部１７ａ間に分割して配置し、ソース配線１３の分岐部１３ａが層間絶縁膜１１上をシールド電極１２近くまで延在し、層間絶縁膜１１を貫通するプラグによって、この分岐部１３ａとシールド電極１２とを接続する。   The source wiring 13 is arranged between the gate wiring 17 and the gate electrode 6 so as to be divided between the branch portions 17 a of the gate wiring 17, and the branch portion 13 a of the source wiring 13 is on the interlayer insulating film 11 and near the shield electrode 12. The branch portion 13a and the shield electrode 12 are connected by a plug extending up to and extending through the interlayer insulating film 11.

ソース配線１３は、層間絶縁膜１１を貫通するプラグ２１によってソース領域７に接続し、プラグ２２によってコンタクト領域１０に接続する。ソース領域７は、プラグ２１、ソース配線１３、プラグ２２、コンタクト領域１０、接続層９及び半導体基体１を順に介して、半導体基板裏面の半導体基体１に形成された裏面電極１５に、電気的に接続してある。   The source wiring 13 is connected to the source region 7 by a plug 21 penetrating the interlayer insulating film 11 and connected to the contact region 10 by a plug 22. The source region 7 is electrically connected to the back electrode 15 formed on the semiconductor substrate 1 on the back surface of the semiconductor substrate through the plug 21, the source wiring 13, the plug 22, the contact region 10, the connection layer 9 and the semiconductor substrate 1 in this order. Connected.

ゲート配線１７、分岐部１７ａ、連結部１７ｂ、ゲートボンディングパッド１７ｃ、ソース配線１３、分岐部１３ａ及びドレイン配線１８、連結部１８ｂ、ドレインボンディングパッド１８ｃはアルミニュウムを主成分とした同一の金属膜からパターニング形成されており、ゲート配線１７、ソース配線１３及びドレイン配線１８とゲート電極６、ソース領域７及び高濃度ドレイン領域８ｂとを、夫々接続するプラグ１９，２０，２１，２２にはタングステンを用いてある。   Gate wiring 17, branching portion 17a, connecting portion 17b, gate bonding pad 17c, source wiring 13, branching portion 13a and drain wiring 18, connecting portion 18b, and drain bonding pad 18c are patterned from the same metal film mainly composed of aluminum. The plugs 19, 20, 21, and 22 that connect the gate wiring 17, the source wiring 13, and the drain wiring 18 with the gate electrode 6, the source region 7, and the high-concentration drain region 8 b are formed using tungsten. is there.

ゲート配線１７、分岐部１７ａ、連結部１７ｂ、ゲートボンディングパッド１７ｃ、ソース配線１３、分岐部１３ａ及びドレイン配線１８、連結部１８ｂ、ドレインボンディングパッド１８ｃは、保護絶縁膜１６によって被覆する。   The gate wiring 17, the branch part 17 a, the connection part 17 b, the gate bonding pad 17 c, the source wiring 13, the branch part 13 a and the drain wiring 18, the connection part 18 b, and the drain bonding pad 18 c are covered with the protective insulating film 16.

本実施の形態の半導体装置では、縦方向に延在するストライプ状にゲート配線１７及びドレイン配線１８を形成し、ゲート配線１７とドレイン配線１８との間にソース配線１３を配置してあるので、帰還容量Ｃｒｓｓ及び出力容量Ｃｏｓｓを低減させることができる。また、本実施の形態の半導体装置では、ドレイン配線１８が一層になり対向部分の面積が半減するので、帰還容量Ｃｒｓｓ及び出力容量Ｃｏｓｓを低減させることができる。   In the semiconductor device of this embodiment, the gate wiring 17 and the drain wiring 18 are formed in stripes extending in the vertical direction, and the source wiring 13 is disposed between the gate wiring 17 and the drain wiring 18. The feedback capacity Crss and the output capacity Coss can be reduced. Further, in the semiconductor device of the present embodiment, the drain wiring 18 becomes one layer and the area of the facing portion is halved, so that the feedback capacitance Crss and the output capacitance Coss can be reduced.

更に、ゲート電極６とゲート配線１７とを活性領域上で接続し、活性領域を分割する分離領域３をなくしたので、実効ゲート幅Ｗｇが大きくなる。   Further, since the gate electrode 6 and the gate wiring 17 are connected on the active region and the isolation region 3 for dividing the active region is eliminated, the effective gate width Wg is increased.

加えて、ドレイン領域８ａ，８ｂは、ドレイン配線１８とプラグ２０との二重構造で、ドレインボンディングパッド１８ｃと接続されており、プラグ２０にエレクトロマイグレーションに対する耐性が高いタングステンを用いていることによって、アルミニュウムのドレイン配線１８がエレクトロマイグレーションにより断線した場合でも、プラグ２０の部分はエレクトロマイグレーションに対する耐性が高いので断線せずに導通を維持する。従って、ドレイン配線１８の切断部分でわずかな抵抗値の変化は生じるが、ＦＥＴの機能を失うことはないので、信頼性が向上する。   In addition, the drain regions 8a and 8b have a dual structure of the drain wiring 18 and the plug 20, and are connected to the drain bonding pad 18c. By using tungsten having high resistance to electromigration for the plug 20, Even when the aluminum drain wiring 18 is disconnected due to electromigration, the plug 20 portion is highly resistant to electromigration, and thus maintains conduction without disconnection. Therefore, although the resistance value slightly changes at the cut portion of the drain wiring 18, the function of the FET is not lost, and the reliability is improved.

続いて、この半導体装置の製造方法について、図８乃至図１０を用いて工程毎に説明する。
先ず、ｐ＋型の半導体基体１上にエピタキシャル成長によってｐ−型のエピタキシャル層２を形成し、このエピタキシャル層２の主面に、ホトリソグラフィによって形成したレジストマスク（図示せず）を用いたイオン注入と熱拡散によって、エピタキシャル層２を貫通し半導体基体１に達する接続層９及びコンタクト領域１０となる高濃度拡散層を形成する。 Next, a manufacturing method of this semiconductor device will be described for each process with reference to FIGS.
First, a p− type epitaxial layer 2 is formed on a p + type semiconductor substrate 1 by epitaxial growth, and ion implantation using a resist mask (not shown) formed by photolithography on the main surface of the epitaxial layer 2 is performed. A high-concentration diffusion layer that forms the connection layer 9 and the contact region 10 that penetrates the epitaxial layer 2 and reaches the semiconductor substrate 1 is formed by thermal diffusion.

次に、ホトリソグラフィによって形成したレジストマスク（図示せず）を用いたボロン等のイオン注入によりＦＥＴのチャネルとなるｐ型ウェル４を形成する。ウェル４の表面を酸化処理して酸化珪素からなるゲート絶縁膜５を形成した後に、多結晶シリコン／タングステンシリサイドの積層膜を全面に堆積させ、この積層膜を所定のパターンにドライエッチングしてゲート電極６を形成する。   Next, a p-type well 4 serving as a channel of the FET is formed by ion implantation of boron or the like using a resist mask (not shown) formed by photolithography. After the surface of the well 4 is oxidized to form a gate insulating film 5 made of silicon oxide, a polycrystalline silicon / tungsten silicide laminated film is deposited on the entire surface, and this laminated film is dry etched into a predetermined pattern to form a gate. The electrode 6 is formed.

次に、このゲート電極６及びホトリソグラフィによって形成したレジストマスク（図示せず）を用いた、例えばヒ素のイオン注入により、ＭＩＳＦＥＴの半導体領域である低濃度ドレイン領域８ａとなるｎ型領域を形成し、続いて、高濃度拡散層であるソース領域７及び高濃度ドレイン領域８ｂを形成する。   Next, using this gate electrode 6 and a resist mask (not shown) formed by photolithography, for example, arsenic ion implantation is used to form an n-type region to be a low-concentration drain region 8a that is a semiconductor region of the MISFET. Subsequently, a source region 7 and a high concentration drain region 8b, which are high concentration diffusion layers, are formed.

次に半導体基板全面に酸化シリコンからなる絶縁膜１１ａをＣＶＤにより全面に形成し、絶縁膜１１ａ上に堆積させた多結晶シリコンを、ホトリソグラフィによって形成した配線形成領域を覆うレジストマスクを用いたドライエッチングによりパターニングしてシールド電極１２を形成する。この状態を図８に示す。   Next, an insulating film 11a made of silicon oxide is formed on the entire surface of the semiconductor substrate by CVD, and polycrystalline silicon deposited on the insulating film 11a is dried using a resist mask that covers a wiring formation region formed by photolithography. The shield electrode 12 is formed by patterning by etching. This state is shown in FIG.

次に、半導体基板全面に酸化シリコンからなる絶縁膜１１ｂをＣＶＤにより全面に形成し、絶縁膜１１ａ，１１ｂが層間絶縁膜１１となる。この層間絶縁膜１１上に、プラグ形成領域を開口させたレジストマスク２３を形成し、レジストマスク２３を用いたドライエッチングにより所定部分を開口する。この状態を図９に示す。   Next, an insulating film 11b made of silicon oxide is formed on the entire surface of the semiconductor substrate by CVD, and the insulating films 11a and 11b become the interlayer insulating film 11. A resist mask 23 having an opening in the plug formation region is formed on the interlayer insulating film 11 and a predetermined portion is opened by dry etching using the resist mask 23. This state is shown in FIG.

次に、前記開口部分に、プラグ１９，２０，２１，２２となるタングステンを埋め込んだ後に、アルミニュウムを主とした金属膜２４をスパッタ法により全面に堆積させ、ホトリソグラフィによって形成した配線形成領域を覆うレジストマスク２５を形成する。この状態を図１０に示す。   Next, after filling the opening with tungsten to be plugs 19, 20, 21, and 22, a metal film 24 mainly composed of aluminum is deposited on the entire surface by sputtering, and a wiring formation region formed by photolithography is formed. A covering resist mask 25 is formed. This state is shown in FIG.

この後、レジストマスク２５を用いたドライエッチングにより金属膜２４をパターニングして、ゲート配線１７、ソース配線１３、ドレイン配線１８を夫々形成し、併せて夫々の配線の端部にゲート配線１７のボンディングパッド１７ｃ或いはドレイン配線１８のボンディングパッド１８ｃを形成する。この後保護絶縁膜１６によって全面を被覆し、ボンディングパッド１７ｃ，１８ｃの各接続領域を露出させる所定の開口を設けて、半導体基板主面の対向面となる半導体基体１の裏面に、Ａｕを被着する又はＡｕ／Ｔｉ／Ｎｉをスパッタ法により被着しこれを合金化して、裏面電極１５を形成すると図６に示す状態となる。   Thereafter, the metal film 24 is patterned by dry etching using the resist mask 25 to form the gate wiring 17, the source wiring 13, and the drain wiring 18, and bonding of the gate wiring 17 to the end of each wiring. A pad 17c or a bonding pad 18c for the drain wiring 18 is formed. Thereafter, the entire surface is covered with a protective insulating film 16, predetermined openings are provided to expose the connection regions of the bonding pads 17 c and 18 c, and Au is coated on the back surface of the semiconductor substrate 1, which faces the main surface of the semiconductor substrate. When the back electrode 15 is formed by depositing or depositing Au / Ti / Ni by sputtering and alloying it, the state shown in FIG. 6 is obtained.

本実施の形態の半導体装置の製造方法では、また、ゲート配線１７、分岐部１７ａ、連結部１７ｂ、ゲートボンディングパッド１７ｃ、ソース配線１３、分岐部１３ａ及びドレイン配線１８、連結部１８ｂ、ドレインボンディングパッド１８ｃはアルミニュウムを主成分とした同一の金属膜からパターニング形成されており、従来の半導体装置が２層の配線が必要であったのに比べて、配線が１層であるため、工程数を削減することができる。 また、ゲート配線１７、ソース配線１３及びドレイン配線１８とゲート電極６、ソース領域７及び高濃度ドレイン領域８ｂとを、夫々プラグ１９，２０，２１，２２によって接続するため、プラグ１９，２０，２１，２２に、タングステンを用いて、ゲート配線１７、ソース配線１３及びドレイン配線１８とは異種金属とすることにより、エレクトロマイグレーション耐性を向上させることができる。   In the method of manufacturing the semiconductor device according to the present embodiment, the gate wiring 17, the branching portion 17a, the connecting portion 17b, the gate bonding pad 17c, the source wiring 13, the branching portion 13a and the drain wiring 18, the connecting portion 18b, and the drain bonding pad are also used. 18c is formed by patterning from the same metal film mainly composed of aluminum. Compared to the conventional semiconductor device which requires two layers of wiring, the number of processes is reduced because the wiring is one layer. can do. Further, since the gate wiring 17, the source wiring 13 and the drain wiring 18, and the gate electrode 6, the source region 7 and the high concentration drain region 8b are connected by the plugs 19, 20, 21, and 22, respectively, the plugs 19, 20, and 21 are connected. , 22 by using tungsten and making the gate wiring 17, the source wiring 13, and the drain wiring 18 different metals, the electromigration resistance can be improved.

以上、本発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。   Although the present invention has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the scope of the invention. It is.

従来の半導体装置を示す平面図である。It is a top view which shows the conventional semiconductor device. 図１中のａ−ａ線に沿った部分拡大縦断面図である。FIG. 2 is a partially enlarged longitudinal sectional view taken along line aa in FIG. 1. 従来の半導体装置を配線形成する前の状態で示す平面図である。It is a top view shown in the state before forming the wiring of the conventional semiconductor device. 従来の半導体装置を下層の配線層を形成した状態で示す平面図である。It is a top view which shows the conventional semiconductor device in the state which formed the lower wiring layer. 本発明の一実施の形態である半導体装置を示す平面図である。It is a top view which shows the semiconductor device which is one embodiment of this invention. 図５中のａ−ａ線に沿った部分拡大縦断面図である。FIG. 6 is a partially enlarged longitudinal sectional view taken along line aa in FIG. 5. 本発明の一実施の形態である半導体装置を配線形成する前の状態で示す平面図である。It is a top view shown in the state before forming wiring in the semiconductor device which is one embodiment of the present invention. 本発明の一実施の形態である半導体装置を工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process. 本発明の一実施の形態である半導体装置を工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process. 本発明の一実施の形態である半導体装置を工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the semiconductor device which is one embodiment of this invention for every process.

符号の説明Explanation of symbols

１…半導体基体、２…エピタキシャル層、３…分離領域、４…ｐ型ウェル、５…ゲート絶縁膜、６…ゲート電極、７…ソース領域、８ａ…低濃度ドレイン領域、８ｂ…高濃度ドレイン領域、９…ｐ型接続層、１０…コンタクト領域、１１，１６…層間絶縁膜、１２…シールド電極、１３…ソース配線、１４，１８…ドレイン配線、１５…裏面電極、１６…層間絶縁膜（保護絶縁膜）、１７…ゲート配線、１７ａ…分岐部、１７ｂ…連結部、１７ｃ…ゲートボンディングパッド、１８ｂ…連結部、１８ｃ…ドレインボンディングパッド、１９，２０，２１，２２…プラグ、２３，２５…レジストマスク、２４…金属膜

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 3 ... Isolation region, 4 ... P-type well, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... Source region, 8a ... Low concentration drain region, 8b ... High concentration drain region , 9 ... p-type connection layer, 10 ... contact region, 11 and 16 ... interlayer insulating film, 12 ... shield electrode, 13 ... source wiring, 14, 18 ... drain wiring, 15 ... back electrode, 16 ... interlayer insulating film (protection Insulating film), 17 ... Gate wiring, 17a ... Branching part, 17b ... Connecting part, 17c ... Gate bonding pad, 18b ... Connecting part, 18c ... Drain bonding pad, 19, 20, 21, 22 ... Plug, 23, 25 ... Resist mask, 24 ... metal film

Claims (5)

半導体基板主面の活性領域に、ソース領域及びドレイン領域を形成し、半導体基板主面上にゲート電極を形成したＦＥＴを有し、前記ソース領域に隣接して、半導体基板内で導通する接続層を形成する半導体装置において、
前記ソース領域、ドレイン領域、ゲート電極、接続層は、単一の連続した活性領域内に、縦方向に連続して延在するストライプ状に形成し、前記半導体基板主面を覆う層間絶縁膜上には、縦方向に活性領域上を連続して延在するゲート配線、ドレイン配線を形成し、
前記ゲート配線は、前記接続層上に配置し、複数箇所で横方向に分岐するゲート配線の分岐部と前記ゲート電極とをプラグによって接続し、前記ドレイン配線は、前記ドレイン領域上に配置し、ドレイン配線とドレイン領域とは、活性領域の略全域に連続するプラグによって接続し、前記ソース配線は、前記ゲート配線とゲート電極との間に、ゲート配線の分岐部間に分割して配置し、ソース配線は、プラグによってソース領域及び接続層に接続することを特徴とする半導体装置。 A connection layer having an FET in which a source region and a drain region are formed in an active region of a main surface of a semiconductor substrate and a gate electrode is formed on the main surface of the semiconductor substrate, and is electrically connected in the semiconductor substrate adjacent to the source region In a semiconductor device for forming
The source region, the drain region, the gate electrode, and the connection layer are formed in a single continuous active region in a stripe shape extending continuously in the vertical direction, and on an interlayer insulating film that covers the main surface of the semiconductor substrate Forming a gate wiring and a drain wiring continuously extending in the vertical direction on the active region,
The gate wiring is disposed on the connection layer, the branch portion of the gate wiring branching in a lateral direction at a plurality of locations and the gate electrode are connected by a plug, and the drain wiring is disposed on the drain region, The drain wiring and the drain region are connected by a continuous plug over substantially the entire active region, and the source wiring is arranged between the gate wiring and the gate electrode and divided between the branch portions of the gate wiring, A semiconductor device, wherein a source wiring is connected to a source region and a connection layer by a plug. 前記ドレイン配線、ソース配線、ゲート配線はアルミニュウムを主成分とした同一の金属膜からパターニング形成し、前記プラグにはタングステンを用いることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the drain wiring, the source wiring, and the gate wiring are formed by patterning from the same metal film mainly composed of aluminum, and tungsten is used for the plug. 前記ゲート電極とドレイン配線との間の層間絶縁膜中には、ソース配線と接続するシールド電極を形成することを特徴とする請求項１又は請求項２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein a shield electrode connected to the source wiring is formed in the interlayer insulating film between the gate electrode and the drain wiring. 縦方向に延在する複数の前記ゲート配線を横方向に延在する連結部によって並列接続し、縦方向に延在する複数の前記ドレイン配線を横方向に延在する連結部によって並列接続し、夫々の連結部にはボンディングパッドを形成し、ソース領域は、半導体基板裏面に形成された裏面電極に電気的に接続してあることを特徴とする請求項１乃至請求項３の何れか一項に記載の半導体装置。 A plurality of the gate wirings extending in the vertical direction are connected in parallel by a connecting portion extending in the horizontal direction, and a plurality of the drain wirings extending in the vertical direction are connected in parallel by a connecting portion extending in the horizontal direction, 4. The bonding pad is formed in each of the connecting portions, and the source region is electrically connected to a back electrode formed on the back surface of the semiconductor substrate. 5. A semiconductor device according to 1. 半導体基板主面の活性領域に、ソース領域及びドレイン領域を形成し、半導体基板主面上にゲート電極を形成したＦＥＴを有し、前記ソース領域に隣接して、半導体基板内で導通する接続層を形成する半導体装置の製造方法において、
前記ソース領域、ドレイン領域、ゲート電極、接続層を、単一の連続した活性領域内に、縦方向に連続して延在するストライプ状に形成する工程と、
前記半導体基板主面を覆う層間絶縁膜を形成し、ゲート電極と接続するプラグ、ドレイン領域と、活性領域の略全域に連続するプラグ、ソース領域及び接続層に接続するプラグを夫々形成する工程と、
層間絶縁膜上に、縦方向に活性領域上を連続して延在するゲート配線、ドレイン配線を形成する工程とを有し、
前記ゲート配線は、前記接続層上に配置し、複数箇所で横方向に分岐する分岐部が前記ゲート電極と接続するプラグに接続し、前記ドレイン配線は、前記ドレイン領域上に配置し、ドレイン領域と接続するプラグに接続し、前記ソース配線は、前記ゲート配線とゲート電極との間に、ゲート配線の分岐部間に分割して配置し、ソース配線は、ソース領域及び接続層に接続するプラグに接続することを特徴とする半導体装置の製造方法。

A connection layer having an FET in which a source region and a drain region are formed in an active region of a main surface of a semiconductor substrate and a gate electrode is formed on the main surface of the semiconductor substrate, and is electrically connected in the semiconductor substrate adjacent to the source region In the manufacturing method of the semiconductor device forming
Forming the source region, the drain region, the gate electrode, and the connection layer in a single continuous active region in a stripe shape extending continuously in a vertical direction;
Forming an interlayer insulating film covering the main surface of the semiconductor substrate, and forming a plug connected to the gate electrode, a drain region, a plug continuous over substantially the entire active region, and a plug connected to the source region and the connection layer; ,
Forming a gate wiring and a drain wiring continuously extending on the active region in the vertical direction on the interlayer insulating film;
The gate wiring is disposed on the connection layer, branch portions branching laterally at a plurality of locations are connected to plugs connected to the gate electrode, and the drain wiring is disposed on the drain region, The source wiring is divided between the gate wiring and the gate electrode and divided between the branch portions of the gate wiring, and the source wiring is a plug connected to the source region and the connection layer. A method for manufacturing a semiconductor device, comprising: connecting to a semiconductor device.

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Cited By (4)

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JP2008263136A (en) * 2007-04-13 2008-10-30 Denso Corp Semiconductor device
CN109755218A (en) * 2017-11-01 2019-05-14 三星电子株式会社 Semiconductor devices including contact plunger and the method for forming it
CN117558749A (en) * 2024-01-11 2024-02-13 英诺赛科（珠海）科技有限公司 Gallium nitride device structure
CN117558749B (en) * 2024-01-11 2024-05-03 英诺赛科（珠海）科技有限公司 Gallium nitride device structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008263136A (en) * 2007-04-13 2008-10-30 Denso Corp Semiconductor device
CN109755218A (en) * 2017-11-01 2019-05-14 三星电子株式会社 Semiconductor devices including contact plunger and the method for forming it
US11721581B2 (en) 2017-11-01 2023-08-08 Samsung Electronics Co., Ltd. Semiconductor devices including contact plugs
CN109755218B (en) * 2017-11-01 2024-03-08 三星电子株式会社 Semiconductor device including contact plug and method of forming the same
CN117558749A (en) * 2024-01-11 2024-02-13 英诺赛科（珠海）科技有限公司 Gallium nitride device structure
CN117558749B (en) * 2024-01-11 2024-05-03 英诺赛科（珠海）科技有限公司 Gallium nitride device structure

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