JP2011250361A - High frequency module and method for operating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency module capable of avoiding bias-jump at high temperature current-carrying time and commonalizing of a external power source regardless of products in actual operation, and reducing the number of terminals.SOLUTION: The high frequency module 1 comprises: a semiconductor device 24; an input matching circuit 17; an output matching circuit 18; a gate bias circuit 70 for actual operation; a gate bias terminal 41a for actual operation connected to the gate bias circuit 70 for actual operation; a gate bias terminal 21a doubling as a high frequency input terminal, for high temperature operation and connected to the input matching circuit 17; a drain bias circuit 80 connected to the output matching circuit 18; a drain bias terminal 41b connected to the drain bias circuit 80; and a high frequency output terminal 21b connected to the output matching circuit 18; and is housed in one package. The method for operating the high frequency module is provided.

Description

  Embodiments described herein relate generally to a high-frequency module and an operation method thereof.

  In recent years, high-frequency semiconductor devices have been applied to small-sized and high-performance mobile phones, and have been rapidly spreading. Development of high-performance field effect transistors is a technology that has greatly contributed to this advance. High-performance field-effect transistors exhibit excellent performance in high-frequency characteristics such as low-voltage operation, high gain, high efficiency, low noise, and low distortion, and are applied as transmission / reception amplifiers for mobile terminals (for example, (See Patent Document 1).

Japanese Patent Laid-Open No. 10-327028

  In a conventional high-frequency semiconductor device, an external power supply is made common regardless of products, and therefore a gate voltage is supplied to the gate terminal of the high-frequency semiconductor device via a bleeder resistance circuit.

  However, since a resistance is inserted between the gate power supply and the gate terminal of the high-frequency semiconductor device, the gate bias voltage decreases when the gate leakage current increases during high-temperature operation. When the value of the gate bias voltage decreases, the drain current increases, and a phenomenon called a so-called bias jump occurs in which the temperature of the high-frequency semiconductor device further increases due to self-heating. For this reason, in the conventional high frequency semiconductor device, there is a problem that a high-temperature energization test is difficult.

  According to one aspect, the semiconductor device, the input matching circuit disposed on the input side of the semiconductor device, the output matching circuit disposed on the output side of the semiconductor device, and the operation time connected to the input matching circuit Gate bias circuit for operation, gate bias terminal for operation connected to the gate bias circuit for operation, high-frequency input terminal connected to the input matching circuit and gate bias terminal for high temperature operation, and the output matching circuit A drain bias circuit connected to the drain bias circuit, a drain bias terminal connected to the drain bias circuit, and a high frequency output terminal connected to the output matching circuit, the semiconductor device, the input matching circuit, and the output High-frequency module in which matching circuit, gate bias circuit for operation, and drain bias circuit are housed in one package Frequency module is provided.

  According to another aspect, the semiconductor device, the input matching circuit disposed on the input side of the semiconductor device, the output matching circuit disposed on the output side of the semiconductor device, and the operation connected to the input matching circuit A gate bias terminal for operation, a gate bias terminal for operation connected to the gate bias circuit for operation, a high-frequency input terminal connected to the input matching circuit and a gate bias terminal for high temperature operation, and the output matching A drain bias circuit connected to the circuit, a drain bias terminal connected to the drain bias circuit, and a high frequency output terminal connected to the output matching circuit, the semiconductor device, the input matching circuit, The output matching circuit, the operation gate bias circuit, and the drain bias circuit are housed in one package. A method of controlling the potential of the gate terminal electrode of the semiconductor device through the gate bias circuit for operation during operation, and for the high-frequency input terminal and high-temperature operation during operation. A step of supplying an input signal to the semiconductor device via a DC blocking capacitor connected to the outside of the gate bias terminal; and a gate bias voltage applied to the high frequency input terminal and the gate bias terminal for high temperature operation during high temperature operation. To provide a method of operating a high-frequency module including a step of controlling a potential of a gate terminal electrode of the semiconductor device.

1 is a schematic bird's-eye view configuration of a package mounting a high-frequency module according to an embodiment, on (a) a metal cap, (b) a metal seal ring, (c) a metal wall, (d) a conductor base plate, and an insulating layer The schematic block diagram of the arrange | positioned stripline. The typical plane block diagram of the high frequency module which concerns on embodiment. It is typical sectional structure of the high frequency module concerning an embodiment, and is a typical section structure figure which meets an II line of Drawing 2. It is typical sectional structure of the high frequency module concerning an embodiment, and is a typical section structure figure which meets the II-II line of Drawing 2. It is typical sectional structure of the high frequency module concerning an embodiment, and is a typical section structure figure which meets the III-III line of Drawing 2. The typical circuit block diagram of the high frequency module which concerns on embodiment. (A) In the high-frequency module according to the embodiment, an enlarged view of a schematic planar pattern configuration of a semiconductor device, (b) an enlarged view of a portion J in FIG. FIG. 8 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 7B, which is the first structural example of the semiconductor device applied to the high-frequency module according to the embodiment. FIG. 8 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 7B, which is a second example of the structure of the semiconductor device applied to the high-frequency module according to the embodiment. 8 is a structural example 3 of a semiconductor device applied to the high-frequency module according to the embodiment and is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. FIG. 8 is a schematic cross-sectional structure diagram taken along line IV-IV in FIG. 7B, which is a fourth structural example of the semiconductor device applied to the high-frequency module according to the embodiment.

  Next, embodiments will be described with reference to the drawings. In the following, the same elements are denoted by the same reference numerals to avoid duplication of explanation and to simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The embodiment described below exemplifies an apparatus and a method for embodying the technical idea, and the embodiment does not specify the arrangement of each component as described below. This embodiment can be modified in various ways within the scope of the claims.

[First embodiment]
(Package structure)
As shown in FIG. 1, the package mounting the high-frequency module 1 according to the embodiment is disposed on the metal cap 10, the metal seal ring 14 a, the metal wall 16, the conductor base plate 200, and the conductor base plate 200. Input side insulating layers 20a and 40a, output side insulating layers 20b and 40b disposed on the conductor base plate 200, input stripline 19a disposed on the input side insulating layer 20a, and disposed on the output side insulating layer 20b The output strip line 19b, the input strip line 39a disposed on the input side insulating layer 40a, and the output strip line 39b disposed on the output side insulating layer 40b are provided.

-Conductor base plate 200-
The conductor base plate 200 is made of, for example, a conductive metal such as molybdenum or a copper molybdenum alloy. Furthermore, a plated conductor such as Au, Ni, Ag, Ag—Pt alloy, or Ag—Pd alloy may be formed on the surface of the conductor base plate 200. The conductor base plate 200 may have a laminated structure such as a Cu / Mo / alumina substrate.

―Metal wall 16―
For example, the metal wall 16 is made of a conductive metal such as aluminum, molybdenum, or copper molybdenum alloy.

  A solder metal layer (not shown) for soldering is formed on the upper surface of the metal wall 16 via a metal seal ring 14a. The solder metal layer can be formed from, for example, a gold germanium alloy, a gold tin alloy, or the like.

  The metal wall 16 is disposed on the conductor base plate 200 via an insulating or conductive adhesive. In addition, the metal wall 16 is arrange | positioned on the convex feedthrough upper layer part 22 (refer FIG. 3) in a feedthrough part. The convex feedthrough upper layer portion 22 is disposed on the input-side insulating layers 20a and 40a and the output-side insulating layers 20b and 40b, and is formed of an insulating layer. In FIG. 1, the convex feedthrough upper layer portion 22 is not shown. Here, the input side insulating layers 20a and 40a and the output side insulating layers 20b and 40b correspond to a feedthrough lower layer. The insulating adhesive can be formed from, for example, an epoxy resin or glass, and the conductive adhesive can be formed from, for example, a gold germanium alloy or a gold-tin alloy.

―Metal cap 10―
As shown in FIG. 1, the metal cap 10 has a flat plate shape.

  The metal cap 10 is disposed on the metal wall 16 via the metal seal ring 14a.

  The package on which the high frequency module 1 according to the embodiment is mounted has high frequency characteristics of 3 GHz or more. For this reason, it can be applied as a package for devices and components having a high frequency (that is, a frequency exceeding 3 GHz).

(High frequency module)
-Planar pattern configuration-
A schematic planar pattern configuration of the high-frequency module 1 according to the embodiment is represented as shown in FIG. 2, and a schematic cross-sectional structure taken along line II in FIG. 2 is represented as shown in FIG. A schematic cross-sectional structure taken along line II-II is represented as shown in FIG. 4, and a schematic cross-sectional structure taken along line III-III in FIG. 2 is represented as shown in FIG.

  As shown in FIGS. 1 to 5, the high-frequency module 1 according to the embodiment includes a semiconductor device 24 disposed on a conductor base plate 200 and an input circuit disposed on an input portion of the semiconductor device 24 on the conductor base plate 200. A substrate 26 and an output circuit substrate 28 disposed in the output portion of the semiconductor device 24 on the conductor base plate 200 are provided.

  An input matching circuit 17 and a bleeder resistance circuit 50 are disposed on the input circuit board 26. An output matching circuit 18 and an electrode pattern 27 are disposed on the output circuit board 28.

  The input matching circuit 17 is connected to the gate terminal electrode G of the semiconductor device 24 via the bonding wire 12, and the output matching circuit 18 is connected to the drain terminal electrode D of the semiconductor device 24 via the bonding wire 14. Yes.

  The input strip line 19a is connected to a high-frequency input terminal and gate bias terminal 21a for high-temperature operation, and the output strip line 19b is connected to a high-frequency output terminal 21b.

  The high frequency input terminal / high temperature operation gate bias terminal 21 a is connected to the gate terminal electrode G of the semiconductor device 24 through the input strip line 19 a, the bonding wire 11, and the input matching circuit 17.

  Further, a DC blocking capacitor C1 may be externally connected to the high frequency input terminal / high temperature operation gate bias terminal 21a.

  An operating gate bias terminal 41a is connected to the stripline 39a.

  A drain bias terminal 41b is connected to the strip line 39b.

  The strip line 39a is connected to the bleeder resistance circuit 50 through the bonding wire 11b. The bleeder resistance circuit 50 is connected to the input matching circuit 17 through the bonding wire 11e, and is connected to the ground potential through the bonding wire 11c.

  The output strip line 19b is connected to one electrode of the DC blocking capacitor C2 via the bonding wire 15, and the other electrode of the DC blocking capacitor C2 is connected to the output matching circuit 18.

  The strip line 39b is connected to the electrode pattern 27 via the bonding wire 15b, and the electrode pattern 27 is connected to the output matching circuit 18 via the bonding wire 15a. As a result, the drain bias terminal 41b is connected to the drain terminal electrode D of the semiconductor device 24 via the strip line 39b, the bonding wire 15b, the electrode pattern 27, the bonding wire 15a, and the output matching circuit 18. Yes. During high-temperature operation / operation, the potential of the drain terminal electrode D of the semiconductor device 24 can be directly controlled by the voltage supplied to the drain bias terminal 41b. The source terminal electrode S of the semiconductor device 24 is connected to the ground potential.

―Circuit configuration―
As shown in FIG. 6, a schematic circuit configuration of the high-frequency module 1 according to the embodiment includes a semiconductor device 24, an input matching circuit 17 disposed on the input side of the semiconductor device 24, and an output side of the semiconductor device 24. The output matching circuit 18 arranged, the operation gate bias circuit 70 connected to the input matching circuit 17, the operation gate bias terminal 41a connected to the operation gate bias circuit 70, and the input matching circuit 17 A high-frequency input terminal and high-temperature gate bias terminal 21a connected to the drain bias circuit 80 connected to the output matching circuit 18, a drain bias terminal 41b connected to the drain bias circuit 80, and the output matching circuit 18 And a high frequency output terminal 21b connected to the. The semiconductor device 24, the input matching circuit 17, the output matching circuit 18, the operation gate bias circuit 70, and the drain bias circuit 80 are accommodated in one package surrounded by the metal wall 16.

  The operational gate bias circuit 70 includes a bleeder resistance circuit 50, and the operational gate bias terminal 41 a is connected to the gate terminal electrode G of the semiconductor device 24 through the bleeder resistance circuit 50.

  The bleeder resistance circuit 50 includes a bleeder resistor 56 connected to the operating gate bias terminal 41a, and a bleeder resistor 58 connected in series between the bleeder resistor 56 and the ground potential, and an operating gate bias. The voltage supplied to the terminal 41 a is applied to the gate terminal electrode G of the semiconductor device 24 by the resistance voltage division between the bleeder resistor 56 and the bleeder resistor 58.

  Also, one electrode of the DC blocking capacitor 52 (C1) is connected to the outside of the high frequency input terminal / high temperature operation gate bias terminal 21a, and the other electrode of the DC blocking capacitor 52 (C1) is connected to the high frequency input. It connects to the input terminal 21i for introducing a signal. As a result, an input signal is supplied to the semiconductor device 24 by supplying a high frequency input signal to the input terminal 21i. For high temperature operation, a semiconductor device is provided via the input stripline 19a, the bonding wire 11 and the input matching circuit 17 by supplying a gate bias voltage to the high frequency input terminal / high temperature operation gate bias terminal 21a. The potentials of the 24 gate terminal electrodes G can be directly controlled.

  In the high-frequency module 1 according to the embodiment, the potential of the gate terminal electrode G of the semiconductor device 24 can be directly controlled by the voltage supplied to the high-frequency input terminal / high-temperature operation gate bias terminal 21a during high-temperature operation. ing. That is, since the high frequency input terminal and the gate bias terminal for high temperature operation can be shared, the number of terminals can be reduced and the configuration of the high frequency module 1 can be simplified.

  Furthermore, the high frequency module according to a user's use can be provided by setting it as the structure which can connect the capacitor C1 for DC interruption | blocking externally.

  The drain bias circuit 80 includes bonding wires 15 a and 15 b and an electrode pattern 27, and the drain bias terminal 41 b is connected to the drain terminal electrode D of the semiconductor device 24 through the drain bias circuit 80.

  A voltage supplied to the drain bias terminal 41 b is applied to the drain terminal electrode D of the semiconductor device 24.

  A DC blocking capacitor 54 (C2) is connected between the high frequency output terminal 21b and the output matching circuit 18.

(High-frequency module operation method)
Semiconductor device 24, input matching circuit 17 disposed on the input side of semiconductor device 24, output matching circuit 18 disposed on the output side of semiconductor device 24, and gate bias for operation connected to input matching circuit 17 A circuit 70; an operation gate bias terminal 41a connected to the operation gate bias circuit 70; a high frequency input terminal / high temperature operation gate bias terminal 21a connected to the input matching circuit 17; and an output matching circuit 18. A drain bias circuit 80 connected to the drain bias circuit 80, a drain bias terminal 41 b connected to the drain bias circuit 80, and a high frequency output terminal 21 b connected to the output matching circuit 18. The semiconductor device 24 and the input matching circuit 17 The output matching circuit 18, the gate bias circuit for operation 70, and the drain bias circuit 80 in one package. The operation method of the housed high-frequency module includes a step of controlling the potential of the gate terminal electrode G of the semiconductor device 24 via the operation gate bias circuit 70 during operation, and a high-frequency input terminal-high temperature operation during operation. A step of supplying an input signal to the semiconductor device 24 via a DC blocking capacitor 52 (C1) connected to the outside of the gate bias terminal for operation 21a, and a high frequency input terminal for high temperature operation during high temperature operation Controlling the potential of the gate terminal electrode G of the semiconductor device 24 by supplying a gate bias voltage to the gate bias terminal 21a.

  The gate bias circuit for operation 70 includes a bleeder resistance circuit 50, and the potential of the gate terminal electrode G of the semiconductor device 24 may be controlled via the bleeder resistance circuit 50 during operation.

  The high-frequency module 1 according to the embodiment uses a high-frequency input terminal and high-temperature operation gate bias terminal 21 a connected to the gate terminal electrode G of the semiconductor device 24 without using a bleeder resistance circuit during high-temperature energization. , Bias jump can be avoided.

  In addition, the high-frequency module 1 according to the embodiment uses an operational gate bias terminal 41a connected to the gate terminal electrode G of the semiconductor device 24 via the bleeder resistance circuit 50 in actual operation, thereby enabling an external power supply. Can be made common regardless of the product.

  According to the embodiment, at the time of high temperature energization, the bias jump is achieved by using the high frequency input terminal and high temperature operation gate bias terminal 21a connected to the gate terminal electrode G of the semiconductor device 24 without using the bleeder resistance circuit. In actual operation, by using the gate bias terminal 41a for operation connected to the gate terminal electrode G of the semiconductor device 24 through the bleeder resistance circuit 50, the external power source can be used regardless of the product. It is possible to provide a semiconductor module applicable to high frequencies in the microwave / millimeter wave / submillimeter wave band and an operation method thereof that can be shared.

(Configuration of semiconductor device)
An enlarged view of a schematic planar pattern configuration of the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment is represented as shown in FIG. 7A, and an enlarged view of a portion J in FIG. It is expressed as shown in FIG. Moreover, it is the structural examples 1-4 of the semiconductor device 24 applied to the high frequency module 1 which concerns on embodiment, Comprising: Typical sectional structure examples 1-4 along the IV-IV line of FIG.7 (b) are respectively figures. 8 to 11 are shown.

  In the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment, the plurality of FET cells FET1 to FET10 include the semi-insulating substrate 110 and the first of the semi-insulating substrate 110 as shown in FIGS. A gate finger electrode 124, a source finger electrode 120, and a drain finger electrode 122, each having a plurality of fingers, disposed on the surface, and disposed on a first surface of the semi-insulating substrate 110, the gate finger electrode 124, the source finger electrode 120, and A plurality of gate terminal electrodes G1, G2,..., G10 formed by bundling a plurality of fingers for each drain finger electrode 122, a plurality of source terminal electrodes S11, S12, S21, S22,. D1, D2, ..., D10 and source VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 disposed below the child electrodes S11, S12, S21, S22,..., S101, S102, and the side opposite to the first surface of the semi-insulating substrate 110. , And ground terminals connected to the source terminal electrodes S11, S12, S21, S22,..., S101, S102 through the VIA holes SC11, SC12, SC21, SC22,. (Not shown).

  The bonding wire 12 is connected to the gate terminal electrodes G1, G2,..., G10, the bonding wire 14 is connected to the drain terminal electrodes D1, D2,..., D10, and the source terminal electrodes S11, S12, S21, S22. ,..., S101, S102, VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 are formed on the inner walls of the VIA holes SC11, SC12, SC21, SC22,. The source terminal electrodes S11, S12, S21, S22,..., S101, S102 are formed on the barrier metal layer (not shown) and the filling metal layer (not shown) that is formed on the barrier metal layer and fills the VIA hole. Connected to the ground electrode.

  The semi-insulating substrate 110 is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or One of the diamond substrates.

―Structure Example 1―
As a schematic cross-sectional configuration along line IV-IV in FIG. 7B, the structure example 1 of the FET cell of the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment is semi-insulating as shown in FIG. Substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x N) disposed on nitride-based compound semiconductor layer 112 ( 0.1 ≦ x ≦ 1) 118 and source finger electrode 120, gate finger electrode 124, and drain disposed on aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118 A finger electrode 122. A two-dimensional electron gas (2DEG) layer is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. 116 is formed. In Structural Example 1 shown in FIG. 8, a heterojunction field effect transistor (HFET) or a high electron mobility transistor (HEMT) is shown.

-Structural example 2-
As a schematic cross-sectional configuration taken along line IV-IV in FIG. 7B, the structure example 2 of the FET cell of the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment is semi-insulating as shown in FIG. On the conductive substrate 110, the nitride-based compound semiconductor layer 112 disposed on the semi-insulating substrate 110, the source region 126 and the drain region 128 disposed on the nitride-based compound semiconductor layer 112, and the source region 126. The source finger electrode 120 is disposed, the gate finger electrode 124 is disposed on the nitride compound semiconductor layer 112, and the drain finger electrode 122 is disposed on the drain region 128. A Schottky contact is formed at the interface between the nitride-based compound semiconductor layer 112 and the gate finger electrode 124. In Structural Example 2 shown in FIG. 9, a metal-semiconductor field effect transistor (MESFET) is shown.

―Structure Example 3―
As a schematic cross-sectional configuration taken along line IV-IV in FIG. 7B, the structure example 3 of the FET cell of the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment is semi-insulating as shown in FIG. Substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x N) disposed on nitride-based compound semiconductor layer 112 ( 0.1 ≦ x ≦ 1) 118, a source finger electrode 120 and a drain finger electrode 122 disposed on an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, And a gate finger electrode 124 disposed in a recess portion on an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 3 shown in FIG. 10, an HFET or HEMT is shown.

-Structural example 4-
As a schematic cross-sectional configuration taken along line IV-IV in FIG. 7B, the structure example 4 of the FET cell of the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment is semi-insulating as shown in FIG. Substrate 110, nitride-based compound semiconductor layer 112 disposed on semi-insulating substrate 110, and an aluminum gallium nitride layer (Al _x Ga _1-x N) disposed on nitride-based compound semiconductor layer 112 ( 0.1 ≦ x ≦ 1) 118, a source finger electrode 120 and a drain finger electrode 122 disposed on an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118, And a gate finger electrode 124 disposed in a two-stage recess portion on an aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. A 2DEG layer 116 is formed at the interface between the nitride-based compound semiconductor layer 112 and the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 118. In Structural Example 4 shown in FIG. 11, an HFET or HEMT is shown.

  In Structural Examples 1 to 4, the nitride-based compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region. Here, the active region refers to the 2DEG layer 116 immediately below the source finger electrode 120, the gate finger electrode 124, and the drain finger electrode 122, between the source finger electrode 120 and the gate finger electrode 124, and between the drain finger electrode 122 and the gate finger electrode 124. 2 DEG layer 116. In the structural examples 1 to 4, the nitride compound semiconductor layer 112 other than the active region is used as an electrically inactive element isolation region.

As another method for forming the element isolation region, the aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1) 18 and a part of the nitride-based compound semiconductor layer 112 in the depth direction are used. It can also be formed by ion implantation. As the ion species, for example, nitrogen (N), argon (Ar), or the like can be applied. The dose accompanying ion implantation is, for example, about 1 × 10 ¹⁴ (ions / cm ² ), and the acceleration energy is, for example, about 100 keV to 200 keV.

A passivation insulating layer (not shown) is formed on the element isolation region and the device surface. As this insulating layer, for example, a nitride film, an alumina (Al ₂ O ₃ ) film, an oxide film (SiO ₂ ), an oxynitride film (SiON) or the like deposited by PECVD (Plasma Enhanced Chemical Vapor Deposition) method is formed. be able to.

  The source finger electrode 120 and the drain finger electrode 122 are made of, for example, Ti / Al. The gate finger electrode 124 can be formed of, for example, Ni / Au.

  In the semiconductor device 24 applied to the high-frequency module 1 according to the embodiment, the longitudinal pattern lengths of the gate finger electrode 124, the source finger electrode 120, and the drain finger electrode 122 operate as microwave / millimeter wave / submillimeter wave. The frequency is set shorter as the frequency becomes higher. For example, in the millimeter wave band, the pattern length is about 25 μm to 50 μm.

  Further, the width of the source finger electrode 120 is, for example, about 40 μm, and the width of the source terminal electrodes S11, S12, S21, S22,..., S101, S102 is, for example, about 100 μm. Further, the formation width of the VIA holes SC11, SC12, SC21, SC22,..., SC101, SC102 is, for example, about 10 μm to 40 μm.

[Other embodiments]
As described above, the embodiments have been described, but the descriptions and drawings forming a part of this disclosure are illustrative and should not be understood as limiting. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The discrete transistors applied to the high-frequency semiconductor device according to the embodiment are not limited to FETs, HFETs, and HEMTs, but are LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors) and heterojunction bipolar transistors (HBTs). Needless to say, an amplifying element such as a junction bipolar transistor (MEMS) or a micro electro mechanical systems (MEMS) element can also be applied.

As described above, various embodiments that are not described herein are included.

DESCRIPTION OF SYMBOLS 1 ... High frequency module 10 ... Metal cap 11, 11b, 11c, 11e, 12, 14, 15, 15a, 15b ... Bonding wire 14a ... Metal seal ring 16 ... Metal wall 17 ... Input matching circuit 18 ... Output matching circuit 19a, 39a ... input strip lines 19b, 39b ... output strip lines 20a, 40a ... input-side insulating layers 20b, 40b ... output-side insulating layers 21a ... high-frequency input terminals and high-temperature operation gate bias terminals 21b ... high-frequency output terminals 22 ... feed through upper layers Unit 24 ... Semiconductor device 27 ... Electrode pattern 26 ... Input circuit board 28 ... Output circuit board 41a ... Operational gate bias terminal 41b ... Drain bias terminal 50 ... Bleeder resistance circuit 52, 54 ... DC blocking capacitors 56, 58 ... Bleeder Resistor 70: Gate bias times for operation 80 ... drain bias circuit 110 ... semi-insulating substrate 112 ... nitride compound semiconductor layer (GaN epitaxial layer)
116: Two-dimensional electron gas (2DEG) layer 118: Aluminum gallium nitride layer (Al _x Ga _1-x N) (0.1 ≦ x ≦ 1)
120 ... Source finger electrode 122 ... Drain finger electrode 124 ... Gate finger electrode 126 ... Source region 128 ... Drain region 200 ... Conductor base plates G, G1, G2, ..., G10 ... Gate terminal electrodes S, S11, S12, ..., S101, S102 ... Source terminal electrodes D, D1, D2, ..., D10 ... Drain terminal electrodes SC11, SC12, ..., SC91, SC92, SC101, SC102 ... VIA holes

Claims (12)

A semiconductor device;
An input matching circuit disposed on the input side of the semiconductor device;
An output matching circuit disposed on the output side of the semiconductor device;
An operational gate bias circuit connected to the input matching circuit;
An operational gate bias terminal connected to the operational gate bias circuit;
A high-frequency input terminal connected to the input matching circuit and a gate bias terminal for high-temperature operation;
A drain bias circuit connected to the output matching circuit;
A drain bias terminal connected to the drain bias circuit;
A high-frequency output terminal connected to the output matching circuit, and the semiconductor device, the input matching circuit, the output matching circuit, the gate bias circuit for operation, and the drain bias circuit in one package A high-frequency module that is housed in a housing.   The operation gate bias circuit includes a bleeder resistance circuit, and the operation gate bias terminal is connected to the gate terminal of the semiconductor device via the bleeder resistance circuit. The high-frequency module described.   2. The high frequency module according to claim 1, further comprising a DC blocking capacitor connected to the outside of the high frequency input terminal and gate bias terminal for high temperature operation.   An input signal is supplied to the semiconductor device through the DC blocking capacitor, and a gate bias voltage is supplied to the high-frequency input terminal and the gate bias terminal for high-temperature operation during high-temperature operation, whereby the semiconductor The high-frequency module according to claim 1, wherein the potential of the gate terminal electrode of the device is controlled. The high-frequency module according to claim 1, wherein the drain bias circuit includes an electrode pattern, and the drain bias terminal is connected to the drain terminal of the semiconductor device via the electrode pattern. The bleeder resistance circuit is:
A first bleeder resistor connected to the second gate bias terminal;
A second bleeder resistor connected in series between the first bleeder resistor and a ground potential, and the voltage supplied to the second gate bias terminal is the first bleeder resistor and the second bleeder resistor. The high-frequency module according to claim 2, wherein the high-frequency module is applied to the gate terminal of the semiconductor device by resistance voltage division.   The high-frequency module according to claim 4, wherein a voltage supplied to the drain bias terminal is applied to the drain terminal of the semiconductor device.   The high frequency module according to claim 1, further comprising a DC blocking capacitor connected between the high frequency output terminal and the output matching circuit. The semiconductor device includes:
A semi-insulating substrate;
A gate finger electrode, a source finger electrode and a drain finger electrode disposed on the first surface of the semi-insulating substrate, each having a plurality of fingers;
A plurality of gate terminal electrodes arranged on the first surface of the semi-insulating substrate and formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode; A drain terminal electrode;
A VIA hole disposed under the source terminal electrode;
2. A ground electrode disposed on a second surface opposite to the first surface of the semi-insulating substrate and connected to the source terminal electrode via the VIA hole. 9. The high frequency module according to any one of 8 above.   The semi-insulating substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on a SiC substrate, a sapphire substrate, or The high-frequency module according to claim 9, wherein the high-frequency module is a diamond substrate. A semiconductor device; an input matching circuit disposed on the input side of the semiconductor device; an output matching circuit disposed on the output side of the semiconductor device; and an operational gate bias circuit connected to the input matching circuit; A gate bias terminal for operation connected to the gate bias circuit for operation, a high-frequency input terminal connected to the input matching circuit and a gate bias terminal for high temperature operation, and a drain bias connected to the output matching circuit A circuit, a drain bias terminal connected to the drain bias circuit, and a high frequency output terminal connected to the output matching circuit, the semiconductor device, the input matching circuit, the output matching circuit, This is a method of operating a high-frequency module in which the gate bias circuit for operation and the drain bias circuit are housed in one package. ,
In operation, the step of controlling the potential of the gate terminal electrode of the semiconductor device through the gate bias circuit for operation;
In operation, supplying an input signal to the semiconductor device through a DC blocking capacitor connected to the outside of the high-frequency input terminal and high-temperature operation gate bias terminal;
And a step of controlling a potential of a gate terminal electrode of the semiconductor device by supplying a gate bias voltage to the high-frequency input terminal and a gate bias terminal for high-temperature operation during high-temperature operation. How it works.   12. The gate bias circuit for operation has a bleeder resistance circuit, and controls the potential of the gate terminal electrode of the semiconductor device through the bleeder resistance circuit during operation. Operation method of high frequency module.