JP2010021416A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2010021416A
JP2010021416A JP2008181456A JP2008181456A JP2010021416A JP 2010021416 A JP2010021416 A JP 2010021416A JP 2008181456 A JP2008181456 A JP 2008181456A JP 2008181456 A JP2008181456 A JP 2008181456A JP 2010021416 A JP2010021416 A JP 2010021416A
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JP
Japan
Prior art keywords
resist pattern
semiconductor substrate
main surface
ions
forming
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Pending
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JP2008181456A
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English (en)
Japanese (ja)
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JP2010021416A5 (cg-RX-API-DMAC10.html
Inventor
Kazuya Kamon
和也 加門
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2008181456A priority Critical patent/JP2010021416A/ja
Publication of JP2010021416A publication Critical patent/JP2010021416A/ja
Publication of JP2010021416A5 publication Critical patent/JP2010021416A5/ja
Pending legal-status Critical Current

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2008181456A 2008-07-11 2008-07-11 半導体装置の製造方法 Pending JP2010021416A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008181456A JP2010021416A (ja) 2008-07-11 2008-07-11 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008181456A JP2010021416A (ja) 2008-07-11 2008-07-11 半導体装置の製造方法

Publications (2)

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JP2010021416A true JP2010021416A (ja) 2010-01-28
JP2010021416A5 JP2010021416A5 (cg-RX-API-DMAC10.html) 2011-08-25

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JP2008181456A Pending JP2010021416A (ja) 2008-07-11 2008-07-11 半導体装置の製造方法

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JP (1) JP2010021416A (cg-RX-API-DMAC10.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019067480A (ja) * 2013-03-14 2019-04-25 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 高度ナノメートルフラッシュメモリ装置において使用される改良形トランジスタ設計
CN112038391A (zh) * 2019-06-03 2020-12-04 上海先进半导体制造股份有限公司 超结场效应晶体管的制作方法
CN114695093A (zh) * 2020-12-29 2022-07-01 芯恩（青岛）集成电路有限公司 一种阱离子注入方法
CN114695094A (zh) * 2020-12-29 2022-07-01 芯恩（青岛）集成电路有限公司 一种抑制wpe的阱离子注入方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007036249A (ja) * 2005-07-26 2007-02-08 Dongbu Electronics Co Ltd 半導体素子のウェルフォトレジストパターン及びその形成方法
JP2007305858A (ja) * 2006-05-12 2007-11-22 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007036249A (ja) * 2005-07-26 2007-02-08 Dongbu Electronics Co Ltd 半導体素子のウェルフォトレジストパターン及びその形成方法
JP2007305858A (ja) * 2006-05-12 2007-11-22 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JPN6013037273; Ｉｇｏｒ　Ｐｏｌｉｓｈｃｈｕｋ: 'ＣＭＯＳ　Ｖｔ-Ｃｏｎｔｒｏｌ　Ｉｍｐｒｏｖｅｍｅｎｔ　ｔｈｒｏｕｇｈ　Ｉｍｐｌａｎｔ　Ｌａｔｅｒａｌ　Ｓｃａｔｔｅｒ　Ｅｌｉｍｉｎａｔｉｏｎ' ＩＥＥＥ　Ｉｎｔｅｒｎａｔｉｏｎａｌ　Ｓｙｍｐｏｓｉｕｍ　ｏｎ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｍａｎｕｆａｃｔｕｒｉｎｇ , 200509, １９３-１９６頁 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019067480A (ja) * 2013-03-14 2019-04-25 シリコン ストーリッジ テクノロージー インコーポレイテッドＳｉｌｉｃｏｎ Ｓｔｏｒａｇｅ Ｔｅｃｈｎｏｌｏｇｙ， Ｉｎｃ． 高度ナノメートルフラッシュメモリ装置において使用される改良形トランジスタ設計
CN112038391A (zh) * 2019-06-03 2020-12-04 上海先进半导体制造股份有限公司 超结场效应晶体管的制作方法
CN112038391B (zh) * 2019-06-03 2024-05-24 上海先进半导体制造有限公司 超结场效应晶体管的制作方法
CN114695093A (zh) * 2020-12-29 2022-07-01 芯恩（青岛）集成电路有限公司 一种阱离子注入方法
CN114695094A (zh) * 2020-12-29 2022-07-01 芯恩（青岛）集成电路有限公司 一种抑制wpe的阱离子注入方法
CN114695094B (zh) * 2020-12-29 2025-07-25 芯恩（青岛）集成电路有限公司 一种抑制wpe的阱离子注入方法

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